drivers/pinctrl/tegra/pinctrl-tegra.c

   1 /*
   2  * Driver for the NVIDIA Tegra pinmux
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Derived from code:
   7  * Copyright (C) 2010 Google, Inc.
   8  * Copyright (C) 2010 NVIDIA Corporation
   9  * Copyright (C) 2009-2011 ST-Ericsson AB
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  */
  20
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf.h>
  30 #include <linux/slab.h>
  31
  32 #include "../core.h"
  33 #include "../pinctrl-utils.h"
  34 #include "pinctrl-tegra.h"
  35
  36 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  37 {
  38         return readl(pmx->regs[bank] + reg);
  39 }
  40
  41 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  42 {
  43         writel_relaxed(val, pmx->regs[bank] + reg);
  44         /* make sure pinmux register write completed */
  45         pmx_readl(pmx, bank, reg);
  46 }
  47
  48 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  49 {
  50         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  51
  52         return pmx->soc->ngroups;
  53 }
  54
  55 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  56                                                 unsigned group)
  57 {
  58         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  59
  60         return pmx->soc->groups[group].name;
  61 }
  62
  63 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  64                                         unsigned group,
  65                                         const unsigned **pins,
  66                                         unsigned *num_pins)
  67 {
  68         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  69
  70         *pins = pmx->soc->groups[group].pins;
  71         *num_pins = pmx->soc->groups[group].npins;
  72
  73         return 0;
  74 }
  75
  76 #ifdef CONFIG_DEBUG_FS
  77 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  78                                        struct seq_file *s,
  79                                        unsigned offset)
  80 {
  81         seq_printf(s, " %s", dev_name(pctldev->dev));
  82 }
  83 #endif
  84
  85 static const struct cfg_param {
  86         const char *property;
  87         enum tegra_pinconf_param param;
  88 } cfg_params[] = {
  89         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  90         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  91         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  92         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  93         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  94         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  95         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  96         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  97         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  98         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  99         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 100         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 101         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 102         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 103         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 104         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 105 };
 106
 107 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 108                                            struct device_node *np,
 109                                            struct pinctrl_map **map,
 110                                            unsigned *reserved_maps,
 111                                            unsigned *num_maps)
 112 {
 113         struct device *dev = pctldev->dev;
 114         int ret, i;
 115         const char *function;
 116         u32 val;
 117         unsigned long config;
 118         unsigned long *configs = NULL;
 119         unsigned num_configs = 0;
 120         unsigned reserve;
 121         struct property *prop;
 122         const char *group;
 123
 124         ret = of_property_read_string(np, "nvidia,function", &function);
 125         if (ret < 0) {
 126                 /* EINVAL=missing, which is fine since it's optional */
 127                 if (ret != -EINVAL)
 128                         dev_err(dev,
 129                                 "could not parse property nvidia,function\n");
 130                 function = NULL;
 131         }
 132
 133         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 134                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 135                 if (!ret) {
 136                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 137                         ret = pinctrl_utils_add_config(pctldev, &configs,
 138                                         &num_configs, config);
 139                         if (ret < 0)
 140                                 goto exit;
 141                 /* EINVAL=missing, which is fine since it's optional */
 142                 } else if (ret != -EINVAL) {
 143                         dev_err(dev, "could not parse property %s\n",
 144                                 cfg_params[i].property);
 145                 }
 146         }
 147
 148         reserve = 0;
 149         if (function != NULL)
 150                 reserve++;
 151         if (num_configs)
 152                 reserve++;
 153         ret = of_property_count_strings(np, "nvidia,pins");
 154         if (ret < 0) {
 155                 dev_err(dev, "could not parse property nvidia,pins\n");
 156                 goto exit;
 157         }
 158         reserve *= ret;
 159
 160         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 161                                         num_maps, reserve);
 162         if (ret < 0)
 163                 goto exit;
 164
 165         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 166                 if (function) {
 167                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 168                                         reserved_maps, num_maps, group,
 169                                         function);
 170                         if (ret < 0)
 171                                 goto exit;
 172                 }
 173
 174                 if (num_configs) {
 175                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 176                                         reserved_maps, num_maps, group,
 177                                         configs, num_configs,
 178                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 179                         if (ret < 0)
 180                                 goto exit;
 181                 }
 182         }
 183
 184         ret = 0;
 185
 186 exit:
 187         kfree(configs);
 188         return ret;
 189 }
 190
 191 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 192                                         struct device_node *np_config,
 193                                         struct pinctrl_map **map,
 194                                         unsigned *num_maps)
 195 {
 196         unsigned reserved_maps;
 197         struct device_node *np;
 198         int ret;
 199
 200         reserved_maps = 0;
 201         *map = NULL;
 202         *num_maps = 0;
 203
 204         for_each_child_of_node(np_config, np) {
 205                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 206                                                       &reserved_maps, num_maps);
 207                 if (ret < 0) {
 208                         pinctrl_utils_free_map(pctldev, *map,
 209                                 *num_maps);
 210                         of_node_put(np);
 211                         return ret;
 212                 }
 213         }
 214
 215         return 0;
 216 }
 217
 218 static const struct pinctrl_ops tegra_pinctrl_ops = {
 219         .get_groups_count = tegra_pinctrl_get_groups_count,
 220         .get_group_name = tegra_pinctrl_get_group_name,
 221         .get_group_pins = tegra_pinctrl_get_group_pins,
 222 #ifdef CONFIG_DEBUG_FS
 223         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 224 #endif
 225         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 226         .dt_free_map = pinctrl_utils_free_map,
 227 };
 228
 229 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 230 {
 231         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 232
 233         return pmx->soc->nfunctions;
 234 }
 235
 236 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 237                                                unsigned function)
 238 {
 239         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 240
 241         return pmx->soc->functions[function].name;
 242 }
 243
 244 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 245                                          unsigned function,
 246                                          const char * const **groups,
 247                                          unsigned * const num_groups)
 248 {
 249         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 250
 251         *groups = pmx->soc->functions[function].groups;
 252         *num_groups = pmx->soc->functions[function].ngroups;
 253
 254         return 0;
 255 }
 256
 257 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 258                                  unsigned function,
 259                                  unsigned group)
 260 {
 261         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 262         const struct tegra_pingroup *g;
 263         int i;
 264         u32 val;
 265
 266         g = &pmx->soc->groups[group];
 267
 268         if (WARN_ON(g->mux_reg < 0))
 269                 return -EINVAL;
 270
 271         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 272                 if (g->funcs[i] == function)
 273                         break;
 274         }
 275         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 276                 return -EINVAL;
 277
 278         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 279         val &= ~(0x3 << g->mux_bit);
 280         val |= i << g->mux_bit;
 281         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 282
 283         return 0;
 284 }
 285
 286 static const struct pinmux_ops tegra_pinmux_ops = {
 287         .get_functions_count = tegra_pinctrl_get_funcs_count,
 288         .get_function_name = tegra_pinctrl_get_func_name,
 289         .get_function_groups = tegra_pinctrl_get_func_groups,
 290         .set_mux = tegra_pinctrl_set_mux,
 291 };
 292
 293 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 294                              const struct tegra_pingroup *g,
 295                              enum tegra_pinconf_param param,
 296                              bool report_err,
 297                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 298 {
 299         switch (param) {
 300         case TEGRA_PINCONF_PARAM_PULL:
 301                 *bank = g->pupd_bank;
 302                 *reg = g->pupd_reg;
 303                 *bit = g->pupd_bit;
 304                 *width = 2;
 305                 break;
 306         case TEGRA_PINCONF_PARAM_TRISTATE:
 307                 *bank = g->tri_bank;
 308                 *reg = g->tri_reg;
 309                 *bit = g->tri_bit;
 310                 *width = 1;
 311                 break;
 312         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 313                 *bank = g->mux_bank;
 314                 *reg = g->mux_reg;
 315                 *bit = g->einput_bit;
 316                 *width = 1;
 317                 break;
 318         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 319                 *bank = g->mux_bank;
 320                 *reg = g->mux_reg;
 321                 *bit = g->odrain_bit;
 322                 *width = 1;
 323                 break;
 324         case TEGRA_PINCONF_PARAM_LOCK:
 325                 *bank = g->mux_bank;
 326                 *reg = g->mux_reg;
 327                 *bit = g->lock_bit;
 328                 *width = 1;
 329                 break;
 330         case TEGRA_PINCONF_PARAM_IORESET:
 331                 *bank = g->mux_bank;
 332                 *reg = g->mux_reg;
 333                 *bit = g->ioreset_bit;
 334                 *width = 1;
 335                 break;
 336         case TEGRA_PINCONF_PARAM_RCV_SEL:
 337                 *bank = g->mux_bank;
 338                 *reg = g->mux_reg;
 339                 *bit = g->rcv_sel_bit;
 340                 *width = 1;
 341                 break;
 342         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 343                 if (pmx->soc->hsm_in_mux) {
 344                         *bank = g->mux_bank;
 345                         *reg = g->mux_reg;
 346                 } else {
 347                         *bank = g->drv_bank;
 348                         *reg = g->drv_reg;
 349                 }
 350                 *bit = g->hsm_bit;
 351                 *width = 1;
 352                 break;
 353         case TEGRA_PINCONF_PARAM_SCHMITT:
 354                 if (pmx->soc->schmitt_in_mux) {
 355                         *bank = g->mux_bank;
 356                         *reg = g->mux_reg;
 357                 } else {
 358                         *bank = g->drv_bank;
 359                         *reg = g->drv_reg;
 360                 }
 361                 *bit = g->schmitt_bit;
 362                 *width = 1;
 363                 break;
 364         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 365                 *bank = g->drv_bank;
 366                 *reg = g->drv_reg;
 367                 *bit = g->lpmd_bit;
 368                 *width = 2;
 369                 break;
 370         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 371                 *bank = g->drv_bank;
 372                 *reg = g->drv_reg;
 373                 *bit = g->drvdn_bit;
 374                 *width = g->drvdn_width;
 375                 break;
 376         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 377                 *bank = g->drv_bank;
 378                 *reg = g->drv_reg;
 379                 *bit = g->drvup_bit;
 380                 *width = g->drvup_width;
 381                 break;
 382         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 383                 *bank = g->drv_bank;
 384                 *reg = g->drv_reg;
 385                 *bit = g->slwf_bit;
 386                 *width = g->slwf_width;
 387                 break;
 388         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 389                 *bank = g->drv_bank;
 390                 *reg = g->drv_reg;
 391                 *bit = g->slwr_bit;
 392                 *width = g->slwr_width;
 393                 break;
 394         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 395                 if (pmx->soc->drvtype_in_mux) {
 396                         *bank = g->mux_bank;
 397                         *reg = g->mux_reg;
 398                 } else {
 399                         *bank = g->drv_bank;
 400                         *reg = g->drv_reg;
 401                 }
 402                 *bit = g->drvtype_bit;
 403                 *width = 2;
 404                 break;
 405         default:
 406                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 407                 return -ENOTSUPP;
 408         }
 409
 410         if (*reg < 0 || *bit < 0)  {
 411                 if (report_err) {
 412                         const char *prop = "unknown";
 413                         int i;
 414
 415                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 416                                 if (cfg_params[i].param == param) {
 417                                         prop = cfg_params[i].property;
 418                                         break;
 419                                 }
 420                         }
 421
 422                         dev_err(pmx->dev,
 423                                 "Config param %04x (%s) not supported on group %s\n",
 424                                 param, prop, g->name);
 425                 }
 426                 return -ENOTSUPP;
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 433                              unsigned pin, unsigned long *config)
 434 {
 435         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 436         return -ENOTSUPP;
 437 }
 438
 439 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 440                              unsigned pin, unsigned long *configs,
 441                              unsigned num_configs)
 442 {
 443         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 444         return -ENOTSUPP;
 445 }
 446
 447 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 448                                    unsigned group, unsigned long *config)
 449 {
 450         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 451         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 452         u16 arg;
 453         const struct tegra_pingroup *g;
 454         int ret;
 455         s8 bank, bit, width;
 456         s16 reg;
 457         u32 val, mask;
 458
 459         g = &pmx->soc->groups[group];
 460
 461         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 462                                 &width);
 463         if (ret < 0)
 464                 return ret;
 465
 466         val = pmx_readl(pmx, bank, reg);
 467         mask = (1 << width) - 1;
 468         arg = (val >> bit) & mask;
 469
 470         *config = TEGRA_PINCONF_PACK(param, arg);
 471
 472         return 0;
 473 }
 474
 475 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 476                                    unsigned group, unsigned long *configs,
 477                                    unsigned num_configs)
 478 {
 479         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 480         enum tegra_pinconf_param param;
 481         u16 arg;
 482         const struct tegra_pingroup *g;
 483         int ret, i;
 484         s8 bank, bit, width;
 485         s16 reg;
 486         u32 val, mask;
 487
 488         g = &pmx->soc->groups[group];
 489
 490         for (i = 0; i < num_configs; i++) {
 491                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 492                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 493
 494                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 495                                         &width);
 496                 if (ret < 0)
 497                         return ret;
 498
 499                 val = pmx_readl(pmx, bank, reg);
 500
 501                 /* LOCK can't be cleared */
 502                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 503                         if ((val & BIT(bit)) && !arg) {
 504                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 505                                 return -EINVAL;
 506                         }
 507                 }
 508
 509                 /* Special-case Boolean values; allow any non-zero as true */
 510                 if (width == 1)
 511                         arg = !!arg;
 512
 513                 /* Range-check user-supplied value */
 514                 mask = (1 << width) - 1;
 515                 if (arg & ~mask) {
 516                         dev_err(pctldev->dev,
 517                                 "config %lx: %x too big for %d bit register\n",
 518                                 configs[i], arg, width);
 519                         return -EINVAL;
 520                 }
 521
 522                 /* Update register */
 523                 val &= ~(mask << bit);
 524                 val |= arg << bit;
 525                 pmx_writel(pmx, val, bank, reg);
 526         } /* for each config */
 527
 528         return 0;
 529 }
 530
 531 #ifdef CONFIG_DEBUG_FS
 532 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 533                                    struct seq_file *s, unsigned offset)
 534 {
 535 }
 536
 537 static const char *strip_prefix(const char *s)
 538 {
 539         const char *comma = strchr(s, ',');
 540         if (!comma)
 541                 return s;
 542
 543         return comma + 1;
 544 }
 545
 546 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 547                                          struct seq_file *s, unsigned group)
 548 {
 549         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 550         const struct tegra_pingroup *g;
 551         int i, ret;
 552         s8 bank, bit, width;
 553         s16 reg;
 554         u32 val;
 555
 556         g = &pmx->soc->groups[group];
 557
 558         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 559                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 560                                         &bank, &reg, &bit, &width);
 561                 if (ret < 0)
 562                         continue;
 563
 564                 val = pmx_readl(pmx, bank, reg);
 565                 val >>= bit;
 566                 val &= (1 << width) - 1;
 567
 568                 seq_printf(s, "\n\t%s=%u",
 569                            strip_prefix(cfg_params[i].property), val);
 570         }
 571 }
 572
 573 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 574                                           struct seq_file *s,
 575                                           unsigned long config)
 576 {
 577         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 578         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 579         const char *pname = "unknown";
 580         int i;
 581
 582         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 583                 if (cfg_params[i].param == param) {
 584                         pname = cfg_params[i].property;
 585                         break;
 586                 }
 587         }
 588
 589         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 590 }
 591 #endif
 592
 593 static const struct pinconf_ops tegra_pinconf_ops = {
 594         .pin_config_get = tegra_pinconf_get,
 595         .pin_config_set = tegra_pinconf_set,
 596         .pin_config_group_get = tegra_pinconf_group_get,
 597         .pin_config_group_set = tegra_pinconf_group_set,
 598 #ifdef CONFIG_DEBUG_FS
 599         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 600         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 601         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 602 #endif
 603 };
 604
 605 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 606         .name = "Tegra GPIOs",
 607         .id = 0,
 608         .base = 0,
 609 };
 610
 611 static struct pinctrl_desc tegra_pinctrl_desc = {
 612         .pctlops = &tegra_pinctrl_ops,
 613         .pmxops = &tegra_pinmux_ops,
 614         .confops = &tegra_pinconf_ops,
 615         .owner = THIS_MODULE,
 616 };
 617
 618 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 619 {
 620         int i = 0;
 621         const struct tegra_pingroup *g;
 622         u32 val;
 623
 624         for (i = 0; i < pmx->soc->ngroups; ++i) {
 625                 g = &pmx->soc->groups[i];
 626                 if (g->parked_bit >= 0) {
 627                         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 628                         val &= ~(1 << g->parked_bit);
 629                         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 630                 }
 631         }
 632 }
 633
 634 static bool gpio_node_has_range(const char *compatible)
 635 {
 636         struct device_node *np;
 637         bool has_prop = false;
 638
 639         np = of_find_compatible_node(NULL, NULL, compatible);
 640         if (!np)
 641                 return has_prop;
 642
 643         has_prop = of_find_property(np, "gpio-ranges", NULL);
 644
 645         of_node_put(np);
 646
 647         return has_prop;
 648 }
 649
 650 int tegra_pinctrl_probe(struct platform_device *pdev,
 651                         const struct tegra_pinctrl_soc_data *soc_data)
 652 {
 653         struct tegra_pmx *pmx;
 654         struct resource *res;
 655         int i;
 656         const char **group_pins;
 657         int fn, gn, gfn;
 658
 659         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 660         if (!pmx)
 661                 return -ENOMEM;
 662
 663         pmx->dev = &pdev->dev;
 664         pmx->soc = soc_data;
 665
 666         /*
 667          * Each mux group will appear in 4 functions' list of groups.
 668          * This over-allocates slightly, since not all groups are mux groups.
 669          */
 670         pmx->group_pins = devm_kcalloc(&pdev->dev,
 671                 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
 672                 GFP_KERNEL);
 673         if (!pmx->group_pins)
 674                 return -ENOMEM;
 675
 676         group_pins = pmx->group_pins;
 677         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 678                 struct tegra_function *func = &soc_data->functions[fn];
 679
 680                 func->groups = group_pins;
 681
 682                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 683                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 684
 685                         if (g->mux_reg == -1)
 686                                 continue;
 687
 688                         for (gfn = 0; gfn < 4; gfn++)
 689                                 if (g->funcs[gfn] == fn)
 690                                         break;
 691                         if (gfn == 4)
 692                                 continue;
 693
 694                         BUG_ON(group_pins - pmx->group_pins >=
 695                                 soc_data->ngroups * 4);
 696                         *group_pins++ = g->name;
 697                         func->ngroups++;
 698                 }
 699         }
 700
 701         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 702         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 703         tegra_pinctrl_desc.pins = pmx->soc->pins;
 704         tegra_pinctrl_desc.npins = pmx->soc->npins;
 705
 706         for (i = 0; ; i++) {
 707                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 708                 if (!res)
 709                         break;
 710         }
 711         pmx->nbanks = i;
 712
 713         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 714                                  GFP_KERNEL);
 715         if (!pmx->regs)
 716                 return -ENOMEM;
 717
 718         for (i = 0; i < pmx->nbanks; i++) {
 719                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 720                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
 721                 if (IS_ERR(pmx->regs[i]))
 722                         return PTR_ERR(pmx->regs[i]);
 723         }
 724
 725         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 726         if (IS_ERR(pmx->pctl)) {
 727                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 728                 return PTR_ERR(pmx->pctl);
 729         }
 730
 731         tegra_pinctrl_clear_parked_bits(pmx);
 732
 733         if (!gpio_node_has_range(pmx->soc->gpio_compatible))
 734                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 735
 736         platform_set_drvdata(pdev, pmx);
 737
 738         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 739
 740         return 0;
 741 }
 742 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);