2 * Copyright (C) 2016 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
24 #define IPROC_PWM_CTRL_OFFSET 0x00
25 #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch))
26 #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch))
27 #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch)
29 #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3))
30 #define IPROC_PWM_PERIOD_MIN 0x02
31 #define IPROC_PWM_PERIOD_MAX 0xffff
33 #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3))
34 #define IPROC_PWM_DUTY_CYCLE_MIN 0x00
35 #define IPROC_PWM_DUTY_CYCLE_MAX 0xffff
37 #define IPROC_PWM_PRESCALE_OFFSET 0x24
38 #define IPROC_PWM_PRESCALE_BITS 0x06
39 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
40 IPROC_PWM_PRESCALE_BITS)
41 #define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \
42 IPROC_PWM_PRESCALE_SHIFT(ch))
43 #define IPROC_PWM_PRESCALE_MIN 0x00
44 #define IPROC_PWM_PRESCALE_MAX 0x3f
52 static inline struct iproc_pwmc
*to_iproc_pwmc(struct pwm_chip
*chip
)
54 return container_of(chip
, struct iproc_pwmc
, chip
);
57 static void iproc_pwmc_enable(struct iproc_pwmc
*ip
, unsigned int channel
)
61 value
= readl(ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
62 value
|= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel
);
63 writel(value
, ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
65 /* must be a 400 ns delay between clearing and setting enable bit */
69 static void iproc_pwmc_disable(struct iproc_pwmc
*ip
, unsigned int channel
)
73 value
= readl(ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
74 value
&= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel
));
75 writel(value
, ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
77 /* must be a 400 ns delay between clearing and setting enable bit */
81 static void iproc_pwmc_get_state(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
82 struct pwm_state
*state
)
84 struct iproc_pwmc
*ip
= to_iproc_pwmc(chip
);
88 rate
= clk_get_rate(ip
->clk
);
90 value
= readl(ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
92 if (value
& BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm
->hwpwm
)))
93 state
->enabled
= true;
95 state
->enabled
= false;
97 if (value
& BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm
->hwpwm
)))
98 state
->polarity
= PWM_POLARITY_NORMAL
;
100 state
->polarity
= PWM_POLARITY_INVERSED
;
102 value
= readl(ip
->base
+ IPROC_PWM_PRESCALE_OFFSET
);
103 prescale
= value
>> IPROC_PWM_PRESCALE_SHIFT(pwm
->hwpwm
);
104 prescale
&= IPROC_PWM_PRESCALE_MAX
;
106 multi
= NSEC_PER_SEC
* (prescale
+ 1);
108 value
= readl(ip
->base
+ IPROC_PWM_PERIOD_OFFSET(pwm
->hwpwm
));
109 tmp
= (value
& IPROC_PWM_PERIOD_MAX
) * multi
;
110 state
->period
= div64_u64(tmp
, rate
);
112 value
= readl(ip
->base
+ IPROC_PWM_DUTY_CYCLE_OFFSET(pwm
->hwpwm
));
113 tmp
= (value
& IPROC_PWM_PERIOD_MAX
) * multi
;
114 state
->duty_cycle
= div64_u64(tmp
, rate
);
117 static int iproc_pwmc_apply(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
118 struct pwm_state
*state
)
120 unsigned long prescale
= IPROC_PWM_PRESCALE_MIN
;
121 struct iproc_pwmc
*ip
= to_iproc_pwmc(chip
);
122 u32 value
, period
, duty
;
125 rate
= clk_get_rate(ip
->clk
);
128 * Find period count, duty count and prescale to suit duty_cycle and
129 * period. This is done according to formulas described below:
131 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
132 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
134 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
135 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
140 div
= NSEC_PER_SEC
* (prescale
+ 1);
141 value
= rate
* state
->period
;
142 period
= div64_u64(value
, div
);
143 value
= rate
* state
->duty_cycle
;
144 duty
= div64_u64(value
, div
);
146 if (period
< IPROC_PWM_PERIOD_MIN
||
147 duty
< IPROC_PWM_DUTY_CYCLE_MIN
)
150 if (period
<= IPROC_PWM_PERIOD_MAX
&&
151 duty
<= IPROC_PWM_DUTY_CYCLE_MAX
)
154 /* Otherwise, increase prescale and recalculate counts */
155 if (++prescale
> IPROC_PWM_PRESCALE_MAX
)
159 iproc_pwmc_disable(ip
, pwm
->hwpwm
);
162 value
= readl(ip
->base
+ IPROC_PWM_PRESCALE_OFFSET
);
163 value
&= ~IPROC_PWM_PRESCALE_MASK(pwm
->hwpwm
);
164 value
|= prescale
<< IPROC_PWM_PRESCALE_SHIFT(pwm
->hwpwm
);
165 writel(value
, ip
->base
+ IPROC_PWM_PRESCALE_OFFSET
);
167 /* set period and duty cycle */
168 writel(period
, ip
->base
+ IPROC_PWM_PERIOD_OFFSET(pwm
->hwpwm
));
169 writel(duty
, ip
->base
+ IPROC_PWM_DUTY_CYCLE_OFFSET(pwm
->hwpwm
));
172 value
= readl(ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
174 if (state
->polarity
== PWM_POLARITY_NORMAL
)
175 value
|= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm
->hwpwm
);
177 value
&= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm
->hwpwm
));
179 writel(value
, ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
182 iproc_pwmc_enable(ip
, pwm
->hwpwm
);
187 static const struct pwm_ops iproc_pwm_ops
= {
188 .apply
= iproc_pwmc_apply
,
189 .get_state
= iproc_pwmc_get_state
,
190 .owner
= THIS_MODULE
,
193 static int iproc_pwmc_probe(struct platform_device
*pdev
)
195 struct iproc_pwmc
*ip
;
196 struct resource
*res
;
201 ip
= devm_kzalloc(&pdev
->dev
, sizeof(*ip
), GFP_KERNEL
);
205 platform_set_drvdata(pdev
, ip
);
207 ip
->chip
.dev
= &pdev
->dev
;
208 ip
->chip
.ops
= &iproc_pwm_ops
;
211 ip
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
212 ip
->chip
.of_pwm_n_cells
= 3;
214 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
215 ip
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
216 if (IS_ERR(ip
->base
))
217 return PTR_ERR(ip
->base
);
219 ip
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
220 if (IS_ERR(ip
->clk
)) {
221 dev_err(&pdev
->dev
, "failed to get clock: %ld\n",
223 return PTR_ERR(ip
->clk
);
226 ret
= clk_prepare_enable(ip
->clk
);
228 dev_err(&pdev
->dev
, "failed to enable clock: %d\n", ret
);
232 /* Set full drive and normal polarity for all channels */
233 value
= readl(ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
235 for (i
= 0; i
< ip
->chip
.npwm
; i
++) {
236 value
&= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i
));
237 value
|= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i
);
240 writel(value
, ip
->base
+ IPROC_PWM_CTRL_OFFSET
);
242 ret
= pwmchip_add(&ip
->chip
);
244 dev_err(&pdev
->dev
, "failed to add PWM chip: %d\n", ret
);
245 clk_disable_unprepare(ip
->clk
);
251 static int iproc_pwmc_remove(struct platform_device
*pdev
)
253 struct iproc_pwmc
*ip
= platform_get_drvdata(pdev
);
255 clk_disable_unprepare(ip
->clk
);
257 return pwmchip_remove(&ip
->chip
);
260 static const struct of_device_id bcm_iproc_pwmc_dt
[] = {
261 { .compatible
= "brcm,iproc-pwm" },
264 MODULE_DEVICE_TABLE(of
, bcm_iproc_pwmc_dt
);
266 static struct platform_driver iproc_pwmc_driver
= {
268 .name
= "bcm-iproc-pwm",
269 .of_match_table
= bcm_iproc_pwmc_dt
,
271 .probe
= iproc_pwmc_probe
,
272 .remove
= iproc_pwmc_remove
,
274 module_platform_driver(iproc_pwmc_driver
);
276 MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>");
277 MODULE_DESCRIPTION("Broadcom iProc PWM driver");
278 MODULE_LICENSE("GPL v2");