drivers/pwm/pwm-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * simple driver for PWM (Pulse Width Modulator) controller
   4  *
   5  * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12 #include <linux/err.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/pwm.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19
  20 /* i.MX1 and i.MX21 share the same PWM function block: */
  21
  22 #define MX1_PWMC                        0x00   /* PWM Control Register */
  23 #define MX1_PWMS                        0x04   /* PWM Sample Register */
  24 #define MX1_PWMP                        0x08   /* PWM Period Register */
  25
  26 #define MX1_PWMC_EN                     (1 << 4)
  27
  28 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
  29
  30 #define MX3_PWMCR                       0x00    /* PWM Control Register */
  31 #define MX3_PWMSR                       0x04    /* PWM Status Register */
  32 #define MX3_PWMSAR                      0x0C    /* PWM Sample Register */
  33 #define MX3_PWMPR                       0x10    /* PWM Period Register */
  34 #define MX3_PWMCR_PRESCALER(x)          ((((x) - 1) & 0xFFF) << 4)
  35 #define MX3_PWMCR_STOPEN                (1 << 25)
  36 #define MX3_PWMCR_DOZEEN                (1 << 24)
  37 #define MX3_PWMCR_WAITEN                (1 << 23)
  38 #define MX3_PWMCR_DBGEN                 (1 << 22)
  39 #define MX3_PWMCR_POUTC                 (1 << 18)
  40 #define MX3_PWMCR_CLKSRC_IPG_HIGH       (2 << 16)
  41 #define MX3_PWMCR_CLKSRC_IPG            (1 << 16)
  42 #define MX3_PWMCR_SWR                   (1 << 3)
  43 #define MX3_PWMCR_EN                    (1 << 0)
  44 #define MX3_PWMSR_FIFOAV_4WORDS         0x4
  45 #define MX3_PWMSR_FIFOAV_MASK           0x7
  46
  47 #define MX3_PWM_SWR_LOOP                5
  48
  49 struct imx_chip {
  50         struct clk      *clk_per;
  51
  52         void __iomem    *mmio_base;
  53
  54         struct pwm_chip chip;
  55 };
  56
  57 #define to_imx_chip(chip)       container_of(chip, struct imx_chip, chip)
  58
  59 static int imx_pwm_config_v1(struct pwm_chip *chip,
  60                 struct pwm_device *pwm, int duty_ns, int period_ns)
  61 {
  62         struct imx_chip *imx = to_imx_chip(chip);
  63
  64         /*
  65          * The PWM subsystem allows for exact frequencies. However,
  66          * I cannot connect a scope on my device to the PWM line and
  67          * thus cannot provide the program the PWM controller
  68          * exactly. Instead, I'm relying on the fact that the
  69          * Bootloader (u-boot or WinCE+haret) has programmed the PWM
  70          * function group already. So I'll just modify the PWM sample
  71          * register to follow the ratio of duty_ns vs. period_ns
  72          * accordingly.
  73          *
  74          * This is good enough for programming the brightness of
  75          * the LCD backlight.
  76          *
  77          * The real implementation would divide PERCLK[0] first by
  78          * both the prescaler (/1 .. /128) and then by CLKSEL
  79          * (/2 .. /16).
  80          */
  81         u32 max = readl(imx->mmio_base + MX1_PWMP);
  82         u32 p = max * duty_ns / period_ns;
  83         writel(max - p, imx->mmio_base + MX1_PWMS);
  84
  85         return 0;
  86 }
  87
  88 static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
  89 {
  90         struct imx_chip *imx = to_imx_chip(chip);
  91         u32 val;
  92         int ret;
  93
  94         ret = clk_prepare_enable(imx->clk_per);
  95         if (ret < 0)
  96                 return ret;
  97
  98         val = readl(imx->mmio_base + MX1_PWMC);
  99         val |= MX1_PWMC_EN;
 100         writel(val, imx->mmio_base + MX1_PWMC);
 101
 102         return 0;
 103 }
 104
 105 static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 106 {
 107         struct imx_chip *imx = to_imx_chip(chip);
 108         u32 val;
 109
 110         val = readl(imx->mmio_base + MX1_PWMC);
 111         val &= ~MX1_PWMC_EN;
 112         writel(val, imx->mmio_base + MX1_PWMC);
 113
 114         clk_disable_unprepare(imx->clk_per);
 115 }
 116
 117 static void imx_pwm_sw_reset(struct pwm_chip *chip)
 118 {
 119         struct imx_chip *imx = to_imx_chip(chip);
 120         struct device *dev = chip->dev;
 121         int wait_count = 0;
 122         u32 cr;
 123
 124         writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
 125         do {
 126                 usleep_range(200, 1000);
 127                 cr = readl(imx->mmio_base + MX3_PWMCR);
 128         } while ((cr & MX3_PWMCR_SWR) &&
 129                  (wait_count++ < MX3_PWM_SWR_LOOP));
 130
 131         if (cr & MX3_PWMCR_SWR)
 132                 dev_warn(dev, "software reset timeout\n");
 133 }
 134
 135 static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
 136                                    struct pwm_device *pwm)
 137 {
 138         struct imx_chip *imx = to_imx_chip(chip);
 139         struct device *dev = chip->dev;
 140         unsigned int period_ms;
 141         int fifoav;
 142         u32 sr;
 143
 144         sr = readl(imx->mmio_base + MX3_PWMSR);
 145         fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
 146         if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
 147                 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
 148                                          NSEC_PER_MSEC);
 149                 msleep(period_ms);
 150
 151                 sr = readl(imx->mmio_base + MX3_PWMSR);
 152                 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
 153                         dev_warn(dev, "there is no free FIFO slot\n");
 154         }
 155 }
 156
 157 static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
 158                             struct pwm_state *state)
 159 {
 160         unsigned long period_cycles, duty_cycles, prescale;
 161         struct imx_chip *imx = to_imx_chip(chip);
 162         struct pwm_state cstate;
 163         unsigned long long c;
 164         int ret;
 165         u32 cr;
 166
 167         pwm_get_state(pwm, &cstate);
 168
 169         if (state->enabled) {
 170                 c = clk_get_rate(imx->clk_per);
 171                 c *= state->period;
 172
 173                 do_div(c, 1000000000);
 174                 period_cycles = c;
 175
 176                 prescale = period_cycles / 0x10000 + 1;
 177
 178                 period_cycles /= prescale;
 179                 c = (unsigned long long)period_cycles * state->duty_cycle;
 180                 do_div(c, state->period);
 181                 duty_cycles = c;
 182
 183                 /*
 184                  * according to imx pwm RM, the real period value should be
 185                  * PERIOD value in PWMPR plus 2.
 186                  */
 187                 if (period_cycles > 2)
 188                         period_cycles -= 2;
 189                 else
 190                         period_cycles = 0;
 191
 192                 /*
 193                  * Wait for a free FIFO slot if the PWM is already enabled, and
 194                  * flush the FIFO if the PWM was disabled and is about to be
 195                  * enabled.
 196                  */
 197                 if (cstate.enabled) {
 198                         imx_pwm_wait_fifo_slot(chip, pwm);
 199                 } else {
 200                         ret = clk_prepare_enable(imx->clk_per);
 201                         if (ret)
 202                                 return ret;
 203
 204                         imx_pwm_sw_reset(chip);
 205                 }
 206
 207                 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
 208                 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 209
 210                 cr = MX3_PWMCR_PRESCALER(prescale) |
 211                      MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
 212                      MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
 213                      MX3_PWMCR_EN;
 214
 215                 if (state->polarity == PWM_POLARITY_INVERSED)
 216                         cr |= MX3_PWMCR_POUTC;
 217
 218                 writel(cr, imx->mmio_base + MX3_PWMCR);
 219         } else if (cstate.enabled) {
 220                 writel(0, imx->mmio_base + MX3_PWMCR);
 221
 222                 clk_disable_unprepare(imx->clk_per);
 223         }
 224
 225         return 0;
 226 }
 227
 228 static const struct pwm_ops imx_pwm_ops_v1 = {
 229         .enable = imx_pwm_enable_v1,
 230         .disable = imx_pwm_disable_v1,
 231         .config = imx_pwm_config_v1,
 232         .owner = THIS_MODULE,
 233 };
 234
 235 static const struct pwm_ops imx_pwm_ops_v2 = {
 236         .apply = imx_pwm_apply_v2,
 237         .owner = THIS_MODULE,
 238 };
 239
 240 struct imx_pwm_data {
 241         bool polarity_supported;
 242         const struct pwm_ops *ops;
 243 };
 244
 245 static struct imx_pwm_data imx_pwm_data_v1 = {
 246         .ops = &imx_pwm_ops_v1,
 247 };
 248
 249 static struct imx_pwm_data imx_pwm_data_v2 = {
 250         .polarity_supported = true,
 251         .ops = &imx_pwm_ops_v2,
 252 };
 253
 254 static const struct of_device_id imx_pwm_dt_ids[] = {
 255         { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
 256         { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
 257         { /* sentinel */ }
 258 };
 259 MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
 260
 261 static int imx_pwm_probe(struct platform_device *pdev)
 262 {
 263         const struct of_device_id *of_id =
 264                         of_match_device(imx_pwm_dt_ids, &pdev->dev);
 265         const struct imx_pwm_data *data;
 266         struct imx_chip *imx;
 267         struct resource *r;
 268         int ret = 0;
 269
 270         if (!of_id)
 271                 return -ENODEV;
 272
 273         data = of_id->data;
 274
 275         imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
 276         if (imx == NULL)
 277                 return -ENOMEM;
 278
 279         imx->clk_per = devm_clk_get(&pdev->dev, "per");
 280         if (IS_ERR(imx->clk_per)) {
 281                 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
 282                                 PTR_ERR(imx->clk_per));
 283                 return PTR_ERR(imx->clk_per);
 284         }
 285
 286         imx->chip.ops = data->ops;
 287         imx->chip.dev = &pdev->dev;
 288         imx->chip.base = -1;
 289         imx->chip.npwm = 1;
 290
 291         if (data->polarity_supported) {
 292                 dev_dbg(&pdev->dev, "PWM supports output inversion\n");
 293                 imx->chip.of_xlate = of_pwm_xlate_with_flags;
 294                 imx->chip.of_pwm_n_cells = 3;
 295         }
 296
 297         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 298         imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 299         if (IS_ERR(imx->mmio_base))
 300                 return PTR_ERR(imx->mmio_base);
 301
 302         ret = pwmchip_add(&imx->chip);
 303         if (ret < 0)
 304                 return ret;
 305
 306         platform_set_drvdata(pdev, imx);
 307         return 0;
 308 }
 309
 310 static int imx_pwm_remove(struct platform_device *pdev)
 311 {
 312         struct imx_chip *imx;
 313
 314         imx = platform_get_drvdata(pdev);
 315         if (imx == NULL)
 316                 return -ENODEV;
 317
 318         return pwmchip_remove(&imx->chip);
 319 }
 320
 321 static struct platform_driver imx_pwm_driver = {
 322         .driver         = {
 323                 .name   = "imx-pwm",
 324                 .of_match_table = imx_pwm_dt_ids,
 325         },
 326         .probe          = imx_pwm_probe,
 327         .remove         = imx_pwm_remove,
 328 };
 329
 330 module_platform_driver(imx_pwm_driver);
 331
 332 MODULE_LICENSE("GPL v2");
 333 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");