drivers/pwm/pwm-stm32-lp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STM32 Low-Power Timer PWM driver
   4  *
   5  * Copyright (C) STMicroelectronics 2017
   6  *
   7  * Author: Gerald Baeza <gerald.baeza@st.com>
   8  *
   9  * Inspired by Gerald Baeza's pwm-stm32 driver
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/mfd/stm32-lptimer.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pwm.h>
  18
  19 struct stm32_pwm_lp {
  20         struct pwm_chip chip;
  21         struct clk *clk;
  22         struct regmap *regmap;
  23 };
  24
  25 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
  26 {
  27         return container_of(chip, struct stm32_pwm_lp, chip);
  28 }
  29
  30 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
  31 #define STM32_LPTIM_MAX_PRESCALER       128
  32
  33 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  34                               struct pwm_state *state)
  35 {
  36         struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
  37         unsigned long long prd, div, dty;
  38         struct pwm_state cstate;
  39         u32 val, mask, cfgr, presc = 0;
  40         bool reenable;
  41         int ret;
  42
  43         pwm_get_state(pwm, &cstate);
  44         reenable = !cstate.enabled;
  45
  46         if (!state->enabled) {
  47                 if (cstate.enabled) {
  48                         /* Disable LP timer */
  49                         ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
  50                         if (ret)
  51                                 return ret;
  52                         /* disable clock to PWM counter */
  53                         clk_disable(priv->clk);
  54                 }
  55                 return 0;
  56         }
  57
  58         /* Calculate the period and prescaler value */
  59         div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
  60         do_div(div, NSEC_PER_SEC);
  61         if (!div) {
  62                 /* Clock is too slow to achieve requested period. */
  63                 dev_dbg(priv->chip.dev, "Can't reach %u ns\n",  state->period);
  64                 return -EINVAL;
  65         }
  66
  67         prd = div;
  68         while (div > STM32_LPTIM_MAX_ARR) {
  69                 presc++;
  70                 if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
  71                         dev_err(priv->chip.dev, "max prescaler exceeded\n");
  72                         return -EINVAL;
  73                 }
  74                 div = prd >> presc;
  75         }
  76         prd = div;
  77
  78         /* Calculate the duty cycle */
  79         dty = prd * state->duty_cycle;
  80         do_div(dty, state->period);
  81
  82         if (!cstate.enabled) {
  83                 /* enable clock to drive PWM counter */
  84                 ret = clk_enable(priv->clk);
  85                 if (ret)
  86                         return ret;
  87         }
  88
  89         ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
  90         if (ret)
  91                 goto err;
  92
  93         if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
  94             (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
  95                 val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
  96                 val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
  97                 mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
  98
  99                 /* Must disable LP timer to modify CFGR */
 100                 reenable = true;
 101                 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
 102                 if (ret)
 103                         goto err;
 104
 105                 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
 106                                          val);
 107                 if (ret)
 108                         goto err;
 109         }
 110
 111         if (reenable) {
 112                 /* Must (re)enable LP timer to modify CMP & ARR */
 113                 ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
 114                                    STM32_LPTIM_ENABLE);
 115                 if (ret)
 116                         goto err;
 117         }
 118
 119         ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
 120         if (ret)
 121                 goto err;
 122
 123         ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
 124         if (ret)
 125                 goto err;
 126
 127         /* ensure CMP & ARR registers are properly written */
 128         ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
 129                                        (val & STM32_LPTIM_CMPOK_ARROK),
 130                                        100, 1000);
 131         if (ret) {
 132                 dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
 133                 goto err;
 134         }
 135         ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
 136                            STM32_LPTIM_CMPOKCF_ARROKCF);
 137         if (ret)
 138                 goto err;
 139
 140         if (reenable) {
 141                 /* Start LP timer in continuous mode */
 142                 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
 143                                          STM32_LPTIM_CNTSTRT,
 144                                          STM32_LPTIM_CNTSTRT);
 145                 if (ret) {
 146                         regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
 147                         goto err;
 148                 }
 149         }
 150
 151         return 0;
 152 err:
 153         if (!cstate.enabled)
 154                 clk_disable(priv->clk);
 155
 156         return ret;
 157 }
 158
 159 static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
 160                                    struct pwm_device *pwm,
 161                                    struct pwm_state *state)
 162 {
 163         struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
 164         unsigned long rate = clk_get_rate(priv->clk);
 165         u32 val, presc, prd;
 166         u64 tmp;
 167
 168         regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
 169         state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
 170         /* Keep PWM counter clock refcount in sync with PWM initial state */
 171         if (state->enabled)
 172                 clk_enable(priv->clk);
 173
 174         regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
 175         presc = FIELD_GET(STM32_LPTIM_PRESC, val);
 176         state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val);
 177
 178         regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd);
 179         tmp = prd + 1;
 180         tmp = (tmp << presc) * NSEC_PER_SEC;
 181         state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
 182
 183         regmap_read(priv->regmap, STM32_LPTIM_CMP, &val);
 184         tmp = prd - val;
 185         tmp = (tmp << presc) * NSEC_PER_SEC;
 186         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
 187 }
 188
 189 static const struct pwm_ops stm32_pwm_lp_ops = {
 190         .owner = THIS_MODULE,
 191         .apply = stm32_pwm_lp_apply,
 192         .get_state = stm32_pwm_lp_get_state,
 193 };
 194
 195 static int stm32_pwm_lp_probe(struct platform_device *pdev)
 196 {
 197         struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
 198         struct stm32_pwm_lp *priv;
 199         int ret;
 200
 201         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 202         if (!priv)
 203                 return -ENOMEM;
 204
 205         priv->regmap = ddata->regmap;
 206         priv->clk = ddata->clk;
 207         priv->chip.base = -1;
 208         priv->chip.dev = &pdev->dev;
 209         priv->chip.ops = &stm32_pwm_lp_ops;
 210         priv->chip.npwm = 1;
 211         priv->chip.of_xlate = of_pwm_xlate_with_flags;
 212         priv->chip.of_pwm_n_cells = 3;
 213
 214         ret = pwmchip_add(&priv->chip);
 215         if (ret < 0)
 216                 return ret;
 217
 218         platform_set_drvdata(pdev, priv);
 219
 220         return 0;
 221 }
 222
 223 static int stm32_pwm_lp_remove(struct platform_device *pdev)
 224 {
 225         struct stm32_pwm_lp *priv = platform_get_drvdata(pdev);
 226
 227         pwm_disable(&priv->chip.pwms[0]);
 228
 229         return pwmchip_remove(&priv->chip);
 230 }
 231
 232 static const struct of_device_id stm32_pwm_lp_of_match[] = {
 233         { .compatible = "st,stm32-pwm-lp", },
 234         {},
 235 };
 236 MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match);
 237
 238 static struct platform_driver stm32_pwm_lp_driver = {
 239         .probe  = stm32_pwm_lp_probe,
 240         .remove = stm32_pwm_lp_remove,
 241         .driver = {
 242                 .name = "stm32-pwm-lp",
 243                 .of_match_table = of_match_ptr(stm32_pwm_lp_of_match),
 244         },
 245 };
 246 module_platform_driver(stm32_pwm_lp_driver);
 247
 248 MODULE_ALIAS("platform:stm32-pwm-lp");
 249 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver");
 250 MODULE_LICENSE("GPL v2");