drivers/reset/reset-simple.c

   1 /*
   2  * Simple Reset Controller Driver
   3  *
   4  * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
   5  *
   6  * Based on Allwinner SoCs Reset Controller driver
   7  *
   8  * Copyright 2013 Maxime Ripard
   9  *
  10  * Maxime Ripard <maxime.ripard@free-electrons.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  */
  17
  18 #include <linux/device.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/reset-controller.h>
  25 #include <linux/spinlock.h>
  26
  27 #include "reset-simple.h"
  28
  29 static inline struct reset_simple_data *
  30 to_reset_simple_data(struct reset_controller_dev *rcdev)
  31 {
  32         return container_of(rcdev, struct reset_simple_data, rcdev);
  33 }
  34
  35 static int reset_simple_update(struct reset_controller_dev *rcdev,
  36                                unsigned long id, bool assert)
  37 {
  38         struct reset_simple_data *data = to_reset_simple_data(rcdev);
  39         int reg_width = sizeof(u32);
  40         int bank = id / (reg_width * BITS_PER_BYTE);
  41         int offset = id % (reg_width * BITS_PER_BYTE);
  42         unsigned long flags;
  43         u32 reg;
  44
  45         spin_lock_irqsave(&data->lock, flags);
  46
  47         reg = readl(data->membase + (bank * reg_width));
  48         if (assert ^ data->active_low)
  49                 reg |= BIT(offset);
  50         else
  51                 reg &= ~BIT(offset);
  52         writel(reg, data->membase + (bank * reg_width));
  53
  54         spin_unlock_irqrestore(&data->lock, flags);
  55
  56         return 0;
  57 }
  58
  59 static int reset_simple_assert(struct reset_controller_dev *rcdev,
  60                                unsigned long id)
  61 {
  62         return reset_simple_update(rcdev, id, true);
  63 }
  64
  65 static int reset_simple_deassert(struct reset_controller_dev *rcdev,
  66                                  unsigned long id)
  67 {
  68         return reset_simple_update(rcdev, id, false);
  69 }
  70
  71 static int reset_simple_status(struct reset_controller_dev *rcdev,
  72                                unsigned long id)
  73 {
  74         struct reset_simple_data *data = to_reset_simple_data(rcdev);
  75         int reg_width = sizeof(u32);
  76         int bank = id / (reg_width * BITS_PER_BYTE);
  77         int offset = id % (reg_width * BITS_PER_BYTE);
  78         u32 reg;
  79
  80         reg = readl(data->membase + (bank * reg_width));
  81
  82         return !(reg & BIT(offset)) ^ !data->status_active_low;
  83 }
  84
  85 const struct reset_control_ops reset_simple_ops = {
  86         .assert         = reset_simple_assert,
  87         .deassert       = reset_simple_deassert,
  88         .status         = reset_simple_status,
  89 };
  90 EXPORT_SYMBOL_GPL(reset_simple_ops);
  91
  92 /**
  93  * struct reset_simple_devdata - simple reset controller properties
  94  * @reg_offset: offset between base address and first reset register.
  95  * @nr_resets: number of resets. If not set, default to resource size in bits.
  96  * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
  97  *              are set to assert the reset.
  98  * @status_active_low: if true, bits read back as cleared while the reset is
  99  *                     asserted. Otherwise, bits read back as set while the
 100  *                     reset is asserted.
 101  */
 102 struct reset_simple_devdata {
 103         u32 reg_offset;
 104         u32 nr_resets;
 105         bool active_low;
 106         bool status_active_low;
 107 };
 108
 109 #define SOCFPGA_NR_BANKS        8
 110
 111 static const struct reset_simple_devdata reset_simple_socfpga = {
 112         .reg_offset = 0x10,
 113         .nr_resets = SOCFPGA_NR_BANKS * 32,
 114         .status_active_low = true,
 115 };
 116
 117 static const struct reset_simple_devdata reset_simple_active_low = {
 118         .active_low = true,
 119         .status_active_low = true,
 120 };
 121
 122 static const struct of_device_id reset_simple_dt_ids[] = {
 123         { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
 124         { .compatible = "st,stm32-rcc", },
 125         { .compatible = "allwinner,sun6i-a31-clock-reset",
 126                 .data = &reset_simple_active_low },
 127         { .compatible = "zte,zx296718-reset",
 128                 .data = &reset_simple_active_low },
 129         { .compatible = "aspeed,ast2400-lpc-reset" },
 130         { .compatible = "aspeed,ast2500-lpc-reset" },
 131         { /* sentinel */ },
 132 };
 133
 134 static int reset_simple_probe(struct platform_device *pdev)
 135 {
 136         struct device *dev = &pdev->dev;
 137         const struct reset_simple_devdata *devdata;
 138         struct reset_simple_data *data;
 139         void __iomem *membase;
 140         struct resource *res;
 141         u32 reg_offset = 0;
 142
 143         devdata = of_device_get_match_data(dev);
 144
 145         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 146         if (!data)
 147                 return -ENOMEM;
 148
 149         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 150         membase = devm_ioremap_resource(dev, res);
 151         if (IS_ERR(membase))
 152                 return PTR_ERR(membase);
 153
 154         spin_lock_init(&data->lock);
 155         data->membase = membase;
 156         data->rcdev.owner = THIS_MODULE;
 157         data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
 158         data->rcdev.ops = &reset_simple_ops;
 159         data->rcdev.of_node = dev->of_node;
 160
 161         if (devdata) {
 162                 reg_offset = devdata->reg_offset;
 163                 if (devdata->nr_resets)
 164                         data->rcdev.nr_resets = devdata->nr_resets;
 165                 data->active_low = devdata->active_low;
 166                 data->status_active_low = devdata->status_active_low;
 167         }
 168
 169         if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
 170             of_property_read_u32(dev->of_node, "altr,modrst-offset",
 171                                  &reg_offset)) {
 172                 dev_warn(dev,
 173                          "missing altr,modrst-offset property, assuming 0x%x!\n",
 174                          reg_offset);
 175         }
 176
 177         data->membase += reg_offset;
 178
 179         return devm_reset_controller_register(dev, &data->rcdev);
 180 }
 181
 182 static struct platform_driver reset_simple_driver = {
 183         .probe  = reset_simple_probe,
 184         .driver = {
 185                 .name           = "simple-reset",
 186                 .of_match_table = reset_simple_dt_ids,
 187         },
 188 };
 189 builtin_platform_driver(reset_simple_driver);