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Linux 4.19.133
[linux/fpc-iii.git] / drivers / rtc / rtc-omap.c
blob080211dd916a654abcf8bb277ae887d7309f2e5a
1 /*
2 * TI OMAP Real Time Clock interface for Linux
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
6 *
7 * Copyright (C) 2006 David Brownell (new RTC framework)
8 * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16 #include <dt-bindings/gpio/gpio.h>
17 #include <linux/bcd.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/rtc.h>
33
34 /*
35 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
36 * with century-range alarm matching, driven by the 32kHz clock.
37 *
38 * The main user-visible ways it differs from PC RTCs are by omitting
39 * "don't care" alarm fields and sub-second periodic IRQs, and having
40 * an autoadjust mechanism to calibrate to the true oscillator rate.
41 *
42 * Board-specific wiring options include using split power mode with
43 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
44 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
45 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
46 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
47 */
48
49 /* RTC registers */
50 #define OMAP_RTC_SECONDS_REG 0x00
51 #define OMAP_RTC_MINUTES_REG 0x04
52 #define OMAP_RTC_HOURS_REG 0x08
53 #define OMAP_RTC_DAYS_REG 0x0C
54 #define OMAP_RTC_MONTHS_REG 0x10
55 #define OMAP_RTC_YEARS_REG 0x14
56 #define OMAP_RTC_WEEKS_REG 0x18
57
58 #define OMAP_RTC_ALARM_SECONDS_REG 0x20
59 #define OMAP_RTC_ALARM_MINUTES_REG 0x24
60 #define OMAP_RTC_ALARM_HOURS_REG 0x28
61 #define OMAP_RTC_ALARM_DAYS_REG 0x2c
62 #define OMAP_RTC_ALARM_MONTHS_REG 0x30
63 #define OMAP_RTC_ALARM_YEARS_REG 0x34
64
65 #define OMAP_RTC_CTRL_REG 0x40
66 #define OMAP_RTC_STATUS_REG 0x44
67 #define OMAP_RTC_INTERRUPTS_REG 0x48
68
69 #define OMAP_RTC_COMP_LSB_REG 0x4c
70 #define OMAP_RTC_COMP_MSB_REG 0x50
71 #define OMAP_RTC_OSC_REG 0x54
72
73 #define OMAP_RTC_SCRATCH0_REG 0x60
74 #define OMAP_RTC_SCRATCH1_REG 0x64
75 #define OMAP_RTC_SCRATCH2_REG 0x68
76
77 #define OMAP_RTC_KICK0_REG 0x6c
78 #define OMAP_RTC_KICK1_REG 0x70
79
80 #define OMAP_RTC_IRQWAKEEN 0x7c
81
82 #define OMAP_RTC_ALARM2_SECONDS_REG 0x80
83 #define OMAP_RTC_ALARM2_MINUTES_REG 0x84
84 #define OMAP_RTC_ALARM2_HOURS_REG 0x88
85 #define OMAP_RTC_ALARM2_DAYS_REG 0x8c
86 #define OMAP_RTC_ALARM2_MONTHS_REG 0x90
87 #define OMAP_RTC_ALARM2_YEARS_REG 0x94
88
89 #define OMAP_RTC_PMIC_REG 0x98
90
91 /* OMAP_RTC_CTRL_REG bit fields: */
92 #define OMAP_RTC_CTRL_SPLIT BIT(7)
93 #define OMAP_RTC_CTRL_DISABLE BIT(6)
94 #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
95 #define OMAP_RTC_CTRL_TEST BIT(4)
96 #define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
97 #define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
98 #define OMAP_RTC_CTRL_ROUND_30S BIT(1)
99 #define OMAP_RTC_CTRL_STOP BIT(0)
100
101 /* OMAP_RTC_STATUS_REG bit fields: */
102 #define OMAP_RTC_STATUS_POWER_UP BIT(7)
103 #define OMAP_RTC_STATUS_ALARM2 BIT(7)
104 #define OMAP_RTC_STATUS_ALARM BIT(6)
105 #define OMAP_RTC_STATUS_1D_EVENT BIT(5)
106 #define OMAP_RTC_STATUS_1H_EVENT BIT(4)
107 #define OMAP_RTC_STATUS_1M_EVENT BIT(3)
108 #define OMAP_RTC_STATUS_1S_EVENT BIT(2)
109 #define OMAP_RTC_STATUS_RUN BIT(1)
110 #define OMAP_RTC_STATUS_BUSY BIT(0)
111
112 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
113 #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
114 #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
115 #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
116
117 /* OMAP_RTC_OSC_REG bit fields: */
118 #define OMAP_RTC_OSC_32KCLK_EN BIT(6)
119 #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
120 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
121
122 /* OMAP_RTC_IRQWAKEEN bit fields: */
123 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
124
125 /* OMAP_RTC_PMIC bit fields: */
126 #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
127 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
128 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
129
130 /* OMAP_RTC_KICKER values */
131 #define KICK0_VALUE 0x83e70b13
132 #define KICK1_VALUE 0x95a4f1e0
133
134 struct omap_rtc;
135
136 struct omap_rtc_device_type {
137 bool has_32kclk_en;
138 bool has_irqwakeen;
139 bool has_pmic_mode;
140 bool has_power_up_reset;
141 void (*lock)(struct omap_rtc *rtc);
142 void (*unlock)(struct omap_rtc *rtc);
143 };
144
145 struct omap_rtc {
146 struct rtc_device *rtc;
147 void __iomem *base;
148 struct clk *clk;
149 int irq_alarm;
150 int irq_timer;
151 u8 interrupts_reg;
152 bool is_pmic_controller;
153 bool has_ext_clk;
154 bool is_suspending;
155 const struct omap_rtc_device_type *type;
156 struct pinctrl_dev *pctldev;
157 };
158
159 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
160 {
161 return readb(rtc->base + reg);
162 }
163
164 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
165 {
166 return readl(rtc->base + reg);
167 }
168
169 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
170 {
171 writeb(val, rtc->base + reg);
172 }
173
174 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
175 {
176 writel(val, rtc->base + reg);
177 }
178
179 static void am3352_rtc_unlock(struct omap_rtc *rtc)
180 {
181 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
182 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
183 }
184
185 static void am3352_rtc_lock(struct omap_rtc *rtc)
186 {
187 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
188 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
189 }
190
191 static void default_rtc_unlock(struct omap_rtc *rtc)
192 {
193 }
194
195 static void default_rtc_lock(struct omap_rtc *rtc)
196 {
197 }
198
199 /*
200 * We rely on the rtc framework to handle locking (rtc->ops_lock),
201 * so the only other requirement is that register accesses which
202 * require BUSY to be clear are made with IRQs locally disabled
203 */
204 static void rtc_wait_not_busy(struct omap_rtc *rtc)
205 {
206 int count;
207 u8 status;
208
209 /* BUSY may stay active for 1/32768 second (~30 usec) */
210 for (count = 0; count < 50; count++) {
211 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
212 if (!(status & OMAP_RTC_STATUS_BUSY))
213 break;
214 udelay(1);
215 }
216 /* now we have ~15 usec to read/write various registers */
217 }
218
219 static irqreturn_t rtc_irq(int irq, void *dev_id)
220 {
221 struct omap_rtc *rtc = dev_id;
222 unsigned long events = 0;
223 u8 irq_data;
224
225 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
226
227 /* alarm irq? */
228 if (irq_data & OMAP_RTC_STATUS_ALARM) {
229 rtc->type->unlock(rtc);
230 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
231 rtc->type->lock(rtc);
232 events |= RTC_IRQF | RTC_AF;
233 }
234
235 /* 1/sec periodic/update irq? */
236 if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
237 events |= RTC_IRQF | RTC_UF;
238
239 rtc_update_irq(rtc->rtc, 1, events);
240
241 return IRQ_HANDLED;
242 }
243
244 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
245 {
246 struct omap_rtc *rtc = dev_get_drvdata(dev);
247 u8 reg, irqwake_reg = 0;
248
249 local_irq_disable();
250 rtc_wait_not_busy(rtc);
251 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
252 if (rtc->type->has_irqwakeen)
253 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
254
255 if (enabled) {
256 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
257 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
258 } else {
259 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
260 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
261 }
262 rtc_wait_not_busy(rtc);
263 rtc->type->unlock(rtc);
264 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
265 if (rtc->type->has_irqwakeen)
266 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
267 rtc->type->lock(rtc);
268 local_irq_enable();
269
270 return 0;
271 }
272
273 /* this hardware doesn't support "don't care" alarm fields */
274 static int tm2bcd(struct rtc_time *tm)
275 {
276 tm->tm_sec = bin2bcd(tm->tm_sec);
277 tm->tm_min = bin2bcd(tm->tm_min);
278 tm->tm_hour = bin2bcd(tm->tm_hour);
279 tm->tm_mday = bin2bcd(tm->tm_mday);
280
281 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
282
283 /* epoch == 1900 */
284 if (tm->tm_year < 100 || tm->tm_year > 199)
285 return -EINVAL;
286 tm->tm_year = bin2bcd(tm->tm_year - 100);
287
288 return 0;
289 }
290
291 static void bcd2tm(struct rtc_time *tm)
292 {
293 tm->tm_sec = bcd2bin(tm->tm_sec);
294 tm->tm_min = bcd2bin(tm->tm_min);
295 tm->tm_hour = bcd2bin(tm->tm_hour);
296 tm->tm_mday = bcd2bin(tm->tm_mday);
297 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
298 /* epoch == 1900 */
299 tm->tm_year = bcd2bin(tm->tm_year) + 100;
300 }
301
302 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
303 {
304 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
305 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
306 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
307 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
308 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
309 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
310 }
311
312 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
313 {
314 struct omap_rtc *rtc = dev_get_drvdata(dev);
315
316 /* we don't report wday/yday/isdst ... */
317 local_irq_disable();
318 rtc_wait_not_busy(rtc);
319 omap_rtc_read_time_raw(rtc, tm);
320 local_irq_enable();
321
322 bcd2tm(tm);
323
324 return 0;
325 }
326
327 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
328 {
329 struct omap_rtc *rtc = dev_get_drvdata(dev);
330
331 if (tm2bcd(tm) < 0)
332 return -EINVAL;
333
334 local_irq_disable();
335 rtc_wait_not_busy(rtc);
336
337 rtc->type->unlock(rtc);
338 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
339 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
340 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
341 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
342 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
343 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
344 rtc->type->lock(rtc);
345
346 local_irq_enable();
347
348 return 0;
349 }
350
351 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
352 {
353 struct omap_rtc *rtc = dev_get_drvdata(dev);
354 u8 interrupts;
355
356 local_irq_disable();
357 rtc_wait_not_busy(rtc);
358
359 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
360 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
361 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
362 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
363 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
364 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
365
366 local_irq_enable();
367
368 bcd2tm(&alm->time);
369
370 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
371 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
372
373 return 0;
374 }
375
376 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
377 {
378 struct omap_rtc *rtc = dev_get_drvdata(dev);
379 u8 reg, irqwake_reg = 0;
380
381 if (tm2bcd(&alm->time) < 0)
382 return -EINVAL;
383
384 local_irq_disable();
385 rtc_wait_not_busy(rtc);
386
387 rtc->type->unlock(rtc);
388 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
389 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
390 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
391 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
392 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
393 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
394
395 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
396 if (rtc->type->has_irqwakeen)
397 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
398
399 if (alm->enabled) {
400 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
401 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
402 } else {
403 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
404 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
405 }
406 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
407 if (rtc->type->has_irqwakeen)
408 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
409 rtc->type->lock(rtc);
410
411 local_irq_enable();
412
413 return 0;
414 }
415
416 static struct omap_rtc *omap_rtc_power_off_rtc;
417
418 /*
419 * omap_rtc_poweroff: RTC-controlled power off
420 *
421 * The RTC can be used to control an external PMIC via the pmic_power_en pin,
422 * which can be configured to transition to OFF on ALARM2 events.
423 *
424 * Notes:
425 * The two-second alarm offset is the shortest offset possible as the alarm
426 * registers must be set before the next timer update and the offset
427 * calculation is too heavy for everything to be done within a single access
428 * period (~15 us).
429 *
430 * Called with local interrupts disabled.
431 */
432 static void omap_rtc_power_off(void)
433 {
434 struct omap_rtc *rtc = omap_rtc_power_off_rtc;
435 struct rtc_time tm;
436 unsigned long now;
437 u32 val;
438
439 rtc->type->unlock(rtc);
440 /* enable pmic_power_en control */
441 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
442 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
443
444 /* set alarm two seconds from now */
445 omap_rtc_read_time_raw(rtc, &tm);
446 bcd2tm(&tm);
447 rtc_tm_to_time(&tm, &now);
448 rtc_time_to_tm(now + 2, &tm);
449
450 if (tm2bcd(&tm) < 0) {
451 dev_err(&rtc->rtc->dev, "power off failed\n");
452 rtc->type->lock(rtc);
453 return;
454 }
455
456 rtc_wait_not_busy(rtc);
457
458 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
459 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
460 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
461 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
462 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
463 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
464
465 /*
466 * enable ALARM2 interrupt
467 *
468 * NOTE: this fails on AM3352 if rtc_write (writeb) is used
469 */
470 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
471 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
472 val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
473 rtc->type->lock(rtc);
474
475 /*
476 * Wait for alarm to trigger (within two seconds) and external PMIC to
477 * power off the system. Add a 500 ms margin for external latencies
478 * (e.g. debounce circuits).
479 */
480 mdelay(2500);
481 }
482
483 static const struct rtc_class_ops omap_rtc_ops = {
484 .read_time = omap_rtc_read_time,
485 .set_time = omap_rtc_set_time,
486 .read_alarm = omap_rtc_read_alarm,
487 .set_alarm = omap_rtc_set_alarm,
488 .alarm_irq_enable = omap_rtc_alarm_irq_enable,
489 };
490
491 static const struct omap_rtc_device_type omap_rtc_default_type = {
492 .has_power_up_reset = true,
493 .lock = default_rtc_lock,
494 .unlock = default_rtc_unlock,
495 };
496
497 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
498 .has_32kclk_en = true,
499 .has_irqwakeen = true,
500 .has_pmic_mode = true,
501 .lock = am3352_rtc_lock,
502 .unlock = am3352_rtc_unlock,
503 };
504
505 static const struct omap_rtc_device_type omap_rtc_da830_type = {
506 .lock = am3352_rtc_lock,
507 .unlock = am3352_rtc_unlock,
508 };
509
510 static const struct platform_device_id omap_rtc_id_table[] = {
511 {
512 .name = "omap_rtc",
513 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
514 }, {
515 .name = "am3352-rtc",
516 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
517 }, {
518 .name = "da830-rtc",
519 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
520 }, {
521 /* sentinel */
522 }
523 };
524 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
525
526 static const struct of_device_id omap_rtc_of_match[] = {
527 {
528 .compatible = "ti,am3352-rtc",
529 .data = &omap_rtc_am3352_type,
530 }, {
531 .compatible = "ti,da830-rtc",
532 .data = &omap_rtc_da830_type,
533 }, {
534 /* sentinel */
535 }
536 };
537 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
538
539 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
540 PINCTRL_PIN(0, "ext_wakeup0"),
541 PINCTRL_PIN(1, "ext_wakeup1"),
542 PINCTRL_PIN(2, "ext_wakeup2"),
543 PINCTRL_PIN(3, "ext_wakeup3"),
544 };
545
546 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
547 {
548 return 0;
549 }
550
551 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
552 unsigned int group)
553 {
554 return NULL;
555 }
556
557 static const struct pinctrl_ops rtc_pinctrl_ops = {
558 .get_groups_count = rtc_pinctrl_get_groups_count,
559 .get_group_name = rtc_pinctrl_get_group_name,
560 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
561 .dt_free_map = pinconf_generic_dt_free_map,
562 };
563
564 #define PIN_CONFIG_ACTIVE_HIGH (PIN_CONFIG_END + 1)
565
566 static const struct pinconf_generic_params rtc_params[] = {
567 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
568 };
569
570 #ifdef CONFIG_DEBUG_FS
571 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
572 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
573 };
574 #endif
575
576 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
577 unsigned int pin, unsigned long *config)
578 {
579 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
580 unsigned int param = pinconf_to_config_param(*config);
581 u32 val;
582 u16 arg = 0;
583
584 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
585
586 switch (param) {
587 case PIN_CONFIG_INPUT_ENABLE:
588 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
589 return -EINVAL;
590 break;
591 case PIN_CONFIG_ACTIVE_HIGH:
592 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
593 return -EINVAL;
594 break;
595 default:
596 return -ENOTSUPP;
597 };
598
599 *config = pinconf_to_config_packed(param, arg);
600
601 return 0;
602 }
603
604 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
605 unsigned int pin, unsigned long *configs,
606 unsigned int num_configs)
607 {
608 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
609 u32 val;
610 unsigned int param;
611 u32 param_val;
612 int i;
613
614 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
615
616 /* active low by default */
617 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
618
619 for (i = 0; i < num_configs; i++) {
620 param = pinconf_to_config_param(configs[i]);
621 param_val = pinconf_to_config_argument(configs[i]);
622
623 switch (param) {
624 case PIN_CONFIG_INPUT_ENABLE:
625 if (param_val)
626 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
627 else
628 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
629 break;
630 case PIN_CONFIG_ACTIVE_HIGH:
631 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
632 break;
633 default:
634 dev_err(&rtc->rtc->dev, "Property %u not supported\n",
635 param);
636 return -ENOTSUPP;
637 }
638 }
639
640 rtc->type->unlock(rtc);
641 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
642 rtc->type->lock(rtc);
643
644 return 0;
645 }
646
647 static const struct pinconf_ops rtc_pinconf_ops = {
648 .is_generic = true,
649 .pin_config_get = rtc_pinconf_get,
650 .pin_config_set = rtc_pinconf_set,
651 };
652
653 static struct pinctrl_desc rtc_pinctrl_desc = {
654 .pins = rtc_pins_desc,
655 .npins = ARRAY_SIZE(rtc_pins_desc),
656 .pctlops = &rtc_pinctrl_ops,
657 .confops = &rtc_pinconf_ops,
658 .custom_params = rtc_params,
659 .num_custom_params = ARRAY_SIZE(rtc_params),
660 #ifdef CONFIG_DEBUG_FS
661 .custom_conf_items = rtc_conf_items,
662 #endif
663 .owner = THIS_MODULE,
664 };
665
666 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
667 size_t bytes)
668 {
669 struct omap_rtc *rtc = priv;
670 u32 *val = _val;
671 int i;
672
673 for (i = 0; i < bytes / 4; i++)
674 val[i] = rtc_readl(rtc,
675 OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
676
677 return 0;
678 }
679
680 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
681 size_t bytes)
682 {
683 struct omap_rtc *rtc = priv;
684 u32 *val = _val;
685 int i;
686
687 rtc->type->unlock(rtc);
688 for (i = 0; i < bytes / 4; i++)
689 rtc_writel(rtc,
690 OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
691 rtc->type->lock(rtc);
692
693 return 0;
694 }
695
696 static struct nvmem_config omap_rtc_nvmem_config = {
697 .name = "omap_rtc_scratch",
698 .word_size = 4,
699 .stride = 4,
700 .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
701 .reg_read = omap_rtc_scratch_read,
702 .reg_write = omap_rtc_scratch_write,
703 };
704
705 static int omap_rtc_probe(struct platform_device *pdev)
706 {
707 struct omap_rtc *rtc;
708 struct resource *res;
709 u8 reg, mask, new_ctrl;
710 const struct platform_device_id *id_entry;
711 const struct of_device_id *of_id;
712 int ret;
713
714 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
715 if (!rtc)
716 return -ENOMEM;
717
718 of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
719 if (of_id) {
720 rtc->type = of_id->data;
721 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
722 of_property_read_bool(pdev->dev.of_node,
723 "system-power-controller");
724 } else {
725 id_entry = platform_get_device_id(pdev);
726 rtc->type = (void *)id_entry->driver_data;
727 }
728
729 rtc->irq_timer = platform_get_irq(pdev, 0);
730 if (rtc->irq_timer <= 0)
731 return -ENOENT;
732
733 rtc->irq_alarm = platform_get_irq(pdev, 1);
734 if (rtc->irq_alarm <= 0)
735 return -ENOENT;
736
737 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
738 if (!IS_ERR(rtc->clk))
739 rtc->has_ext_clk = true;
740 else
741 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
742
743 if (!IS_ERR(rtc->clk))
744 clk_prepare_enable(rtc->clk);
745
746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
747 rtc->base = devm_ioremap_resource(&pdev->dev, res);
748 if (IS_ERR(rtc->base)) {
749 clk_disable_unprepare(rtc->clk);
750 return PTR_ERR(rtc->base);
751 }
752
753 platform_set_drvdata(pdev, rtc);
754
755 /* Enable the clock/module so that we can access the registers */
756 pm_runtime_enable(&pdev->dev);
757 pm_runtime_get_sync(&pdev->dev);
758
759 rtc->type->unlock(rtc);
760
761 /*
762 * disable interrupts
763 *
764 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
765 */
766 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
767
768 /* enable RTC functional clock */
769 if (rtc->type->has_32kclk_en) {
770 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
771 rtc_writel(rtc, OMAP_RTC_OSC_REG,
772 reg | OMAP_RTC_OSC_32KCLK_EN);
773 }
774
775 /* clear old status */
776 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
777
778 mask = OMAP_RTC_STATUS_ALARM;
779
780 if (rtc->type->has_pmic_mode)
781 mask |= OMAP_RTC_STATUS_ALARM2;
782
783 if (rtc->type->has_power_up_reset) {
784 mask |= OMAP_RTC_STATUS_POWER_UP;
785 if (reg & OMAP_RTC_STATUS_POWER_UP)
786 dev_info(&pdev->dev, "RTC power up reset detected\n");
787 }
788
789 if (reg & mask)
790 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
791
792 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
793 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
794 if (reg & OMAP_RTC_CTRL_STOP)
795 dev_info(&pdev->dev, "already running\n");
796
797 /* force to 24 hour mode */
798 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
799 new_ctrl |= OMAP_RTC_CTRL_STOP;
800
801 /*
802 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
803 *
804 * - Device wake-up capability setting should come through chip
805 * init logic. OMAP1 boards should initialize the "wakeup capable"
806 * flag in the platform device if the board is wired right for
807 * being woken up by RTC alarm. For OMAP-L138, this capability
808 * is built into the SoC by the "Deep Sleep" capability.
809 *
810 * - Boards wired so RTC_ON_nOFF is used as the reset signal,
811 * rather than nPWRON_RESET, should forcibly enable split
812 * power mode. (Some chip errata report that RTC_CTRL_SPLIT
813 * is write-only, and always reads as zero...)
814 */
815
816 if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
817 dev_info(&pdev->dev, "split power mode\n");
818
819 if (reg != new_ctrl)
820 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
821
822 /*
823 * If we have the external clock then switch to it so we can keep
824 * ticking across suspend.
825 */
826 if (rtc->has_ext_clk) {
827 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
828 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
829 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
830 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
831 }
832
833 rtc->type->lock(rtc);
834
835 device_init_wakeup(&pdev->dev, true);
836
837 rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
838 if (IS_ERR(rtc->rtc)) {
839 ret = PTR_ERR(rtc->rtc);
840 goto err;
841 }
842
843 rtc->rtc->ops = &omap_rtc_ops;
844 omap_rtc_nvmem_config.priv = rtc;
845
846 /* handle periodic and alarm irqs */
847 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
848 dev_name(&rtc->rtc->dev), rtc);
849 if (ret)
850 goto err;
851
852 if (rtc->irq_timer != rtc->irq_alarm) {
853 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
854 dev_name(&rtc->rtc->dev), rtc);
855 if (ret)
856 goto err;
857 }
858
859 /* Support ext_wakeup pinconf */
860 rtc_pinctrl_desc.name = dev_name(&pdev->dev);
861
862 rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
863 if (IS_ERR(rtc->pctldev)) {
864 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
865 ret = PTR_ERR(rtc->pctldev);
866 goto err;
867 }
868
869 ret = rtc_register_device(rtc->rtc);
870 if (ret)
871 goto err_deregister_pinctrl;
872
873 rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
874
875 if (rtc->is_pmic_controller) {
876 if (!pm_power_off) {
877 omap_rtc_power_off_rtc = rtc;
878 pm_power_off = omap_rtc_power_off;
879 }
880 }
881
882 return 0;
883
884 err_deregister_pinctrl:
885 pinctrl_unregister(rtc->pctldev);
886 err:
887 clk_disable_unprepare(rtc->clk);
888 device_init_wakeup(&pdev->dev, false);
889 rtc->type->lock(rtc);
890 pm_runtime_put_sync(&pdev->dev);
891 pm_runtime_disable(&pdev->dev);
892
893 return ret;
894 }
895
896 static int omap_rtc_remove(struct platform_device *pdev)
897 {
898 struct omap_rtc *rtc = platform_get_drvdata(pdev);
899 u8 reg;
900
901 if (pm_power_off == omap_rtc_power_off &&
902 omap_rtc_power_off_rtc == rtc) {
903 pm_power_off = NULL;
904 omap_rtc_power_off_rtc = NULL;
905 }
906
907 device_init_wakeup(&pdev->dev, 0);
908
909 if (!IS_ERR(rtc->clk))
910 clk_disable_unprepare(rtc->clk);
911
912 rtc->type->unlock(rtc);
913 /* leave rtc running, but disable irqs */
914 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
915
916 if (rtc->has_ext_clk) {
917 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
918 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
919 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
920 }
921
922 rtc->type->lock(rtc);
923
924 /* Disable the clock/module */
925 pm_runtime_put_sync(&pdev->dev);
926 pm_runtime_disable(&pdev->dev);
927
928 /* Remove ext_wakeup pinconf */
929 pinctrl_unregister(rtc->pctldev);
930
931 return 0;
932 }
933
934 static int __maybe_unused omap_rtc_suspend(struct device *dev)
935 {
936 struct omap_rtc *rtc = dev_get_drvdata(dev);
937
938 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
939
940 rtc->type->unlock(rtc);
941 /*
942 * FIXME: the RTC alarm is not currently acting as a wakeup event
943 * source on some platforms, and in fact this enable() call is just
944 * saving a flag that's never used...
945 */
946 if (device_may_wakeup(dev))
947 enable_irq_wake(rtc->irq_alarm);
948 else
949 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
950 rtc->type->lock(rtc);
951
952 rtc->is_suspending = true;
953
954 return 0;
955 }
956
957 static int __maybe_unused omap_rtc_resume(struct device *dev)
958 {
959 struct omap_rtc *rtc = dev_get_drvdata(dev);
960
961 rtc->type->unlock(rtc);
962 if (device_may_wakeup(dev))
963 disable_irq_wake(rtc->irq_alarm);
964 else
965 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
966 rtc->type->lock(rtc);
967
968 rtc->is_suspending = false;
969
970 return 0;
971 }
972
973 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
974 {
975 struct omap_rtc *rtc = dev_get_drvdata(dev);
976
977 if (rtc->is_suspending && !rtc->has_ext_clk)
978 return -EBUSY;
979
980 return 0;
981 }
982
983 static const struct dev_pm_ops omap_rtc_pm_ops = {
984 SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
985 SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
986 };
987
988 static void omap_rtc_shutdown(struct platform_device *pdev)
989 {
990 struct omap_rtc *rtc = platform_get_drvdata(pdev);
991 u8 mask;
992
993 /*
994 * Keep the ALARM interrupt enabled to allow the system to power up on
995 * alarm events.
996 */
997 rtc->type->unlock(rtc);
998 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
999 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1000 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1001 rtc->type->lock(rtc);
1002 }
1003
1004 static struct platform_driver omap_rtc_driver = {
1005 .probe = omap_rtc_probe,
1006 .remove = omap_rtc_remove,
1007 .shutdown = omap_rtc_shutdown,
1008 .driver = {
1009 .name = "omap_rtc",
1010 .pm = &omap_rtc_pm_ops,
1011 .of_match_table = omap_rtc_of_match,
1012 },
1013 .id_table = omap_rtc_id_table,
1014 };
1015
1016 module_platform_driver(omap_rtc_driver);
1017
1018 MODULE_ALIAS("platform:omap_rtc");
1019 MODULE_AUTHOR("George G. Davis (and others)");
1020 MODULE_LICENSE("GPL");
Linux with added FPC-III support