drivers/rtc/rtc-snvs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
   4
   5 #include <linux/init.h>
   6 #include <linux/io.h>
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/rtc.h>
  13 #include <linux/clk.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/regmap.h>
  16
  17 #define SNVS_LPREGISTER_OFFSET  0x34
  18
  19 /* These register offsets are relative to LP (Low Power) range */
  20 #define SNVS_LPCR               0x04
  21 #define SNVS_LPSR               0x18
  22 #define SNVS_LPSRTCMR           0x1c
  23 #define SNVS_LPSRTCLR           0x20
  24 #define SNVS_LPTAR              0x24
  25 #define SNVS_LPPGDR             0x30
  26
  27 #define SNVS_LPCR_SRTC_ENV      (1 << 0)
  28 #define SNVS_LPCR_LPTA_EN       (1 << 1)
  29 #define SNVS_LPCR_LPWUI_EN      (1 << 3)
  30 #define SNVS_LPSR_LPTA          (1 << 0)
  31
  32 #define SNVS_LPPGDR_INIT        0x41736166
  33 #define CNTR_TO_SECS_SH         15
  34
  35 struct snvs_rtc_data {
  36         struct rtc_device *rtc;
  37         struct regmap *regmap;
  38         int offset;
  39         int irq;
  40         struct clk *clk;
  41 };
  42
  43 /* Read 64 bit timer register, which could be in inconsistent state */
  44 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
  45 {
  46         u32 msb, lsb;
  47
  48         regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
  49         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
  50         return (u64)msb << 32 | lsb;
  51 }
  52
  53 /* Read the secure real time counter, taking care to deal with the cases of the
  54  * counter updating while being read.
  55  */
  56 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
  57 {
  58         u64 read1, read2;
  59         unsigned int timeout = 100;
  60
  61         /* As expected, the registers might update between the read of the LSB
  62          * reg and the MSB reg.  It's also possible that one register might be
  63          * in partially modified state as well.
  64          */
  65         read1 = rtc_read_lpsrt(data);
  66         do {
  67                 read2 = read1;
  68                 read1 = rtc_read_lpsrt(data);
  69         } while (read1 != read2 && --timeout);
  70         if (!timeout)
  71                 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
  72
  73         /* Convert 47-bit counter to 32-bit raw second count */
  74         return (u32) (read1 >> CNTR_TO_SECS_SH);
  75 }
  76
  77 /* Just read the lsb from the counter, dealing with inconsistent state */
  78 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
  79 {
  80         u32 count1, count2;
  81         unsigned int timeout = 100;
  82
  83         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
  84         do {
  85                 count2 = count1;
  86                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
  87         } while (count1 != count2 && --timeout);
  88         if (!timeout) {
  89                 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
  90                 return -ETIMEDOUT;
  91         }
  92
  93         *lsb = count1;
  94         return 0;
  95 }
  96
  97 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
  98 {
  99         u32 count1, count2;
 100         u32 elapsed;
 101         unsigned int timeout = 1000;
 102         int ret;
 103
 104         ret = rtc_read_lp_counter_lsb(data, &count1);
 105         if (ret)
 106                 return ret;
 107
 108         /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
 109         do {
 110                 ret = rtc_read_lp_counter_lsb(data, &count2);
 111                 if (ret)
 112                         return ret;
 113                 elapsed = count2 - count1; /* wrap around _is_ handled! */
 114         } while (elapsed < 3 && --timeout);
 115         if (!timeout) {
 116                 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
 117                 return -ETIMEDOUT;
 118         }
 119         return 0;
 120 }
 121
 122 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 123 {
 124         int timeout = 1000;
 125         u32 lpcr;
 126
 127         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
 128                            enable ? SNVS_LPCR_SRTC_ENV : 0);
 129
 130         while (--timeout) {
 131                 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
 132
 133                 if (enable) {
 134                         if (lpcr & SNVS_LPCR_SRTC_ENV)
 135                                 break;
 136                 } else {
 137                         if (!(lpcr & SNVS_LPCR_SRTC_ENV))
 138                                 break;
 139                 }
 140         }
 141
 142         if (!timeout)
 143                 return -ETIMEDOUT;
 144
 145         return 0;
 146 }
 147
 148 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
 149 {
 150         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 151         unsigned long time = rtc_read_lp_counter(data);
 152
 153         rtc_time_to_tm(time, tm);
 154
 155         return 0;
 156 }
 157
 158 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
 159 {
 160         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 161         unsigned long time;
 162         int ret;
 163
 164         rtc_tm_to_time(tm, &time);
 165
 166         /* Disable RTC first */
 167         ret = snvs_rtc_enable(data, false);
 168         if (ret)
 169                 return ret;
 170
 171         /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
 172         regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
 173         regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
 174
 175         /* Enable RTC again */
 176         ret = snvs_rtc_enable(data, true);
 177
 178         return ret;
 179 }
 180
 181 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 182 {
 183         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 184         u32 lptar, lpsr;
 185
 186         regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
 187         rtc_time_to_tm(lptar, &alrm->time);
 188
 189         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 190         alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
 191
 192         return 0;
 193 }
 194
 195 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 196 {
 197         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 198
 199         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
 200                            (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
 201                            enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
 202
 203         return rtc_write_sync_lp(data);
 204 }
 205
 206 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 207 {
 208         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 209         struct rtc_time *alrm_tm = &alrm->time;
 210         unsigned long time;
 211         int ret;
 212
 213         rtc_tm_to_time(alrm_tm, &time);
 214
 215         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
 216         ret = rtc_write_sync_lp(data);
 217         if (ret)
 218                 return ret;
 219         regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
 220
 221         /* Clear alarm interrupt status bit */
 222         regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
 223
 224         return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
 225 }
 226
 227 static const struct rtc_class_ops snvs_rtc_ops = {
 228         .read_time = snvs_rtc_read_time,
 229         .set_time = snvs_rtc_set_time,
 230         .read_alarm = snvs_rtc_read_alarm,
 231         .set_alarm = snvs_rtc_set_alarm,
 232         .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
 233 };
 234
 235 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
 236 {
 237         struct device *dev = dev_id;
 238         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 239         u32 lpsr;
 240         u32 events = 0;
 241
 242         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 243
 244         if (lpsr & SNVS_LPSR_LPTA) {
 245                 events |= (RTC_AF | RTC_IRQF);
 246
 247                 /* RTC alarm should be one-shot */
 248                 snvs_rtc_alarm_irq_enable(dev, 0);
 249
 250                 rtc_update_irq(data->rtc, 1, events);
 251         }
 252
 253         /* clear interrupt status */
 254         regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
 255
 256         return events ? IRQ_HANDLED : IRQ_NONE;
 257 }
 258
 259 static const struct regmap_config snvs_rtc_config = {
 260         .reg_bits = 32,
 261         .val_bits = 32,
 262         .reg_stride = 4,
 263 };
 264
 265 static int snvs_rtc_probe(struct platform_device *pdev)
 266 {
 267         struct snvs_rtc_data *data;
 268         struct resource *res;
 269         int ret;
 270         void __iomem *mmio;
 271
 272         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 273         if (!data)
 274                 return -ENOMEM;
 275
 276         data->rtc = devm_rtc_allocate_device(&pdev->dev);
 277         if (IS_ERR(data->rtc))
 278                 return PTR_ERR(data->rtc);
 279
 280         data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
 281
 282         if (IS_ERR(data->regmap)) {
 283                 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
 284                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 285
 286                 mmio = devm_ioremap_resource(&pdev->dev, res);
 287                 if (IS_ERR(mmio))
 288                         return PTR_ERR(mmio);
 289
 290                 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
 291         } else {
 292                 data->offset = SNVS_LPREGISTER_OFFSET;
 293                 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
 294         }
 295
 296         if (IS_ERR(data->regmap)) {
 297                 dev_err(&pdev->dev, "Can't find snvs syscon\n");
 298                 return -ENODEV;
 299         }
 300
 301         data->irq = platform_get_irq(pdev, 0);
 302         if (data->irq < 0)
 303                 return data->irq;
 304
 305         data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
 306         if (IS_ERR(data->clk)) {
 307                 data->clk = NULL;
 308         } else {
 309                 ret = clk_prepare_enable(data->clk);
 310                 if (ret) {
 311                         dev_err(&pdev->dev,
 312                                 "Could not prepare or enable the snvs clock\n");
 313                         return ret;
 314                 }
 315         }
 316
 317         platform_set_drvdata(pdev, data);
 318
 319         /* Initialize glitch detect */
 320         regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
 321
 322         /* Clear interrupt status */
 323         regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
 324
 325         /* Enable RTC */
 326         ret = snvs_rtc_enable(data, true);
 327         if (ret) {
 328                 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
 329                 goto error_rtc_device_register;
 330         }
 331
 332         device_init_wakeup(&pdev->dev, true);
 333
 334         ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
 335                                IRQF_SHARED, "rtc alarm", &pdev->dev);
 336         if (ret) {
 337                 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
 338                         data->irq, ret);
 339                 goto error_rtc_device_register;
 340         }
 341
 342         data->rtc->ops = &snvs_rtc_ops;
 343         ret = rtc_register_device(data->rtc);
 344         if (ret) {
 345                 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
 346                 goto error_rtc_device_register;
 347         }
 348
 349         return 0;
 350
 351 error_rtc_device_register:
 352         if (data->clk)
 353                 clk_disable_unprepare(data->clk);
 354
 355         return ret;
 356 }
 357
 358 #ifdef CONFIG_PM_SLEEP
 359 static int snvs_rtc_suspend(struct device *dev)
 360 {
 361         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 362
 363         if (device_may_wakeup(dev))
 364                 return enable_irq_wake(data->irq);
 365
 366         return 0;
 367 }
 368
 369 static int snvs_rtc_suspend_noirq(struct device *dev)
 370 {
 371         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 372
 373         if (data->clk)
 374                 clk_disable_unprepare(data->clk);
 375
 376         return 0;
 377 }
 378
 379 static int snvs_rtc_resume(struct device *dev)
 380 {
 381         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 382
 383         if (device_may_wakeup(dev))
 384                 return disable_irq_wake(data->irq);
 385
 386         return 0;
 387 }
 388
 389 static int snvs_rtc_resume_noirq(struct device *dev)
 390 {
 391         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 392
 393         if (data->clk)
 394                 return clk_prepare_enable(data->clk);
 395
 396         return 0;
 397 }
 398
 399 static const struct dev_pm_ops snvs_rtc_pm_ops = {
 400         .suspend = snvs_rtc_suspend,
 401         .suspend_noirq = snvs_rtc_suspend_noirq,
 402         .resume = snvs_rtc_resume,
 403         .resume_noirq = snvs_rtc_resume_noirq,
 404 };
 405
 406 #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
 407
 408 #else
 409
 410 #define SNVS_RTC_PM_OPS NULL
 411
 412 #endif
 413
 414 static const struct of_device_id snvs_dt_ids[] = {
 415         { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
 416         { /* sentinel */ }
 417 };
 418 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
 419
 420 static struct platform_driver snvs_rtc_driver = {
 421         .driver = {
 422                 .name   = "snvs_rtc",
 423                 .pm     = SNVS_RTC_PM_OPS,
 424                 .of_match_table = snvs_dt_ids,
 425         },
 426         .probe          = snvs_rtc_probe,
 427 };
 428 module_platform_driver(snvs_rtc_driver);
 429
 430 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 431 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
 432 MODULE_LICENSE("GPL");