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Linux 4.19.133
[linux/fpc-iii.git] / drivers / scsi / megaraid / megaraid_sas.h
blob67d356d84717631eb7f1c85726a6eff334e2da7f
1 /*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
25 *
26 * Send feedback to: megaraidlinux.pdl@avagotech.com
27 *
28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
30 */
31
32 #ifndef LSI_MEGARAID_SAS_H
33 #define LSI_MEGARAID_SAS_H
34
35 /*
36 * MegaRAID SAS Driver meta data
37 */
38 #define MEGASAS_VERSION "07.706.03.00-rc1"
39 #define MEGASAS_RELDATE "May 21, 2018"
40
41 /*
42 * Device IDs
43 */
44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 #define PCI_DEVICE_ID_LSI_FURY 0x005f
55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
60 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
61 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
62 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
63 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
64 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
65
66 /*
67 * Intel HBA SSDIDs
68 */
69 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
70 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
71 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
72 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
73 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
74 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
75 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
76
77 /*
78 * Intruder HBA SSDIDs
79 */
80 #define MEGARAID_INTRUDER_SSDID1 0x9371
81 #define MEGARAID_INTRUDER_SSDID2 0x9390
82 #define MEGARAID_INTRUDER_SSDID3 0x9370
83
84 /*
85 * Intel HBA branding
86 */
87 #define MEGARAID_INTEL_RS3DC080_BRANDING \
88 "Intel(R) RAID Controller RS3DC080"
89 #define MEGARAID_INTEL_RS3DC040_BRANDING \
90 "Intel(R) RAID Controller RS3DC040"
91 #define MEGARAID_INTEL_RS3SC008_BRANDING \
92 "Intel(R) RAID Controller RS3SC008"
93 #define MEGARAID_INTEL_RS3MC044_BRANDING \
94 "Intel(R) RAID Controller RS3MC044"
95 #define MEGARAID_INTEL_RS3WC080_BRANDING \
96 "Intel(R) RAID Controller RS3WC080"
97 #define MEGARAID_INTEL_RS3WC040_BRANDING \
98 "Intel(R) RAID Controller RS3WC040"
99 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
100 "Intel(R) Integrated RAID Module RMS3BC160"
101
102 /*
103 * =====================================
104 * MegaRAID SAS MFI firmware definitions
105 * =====================================
106 */
107
108 /*
109 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
110 * protocol between the software and firmware. Commands are issued using
111 * "message frames"
112 */
113
114 /*
115 * FW posts its state in upper 4 bits of outbound_msg_0 register
116 */
117 #define MFI_STATE_MASK 0xF0000000
118 #define MFI_STATE_UNDEFINED 0x00000000
119 #define MFI_STATE_BB_INIT 0x10000000
120 #define MFI_STATE_FW_INIT 0x40000000
121 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
122 #define MFI_STATE_FW_INIT_2 0x70000000
123 #define MFI_STATE_DEVICE_SCAN 0x80000000
124 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
125 #define MFI_STATE_FLUSH_CACHE 0xA0000000
126 #define MFI_STATE_READY 0xB0000000
127 #define MFI_STATE_OPERATIONAL 0xC0000000
128 #define MFI_STATE_FAULT 0xF0000000
129 #define MFI_STATE_FORCE_OCR 0x00000080
130 #define MFI_STATE_DMADONE 0x00000008
131 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
132 #define MFI_RESET_REQUIRED 0x00000001
133 #define MFI_RESET_ADAPTER 0x00000002
134 #define MEGAMFI_FRAME_SIZE 64
135
136 /*
137 * During FW init, clear pending cmds & reset state using inbound_msg_0
138 *
139 * ABORT : Abort all pending cmds
140 * READY : Move from OPERATIONAL to READY state; discard queue info
141 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
142 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
143 * HOTPLUG : Resume from Hotplug
144 * MFI_STOP_ADP : Send signal to FW to stop processing
145 */
146 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
147 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
148 #define DIAG_WRITE_ENABLE (0x00000080)
149 #define DIAG_RESET_ADAPTER (0x00000004)
150
151 #define MFI_ADP_RESET 0x00000040
152 #define MFI_INIT_ABORT 0x00000001
153 #define MFI_INIT_READY 0x00000002
154 #define MFI_INIT_MFIMODE 0x00000004
155 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
156 #define MFI_INIT_HOTPLUG 0x00000010
157 #define MFI_STOP_ADP 0x00000020
158 #define MFI_RESET_FLAGS MFI_INIT_READY| \
159 MFI_INIT_MFIMODE| \
160 MFI_INIT_ABORT
161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
162
163 /*
164 * MFI frame flags
165 */
166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
168 #define MFI_FRAME_SGL32 0x0000
169 #define MFI_FRAME_SGL64 0x0002
170 #define MFI_FRAME_SENSE32 0x0000
171 #define MFI_FRAME_SENSE64 0x0004
172 #define MFI_FRAME_DIR_NONE 0x0000
173 #define MFI_FRAME_DIR_WRITE 0x0008
174 #define MFI_FRAME_DIR_READ 0x0010
175 #define MFI_FRAME_DIR_BOTH 0x0018
176 #define MFI_FRAME_IEEE 0x0020
177
178 /* Driver internal */
179 #define DRV_DCMD_POLLED_MODE 0x1
180 #define DRV_DCMD_SKIP_REFIRE 0x2
181
182 /*
183 * Definition for cmd_status
184 */
185 #define MFI_CMD_STATUS_POLL_MODE 0xFF
186
187 /*
188 * MFI command opcodes
189 */
190 enum MFI_CMD_OP {
191 MFI_CMD_INIT = 0x0,
192 MFI_CMD_LD_READ = 0x1,
193 MFI_CMD_LD_WRITE = 0x2,
194 MFI_CMD_LD_SCSI_IO = 0x3,
195 MFI_CMD_PD_SCSI_IO = 0x4,
196 MFI_CMD_DCMD = 0x5,
197 MFI_CMD_ABORT = 0x6,
198 MFI_CMD_SMP = 0x7,
199 MFI_CMD_STP = 0x8,
200 MFI_CMD_NVME = 0x9,
201 MFI_CMD_OP_COUNT,
202 MFI_CMD_INVALID = 0xff
203 };
204
205 #define MR_DCMD_CTRL_GET_INFO 0x01010000
206 #define MR_DCMD_LD_GET_LIST 0x03010000
207 #define MR_DCMD_LD_LIST_QUERY 0x03010100
208
209 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
210 #define MR_FLUSH_CTRL_CACHE 0x01
211 #define MR_FLUSH_DISK_CACHE 0x02
212
213 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
214 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
215 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
216
217 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
218 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
219 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
220 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
221
222 #define MR_DCMD_CLUSTER 0x08000000
223 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
224 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
225 #define MR_DCMD_PD_LIST_QUERY 0x02010100
226
227 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
228 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
229 #define MR_DCMD_PD_GET_INFO 0x02020000
230
231 /*
232 * Global functions
233 */
234 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
235
236
237 /*
238 * MFI command completion codes
239 */
240 enum MFI_STAT {
241 MFI_STAT_OK = 0x00,
242 MFI_STAT_INVALID_CMD = 0x01,
243 MFI_STAT_INVALID_DCMD = 0x02,
244 MFI_STAT_INVALID_PARAMETER = 0x03,
245 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
246 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
247 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
248 MFI_STAT_APP_IN_USE = 0x07,
249 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
250 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
251 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
252 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
253 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
254 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
255 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
256 MFI_STAT_FLASH_BUSY = 0x0f,
257 MFI_STAT_FLASH_ERROR = 0x10,
258 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
259 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
260 MFI_STAT_FLASH_NOT_OPEN = 0x13,
261 MFI_STAT_FLASH_NOT_STARTED = 0x14,
262 MFI_STAT_FLUSH_FAILED = 0x15,
263 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
264 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
265 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
266 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
267 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
268 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
269 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
270 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
271 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
272 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
273 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
274 MFI_STAT_MFC_HW_ERROR = 0x21,
275 MFI_STAT_NO_HW_PRESENT = 0x22,
276 MFI_STAT_NOT_FOUND = 0x23,
277 MFI_STAT_NOT_IN_ENCL = 0x24,
278 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
279 MFI_STAT_PD_TYPE_WRONG = 0x26,
280 MFI_STAT_PR_DISABLED = 0x27,
281 MFI_STAT_ROW_INDEX_INVALID = 0x28,
282 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
283 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
284 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
285 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
286 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
287 MFI_STAT_SCSI_IO_FAILED = 0x2e,
288 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
289 MFI_STAT_SHUTDOWN_FAILED = 0x30,
290 MFI_STAT_TIME_NOT_SET = 0x31,
291 MFI_STAT_WRONG_STATE = 0x32,
292 MFI_STAT_LD_OFFLINE = 0x33,
293 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
294 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
295 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
296 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
297 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
298 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
299
300 MFI_STAT_INVALID_STATUS = 0xFF
301 };
302
303 enum mfi_evt_class {
304 MFI_EVT_CLASS_DEBUG = -2,
305 MFI_EVT_CLASS_PROGRESS = -1,
306 MFI_EVT_CLASS_INFO = 0,
307 MFI_EVT_CLASS_WARNING = 1,
308 MFI_EVT_CLASS_CRITICAL = 2,
309 MFI_EVT_CLASS_FATAL = 3,
310 MFI_EVT_CLASS_DEAD = 4
311 };
312
313 /*
314 * Crash dump related defines
315 */
316 #define MAX_CRASH_DUMP_SIZE 512
317 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
318
319 enum MR_FW_CRASH_DUMP_STATE {
320 UNAVAILABLE = 0,
321 AVAILABLE = 1,
322 COPYING = 2,
323 COPIED = 3,
324 COPY_ERROR = 4,
325 };
326
327 enum _MR_CRASH_BUF_STATUS {
328 MR_CRASH_BUF_TURN_OFF = 0,
329 MR_CRASH_BUF_TURN_ON = 1,
330 };
331
332 /*
333 * Number of mailbox bytes in DCMD message frame
334 */
335 #define MFI_MBOX_SIZE 12
336
337 enum MR_EVT_CLASS {
338
339 MR_EVT_CLASS_DEBUG = -2,
340 MR_EVT_CLASS_PROGRESS = -1,
341 MR_EVT_CLASS_INFO = 0,
342 MR_EVT_CLASS_WARNING = 1,
343 MR_EVT_CLASS_CRITICAL = 2,
344 MR_EVT_CLASS_FATAL = 3,
345 MR_EVT_CLASS_DEAD = 4,
346
347 };
348
349 enum MR_EVT_LOCALE {
350
351 MR_EVT_LOCALE_LD = 0x0001,
352 MR_EVT_LOCALE_PD = 0x0002,
353 MR_EVT_LOCALE_ENCL = 0x0004,
354 MR_EVT_LOCALE_BBU = 0x0008,
355 MR_EVT_LOCALE_SAS = 0x0010,
356 MR_EVT_LOCALE_CTRL = 0x0020,
357 MR_EVT_LOCALE_CONFIG = 0x0040,
358 MR_EVT_LOCALE_CLUSTER = 0x0080,
359 MR_EVT_LOCALE_ALL = 0xffff,
360
361 };
362
363 enum MR_EVT_ARGS {
364
365 MR_EVT_ARGS_NONE,
366 MR_EVT_ARGS_CDB_SENSE,
367 MR_EVT_ARGS_LD,
368 MR_EVT_ARGS_LD_COUNT,
369 MR_EVT_ARGS_LD_LBA,
370 MR_EVT_ARGS_LD_OWNER,
371 MR_EVT_ARGS_LD_LBA_PD_LBA,
372 MR_EVT_ARGS_LD_PROG,
373 MR_EVT_ARGS_LD_STATE,
374 MR_EVT_ARGS_LD_STRIP,
375 MR_EVT_ARGS_PD,
376 MR_EVT_ARGS_PD_ERR,
377 MR_EVT_ARGS_PD_LBA,
378 MR_EVT_ARGS_PD_LBA_LD,
379 MR_EVT_ARGS_PD_PROG,
380 MR_EVT_ARGS_PD_STATE,
381 MR_EVT_ARGS_PCI,
382 MR_EVT_ARGS_RATE,
383 MR_EVT_ARGS_STR,
384 MR_EVT_ARGS_TIME,
385 MR_EVT_ARGS_ECC,
386 MR_EVT_ARGS_LD_PROP,
387 MR_EVT_ARGS_PD_SPARE,
388 MR_EVT_ARGS_PD_INDEX,
389 MR_EVT_ARGS_DIAG_PASS,
390 MR_EVT_ARGS_DIAG_FAIL,
391 MR_EVT_ARGS_PD_LBA_LBA,
392 MR_EVT_ARGS_PORT_PHY,
393 MR_EVT_ARGS_PD_MISSING,
394 MR_EVT_ARGS_PD_ADDRESS,
395 MR_EVT_ARGS_BITMAP,
396 MR_EVT_ARGS_CONNECTOR,
397 MR_EVT_ARGS_PD_PD,
398 MR_EVT_ARGS_PD_FRU,
399 MR_EVT_ARGS_PD_PATHINFO,
400 MR_EVT_ARGS_PD_POWER_STATE,
401 MR_EVT_ARGS_GENERIC,
402 };
403
404
405 #define SGE_BUFFER_SIZE 4096
406 #define MEGASAS_CLUSTER_ID_SIZE 16
407 /*
408 * define constants for device list query options
409 */
410 enum MR_PD_QUERY_TYPE {
411 MR_PD_QUERY_TYPE_ALL = 0,
412 MR_PD_QUERY_TYPE_STATE = 1,
413 MR_PD_QUERY_TYPE_POWER_STATE = 2,
414 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
415 MR_PD_QUERY_TYPE_SPEED = 4,
416 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
417 };
418
419 enum MR_LD_QUERY_TYPE {
420 MR_LD_QUERY_TYPE_ALL = 0,
421 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
422 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
423 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
424 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
425 };
426
427
428 #define MR_EVT_CFG_CLEARED 0x0004
429 #define MR_EVT_LD_STATE_CHANGE 0x0051
430 #define MR_EVT_PD_INSERTED 0x005b
431 #define MR_EVT_PD_REMOVED 0x0070
432 #define MR_EVT_LD_CREATED 0x008a
433 #define MR_EVT_LD_DELETED 0x008b
434 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
435 #define MR_EVT_LD_OFFLINE 0x00fc
436 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
437 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
438
439 enum MR_PD_STATE {
440 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
441 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
442 MR_PD_STATE_HOT_SPARE = 0x02,
443 MR_PD_STATE_OFFLINE = 0x10,
444 MR_PD_STATE_FAILED = 0x11,
445 MR_PD_STATE_REBUILD = 0x14,
446 MR_PD_STATE_ONLINE = 0x18,
447 MR_PD_STATE_COPYBACK = 0x20,
448 MR_PD_STATE_SYSTEM = 0x40,
449 };
450
451 union MR_PD_REF {
452 struct {
453 u16 deviceId;
454 u16 seqNum;
455 } mrPdRef;
456 u32 ref;
457 };
458
459 /*
460 * define the DDF Type bit structure
461 */
462 union MR_PD_DDF_TYPE {
463 struct {
464 union {
465 struct {
466 #ifndef __BIG_ENDIAN_BITFIELD
467 u16 forcedPDGUID:1;
468 u16 inVD:1;
469 u16 isGlobalSpare:1;
470 u16 isSpare:1;
471 u16 isForeign:1;
472 u16 reserved:7;
473 u16 intf:4;
474 #else
475 u16 intf:4;
476 u16 reserved:7;
477 u16 isForeign:1;
478 u16 isSpare:1;
479 u16 isGlobalSpare:1;
480 u16 inVD:1;
481 u16 forcedPDGUID:1;
482 #endif
483 } pdType;
484 u16 type;
485 };
486 u16 reserved;
487 } ddf;
488 struct {
489 u32 reserved;
490 } nonDisk;
491 u32 type;
492 } __packed;
493
494 /*
495 * defines the progress structure
496 */
497 union MR_PROGRESS {
498 struct {
499 u16 progress;
500 union {
501 u16 elapsedSecs;
502 u16 elapsedSecsForLastPercent;
503 };
504 } mrProgress;
505 u32 w;
506 } __packed;
507
508 /*
509 * defines the physical drive progress structure
510 */
511 struct MR_PD_PROGRESS {
512 struct {
513 #ifndef MFI_BIG_ENDIAN
514 u32 rbld:1;
515 u32 patrol:1;
516 u32 clear:1;
517 u32 copyBack:1;
518 u32 erase:1;
519 u32 locate:1;
520 u32 reserved:26;
521 #else
522 u32 reserved:26;
523 u32 locate:1;
524 u32 erase:1;
525 u32 copyBack:1;
526 u32 clear:1;
527 u32 patrol:1;
528 u32 rbld:1;
529 #endif
530 } active;
531 union MR_PROGRESS rbld;
532 union MR_PROGRESS patrol;
533 union {
534 union MR_PROGRESS clear;
535 union MR_PROGRESS erase;
536 };
537
538 struct {
539 #ifndef MFI_BIG_ENDIAN
540 u32 rbld:1;
541 u32 patrol:1;
542 u32 clear:1;
543 u32 copyBack:1;
544 u32 erase:1;
545 u32 reserved:27;
546 #else
547 u32 reserved:27;
548 u32 erase:1;
549 u32 copyBack:1;
550 u32 clear:1;
551 u32 patrol:1;
552 u32 rbld:1;
553 #endif
554 } pause;
555
556 union MR_PROGRESS reserved[3];
557 } __packed;
558
559 struct MR_PD_INFO {
560 union MR_PD_REF ref;
561 u8 inquiryData[96];
562 u8 vpdPage83[64];
563 u8 notSupported;
564 u8 scsiDevType;
565
566 union {
567 u8 connectedPortBitmap;
568 u8 connectedPortNumbers;
569 };
570
571 u8 deviceSpeed;
572 u32 mediaErrCount;
573 u32 otherErrCount;
574 u32 predFailCount;
575 u32 lastPredFailEventSeqNum;
576
577 u16 fwState;
578 u8 disabledForRemoval;
579 u8 linkSpeed;
580 union MR_PD_DDF_TYPE state;
581
582 struct {
583 u8 count;
584 #ifndef __BIG_ENDIAN_BITFIELD
585 u8 isPathBroken:4;
586 u8 reserved3:3;
587 u8 widePortCapable:1;
588 #else
589 u8 widePortCapable:1;
590 u8 reserved3:3;
591 u8 isPathBroken:4;
592 #endif
593
594 u8 connectorIndex[2];
595 u8 reserved[4];
596 u64 sasAddr[2];
597 u8 reserved2[16];
598 } pathInfo;
599
600 u64 rawSize;
601 u64 nonCoercedSize;
602 u64 coercedSize;
603 u16 enclDeviceId;
604 u8 enclIndex;
605
606 union {
607 u8 slotNumber;
608 u8 enclConnectorIndex;
609 };
610
611 struct MR_PD_PROGRESS progInfo;
612 u8 badBlockTableFull;
613 u8 unusableInCurrentConfig;
614 u8 vpdPage83Ext[64];
615 u8 powerState;
616 u8 enclPosition;
617 u32 allowedOps;
618 u16 copyBackPartnerId;
619 u16 enclPartnerDeviceId;
620 struct {
621 #ifndef __BIG_ENDIAN_BITFIELD
622 u16 fdeCapable:1;
623 u16 fdeEnabled:1;
624 u16 secured:1;
625 u16 locked:1;
626 u16 foreign:1;
627 u16 needsEKM:1;
628 u16 reserved:10;
629 #else
630 u16 reserved:10;
631 u16 needsEKM:1;
632 u16 foreign:1;
633 u16 locked:1;
634 u16 secured:1;
635 u16 fdeEnabled:1;
636 u16 fdeCapable:1;
637 #endif
638 } security;
639 u8 mediaType;
640 u8 notCertified;
641 u8 bridgeVendor[8];
642 u8 bridgeProductIdentification[16];
643 u8 bridgeProductRevisionLevel[4];
644 u8 satBridgeExists;
645
646 u8 interfaceType;
647 u8 temperature;
648 u8 emulatedBlockSize;
649 u16 userDataBlockSize;
650 u16 reserved2;
651
652 struct {
653 #ifndef __BIG_ENDIAN_BITFIELD
654 u32 piType:3;
655 u32 piFormatted:1;
656 u32 piEligible:1;
657 u32 NCQ:1;
658 u32 WCE:1;
659 u32 commissionedSpare:1;
660 u32 emergencySpare:1;
661 u32 ineligibleForSSCD:1;
662 u32 ineligibleForLd:1;
663 u32 useSSEraseType:1;
664 u32 wceUnchanged:1;
665 u32 supportScsiUnmap:1;
666 u32 reserved:18;
667 #else
668 u32 reserved:18;
669 u32 supportScsiUnmap:1;
670 u32 wceUnchanged:1;
671 u32 useSSEraseType:1;
672 u32 ineligibleForLd:1;
673 u32 ineligibleForSSCD:1;
674 u32 emergencySpare:1;
675 u32 commissionedSpare:1;
676 u32 WCE:1;
677 u32 NCQ:1;
678 u32 piEligible:1;
679 u32 piFormatted:1;
680 u32 piType:3;
681 #endif
682 } properties;
683
684 u64 shieldDiagCompletionTime;
685 u8 shieldCounter;
686
687 u8 linkSpeedOther;
688 u8 reserved4[2];
689
690 struct {
691 #ifndef __BIG_ENDIAN_BITFIELD
692 u32 bbmErrCountSupported:1;
693 u32 bbmErrCount:31;
694 #else
695 u32 bbmErrCount:31;
696 u32 bbmErrCountSupported:1;
697 #endif
698 } bbmErr;
699
700 u8 reserved1[512-428];
701 } __packed;
702
703 /*
704 * Definition of structure used to expose attributes of VD or JBOD
705 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
706 * is fired by driver)
707 */
708 struct MR_TARGET_PROPERTIES {
709 u32 max_io_size_kb;
710 u32 device_qdepth;
711 u32 sector_size;
712 u8 reset_tmo;
713 u8 reserved[499];
714 } __packed;
715
716 /*
717 * defines the physical drive address structure
718 */
719 struct MR_PD_ADDRESS {
720 __le16 deviceId;
721 u16 enclDeviceId;
722
723 union {
724 struct {
725 u8 enclIndex;
726 u8 slotNumber;
727 } mrPdAddress;
728 struct {
729 u8 enclPosition;
730 u8 enclConnectorIndex;
731 } mrEnclAddress;
732 };
733 u8 scsiDevType;
734 union {
735 u8 connectedPortBitmap;
736 u8 connectedPortNumbers;
737 };
738 u64 sasAddr[2];
739 } __packed;
740
741 /*
742 * defines the physical drive list structure
743 */
744 struct MR_PD_LIST {
745 __le32 size;
746 __le32 count;
747 struct MR_PD_ADDRESS addr[1];
748 } __packed;
749
750 struct megasas_pd_list {
751 u16 tid;
752 u8 driveType;
753 u8 driveState;
754 } __packed;
755
756 /*
757 * defines the logical drive reference structure
758 */
759 union MR_LD_REF {
760 struct {
761 u8 targetId;
762 u8 reserved;
763 __le16 seqNum;
764 };
765 __le32 ref;
766 } __packed;
767
768 /*
769 * defines the logical drive list structure
770 */
771 struct MR_LD_LIST {
772 __le32 ldCount;
773 __le32 reserved;
774 struct {
775 union MR_LD_REF ref;
776 u8 state;
777 u8 reserved[3];
778 __le64 size;
779 } ldList[MAX_LOGICAL_DRIVES_EXT];
780 } __packed;
781
782 struct MR_LD_TARGETID_LIST {
783 __le32 size;
784 __le32 count;
785 u8 pad[3];
786 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
787 };
788
789
790 /*
791 * SAS controller properties
792 */
793 struct megasas_ctrl_prop {
794
795 u16 seq_num;
796 u16 pred_fail_poll_interval;
797 u16 intr_throttle_count;
798 u16 intr_throttle_timeouts;
799 u8 rebuild_rate;
800 u8 patrol_read_rate;
801 u8 bgi_rate;
802 u8 cc_rate;
803 u8 recon_rate;
804 u8 cache_flush_interval;
805 u8 spinup_drv_count;
806 u8 spinup_delay;
807 u8 cluster_enable;
808 u8 coercion_mode;
809 u8 alarm_enable;
810 u8 disable_auto_rebuild;
811 u8 disable_battery_warn;
812 u8 ecc_bucket_size;
813 u16 ecc_bucket_leak_rate;
814 u8 restore_hotspare_on_insertion;
815 u8 expose_encl_devices;
816 u8 maintainPdFailHistory;
817 u8 disallowHostRequestReordering;
818 u8 abortCCOnError;
819 u8 loadBalanceMode;
820 u8 disableAutoDetectBackplane;
821
822 u8 snapVDSpace;
823
824 /*
825 * Add properties that can be controlled by
826 * a bit in the following structure.
827 */
828 struct {
829 #if defined(__BIG_ENDIAN_BITFIELD)
830 u32 reserved:18;
831 u32 enableJBOD:1;
832 u32 disableSpinDownHS:1;
833 u32 allowBootWithPinnedCache:1;
834 u32 disableOnlineCtrlReset:1;
835 u32 enableSecretKeyControl:1;
836 u32 autoEnhancedImport:1;
837 u32 enableSpinDownUnconfigured:1;
838 u32 SSDPatrolReadEnabled:1;
839 u32 SSDSMARTerEnabled:1;
840 u32 disableNCQ:1;
841 u32 useFdeOnly:1;
842 u32 prCorrectUnconfiguredAreas:1;
843 u32 SMARTerEnabled:1;
844 u32 copyBackDisabled:1;
845 #else
846 u32 copyBackDisabled:1;
847 u32 SMARTerEnabled:1;
848 u32 prCorrectUnconfiguredAreas:1;
849 u32 useFdeOnly:1;
850 u32 disableNCQ:1;
851 u32 SSDSMARTerEnabled:1;
852 u32 SSDPatrolReadEnabled:1;
853 u32 enableSpinDownUnconfigured:1;
854 u32 autoEnhancedImport:1;
855 u32 enableSecretKeyControl:1;
856 u32 disableOnlineCtrlReset:1;
857 u32 allowBootWithPinnedCache:1;
858 u32 disableSpinDownHS:1;
859 u32 enableJBOD:1;
860 u32 reserved:18;
861 #endif
862 } OnOffProperties;
863 u8 autoSnapVDSpace;
864 u8 viewSpace;
865 __le16 spinDownTime;
866 u8 reserved[24];
867 } __packed;
868
869 /*
870 * SAS controller information
871 */
872 struct megasas_ctrl_info {
873
874 /*
875 * PCI device information
876 */
877 struct {
878
879 __le16 vendor_id;
880 __le16 device_id;
881 __le16 sub_vendor_id;
882 __le16 sub_device_id;
883 u8 reserved[24];
884
885 } __attribute__ ((packed)) pci;
886
887 /*
888 * Host interface information
889 */
890 struct {
891
892 u8 PCIX:1;
893 u8 PCIE:1;
894 u8 iSCSI:1;
895 u8 SAS_3G:1;
896 u8 SRIOV:1;
897 u8 reserved_0:3;
898 u8 reserved_1[6];
899 u8 port_count;
900 u64 port_addr[8];
901
902 } __attribute__ ((packed)) host_interface;
903
904 /*
905 * Device (backend) interface information
906 */
907 struct {
908
909 u8 SPI:1;
910 u8 SAS_3G:1;
911 u8 SATA_1_5G:1;
912 u8 SATA_3G:1;
913 u8 reserved_0:4;
914 u8 reserved_1[6];
915 u8 port_count;
916 u64 port_addr[8];
917
918 } __attribute__ ((packed)) device_interface;
919
920 /*
921 * List of components residing in flash. All str are null terminated
922 */
923 __le32 image_check_word;
924 __le32 image_component_count;
925
926 struct {
927
928 char name[8];
929 char version[32];
930 char build_date[16];
931 char built_time[16];
932
933 } __attribute__ ((packed)) image_component[8];
934
935 /*
936 * List of flash components that have been flashed on the card, but
937 * are not in use, pending reset of the adapter. This list will be
938 * empty if a flash operation has not occurred. All stings are null
939 * terminated
940 */
941 __le32 pending_image_component_count;
942
943 struct {
944
945 char name[8];
946 char version[32];
947 char build_date[16];
948 char build_time[16];
949
950 } __attribute__ ((packed)) pending_image_component[8];
951
952 u8 max_arms;
953 u8 max_spans;
954 u8 max_arrays;
955 u8 max_lds;
956
957 char product_name[80];
958 char serial_no[32];
959
960 /*
961 * Other physical/controller/operation information. Indicates the
962 * presence of the hardware
963 */
964 struct {
965
966 u32 bbu:1;
967 u32 alarm:1;
968 u32 nvram:1;
969 u32 uart:1;
970 u32 reserved:28;
971
972 } __attribute__ ((packed)) hw_present;
973
974 __le32 current_fw_time;
975
976 /*
977 * Maximum data transfer sizes
978 */
979 __le16 max_concurrent_cmds;
980 __le16 max_sge_count;
981 __le32 max_request_size;
982
983 /*
984 * Logical and physical device counts
985 */
986 __le16 ld_present_count;
987 __le16 ld_degraded_count;
988 __le16 ld_offline_count;
989
990 __le16 pd_present_count;
991 __le16 pd_disk_present_count;
992 __le16 pd_disk_pred_failure_count;
993 __le16 pd_disk_failed_count;
994
995 /*
996 * Memory size information
997 */
998 __le16 nvram_size;
999 __le16 memory_size;
1000 __le16 flash_size;
1001
1002 /*
1003 * Error counters
1004 */
1005 __le16 mem_correctable_error_count;
1006 __le16 mem_uncorrectable_error_count;
1007
1008 /*
1009 * Cluster information
1010 */
1011 u8 cluster_permitted;
1012 u8 cluster_active;
1013
1014 /*
1015 * Additional max data transfer sizes
1016 */
1017 __le16 max_strips_per_io;
1018
1019 /*
1020 * Controller capabilities structures
1021 */
1022 struct {
1023
1024 u32 raid_level_0:1;
1025 u32 raid_level_1:1;
1026 u32 raid_level_5:1;
1027 u32 raid_level_1E:1;
1028 u32 raid_level_6:1;
1029 u32 reserved:27;
1030
1031 } __attribute__ ((packed)) raid_levels;
1032
1033 struct {
1034
1035 u32 rbld_rate:1;
1036 u32 cc_rate:1;
1037 u32 bgi_rate:1;
1038 u32 recon_rate:1;
1039 u32 patrol_rate:1;
1040 u32 alarm_control:1;
1041 u32 cluster_supported:1;
1042 u32 bbu:1;
1043 u32 spanning_allowed:1;
1044 u32 dedicated_hotspares:1;
1045 u32 revertible_hotspares:1;
1046 u32 foreign_config_import:1;
1047 u32 self_diagnostic:1;
1048 u32 mixed_redundancy_arr:1;
1049 u32 global_hot_spares:1;
1050 u32 reserved:17;
1051
1052 } __attribute__ ((packed)) adapter_operations;
1053
1054 struct {
1055
1056 u32 read_policy:1;
1057 u32 write_policy:1;
1058 u32 io_policy:1;
1059 u32 access_policy:1;
1060 u32 disk_cache_policy:1;
1061 u32 reserved:27;
1062
1063 } __attribute__ ((packed)) ld_operations;
1064
1065 struct {
1066
1067 u8 min;
1068 u8 max;
1069 u8 reserved[2];
1070
1071 } __attribute__ ((packed)) stripe_sz_ops;
1072
1073 struct {
1074
1075 u32 force_online:1;
1076 u32 force_offline:1;
1077 u32 force_rebuild:1;
1078 u32 reserved:29;
1079
1080 } __attribute__ ((packed)) pd_operations;
1081
1082 struct {
1083
1084 u32 ctrl_supports_sas:1;
1085 u32 ctrl_supports_sata:1;
1086 u32 allow_mix_in_encl:1;
1087 u32 allow_mix_in_ld:1;
1088 u32 allow_sata_in_cluster:1;
1089 u32 reserved:27;
1090
1091 } __attribute__ ((packed)) pd_mix_support;
1092
1093 /*
1094 * Define ECC single-bit-error bucket information
1095 */
1096 u8 ecc_bucket_count;
1097 u8 reserved_2[11];
1098
1099 /*
1100 * Include the controller properties (changeable items)
1101 */
1102 struct megasas_ctrl_prop properties;
1103
1104 /*
1105 * Define FW pkg version (set in envt v'bles on OEM basis)
1106 */
1107 char package_version[0x60];
1108
1109
1110 /*
1111 * If adapterOperations.supportMoreThan8Phys is set,
1112 * and deviceInterface.portCount is greater than 8,
1113 * SAS Addrs for first 8 ports shall be populated in
1114 * deviceInterface.portAddr, and the rest shall be
1115 * populated in deviceInterfacePortAddr2.
1116 */
1117 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
1118 u8 reserved3[128]; /*6e0h */
1119
1120 struct { /*760h */
1121 u16 minPdRaidLevel_0:4;
1122 u16 maxPdRaidLevel_0:12;
1123
1124 u16 minPdRaidLevel_1:4;
1125 u16 maxPdRaidLevel_1:12;
1126
1127 u16 minPdRaidLevel_5:4;
1128 u16 maxPdRaidLevel_5:12;
1129
1130 u16 minPdRaidLevel_1E:4;
1131 u16 maxPdRaidLevel_1E:12;
1132
1133 u16 minPdRaidLevel_6:4;
1134 u16 maxPdRaidLevel_6:12;
1135
1136 u16 minPdRaidLevel_10:4;
1137 u16 maxPdRaidLevel_10:12;
1138
1139 u16 minPdRaidLevel_50:4;
1140 u16 maxPdRaidLevel_50:12;
1141
1142 u16 minPdRaidLevel_60:4;
1143 u16 maxPdRaidLevel_60:12;
1144
1145 u16 minPdRaidLevel_1E_RLQ0:4;
1146 u16 maxPdRaidLevel_1E_RLQ0:12;
1147
1148 u16 minPdRaidLevel_1E0_RLQ0:4;
1149 u16 maxPdRaidLevel_1E0_RLQ0:12;
1150
1151 u16 reserved[6];
1152 } pdsForRaidLevels;
1153
1154 __le16 maxPds; /*780h */
1155 __le16 maxDedHSPs; /*782h */
1156 __le16 maxGlobalHSP; /*784h */
1157 __le16 ddfSize; /*786h */
1158 u8 maxLdsPerArray; /*788h */
1159 u8 partitionsInDDF; /*789h */
1160 u8 lockKeyBinding; /*78ah */
1161 u8 maxPITsPerLd; /*78bh */
1162 u8 maxViewsPerLd; /*78ch */
1163 u8 maxTargetId; /*78dh */
1164 __le16 maxBvlVdSize; /*78eh */
1165
1166 __le16 maxConfigurableSSCSize; /*790h */
1167 __le16 currentSSCsize; /*792h */
1168
1169 char expanderFwVersion[12]; /*794h */
1170
1171 __le16 PFKTrialTimeRemaining; /*7A0h */
1172
1173 __le16 cacheMemorySize; /*7A2h */
1174
1175 struct { /*7A4h */
1176 #if defined(__BIG_ENDIAN_BITFIELD)
1177 u32 reserved:5;
1178 u32 activePassive:2;
1179 u32 supportConfigAutoBalance:1;
1180 u32 mpio:1;
1181 u32 supportDataLDonSSCArray:1;
1182 u32 supportPointInTimeProgress:1;
1183 u32 supportUnevenSpans:1;
1184 u32 dedicatedHotSparesLimited:1;
1185 u32 headlessMode:1;
1186 u32 supportEmulatedDrives:1;
1187 u32 supportResetNow:1;
1188 u32 realTimeScheduler:1;
1189 u32 supportSSDPatrolRead:1;
1190 u32 supportPerfTuning:1;
1191 u32 disableOnlinePFKChange:1;
1192 u32 supportJBOD:1;
1193 u32 supportBootTimePFKChange:1;
1194 u32 supportSetLinkSpeed:1;
1195 u32 supportEmergencySpares:1;
1196 u32 supportSuspendResumeBGops:1;
1197 u32 blockSSDWriteCacheChange:1;
1198 u32 supportShieldState:1;
1199 u32 supportLdBBMInfo:1;
1200 u32 supportLdPIType3:1;
1201 u32 supportLdPIType2:1;
1202 u32 supportLdPIType1:1;
1203 u32 supportPIcontroller:1;
1204 #else
1205 u32 supportPIcontroller:1;
1206 u32 supportLdPIType1:1;
1207 u32 supportLdPIType2:1;
1208 u32 supportLdPIType3:1;
1209 u32 supportLdBBMInfo:1;
1210 u32 supportShieldState:1;
1211 u32 blockSSDWriteCacheChange:1;
1212 u32 supportSuspendResumeBGops:1;
1213 u32 supportEmergencySpares:1;
1214 u32 supportSetLinkSpeed:1;
1215 u32 supportBootTimePFKChange:1;
1216 u32 supportJBOD:1;
1217 u32 disableOnlinePFKChange:1;
1218 u32 supportPerfTuning:1;
1219 u32 supportSSDPatrolRead:1;
1220 u32 realTimeScheduler:1;
1221
1222 u32 supportResetNow:1;
1223 u32 supportEmulatedDrives:1;
1224 u32 headlessMode:1;
1225 u32 dedicatedHotSparesLimited:1;
1226
1227
1228 u32 supportUnevenSpans:1;
1229 u32 supportPointInTimeProgress:1;
1230 u32 supportDataLDonSSCArray:1;
1231 u32 mpio:1;
1232 u32 supportConfigAutoBalance:1;
1233 u32 activePassive:2;
1234 u32 reserved:5;
1235 #endif
1236 } adapterOperations2;
1237
1238 u8 driverVersion[32]; /*7A8h */
1239 u8 maxDAPdCountSpinup60; /*7C8h */
1240 u8 temperatureROC; /*7C9h */
1241 u8 temperatureCtrl; /*7CAh */
1242 u8 reserved4; /*7CBh */
1243 __le16 maxConfigurablePds; /*7CCh */
1244
1245
1246 u8 reserved5[2]; /*0x7CDh */
1247
1248 /*
1249 * HA cluster information
1250 */
1251 struct {
1252 #if defined(__BIG_ENDIAN_BITFIELD)
1253 u32 reserved:25;
1254 u32 passive:1;
1255 u32 premiumFeatureMismatch:1;
1256 u32 ctrlPropIncompatible:1;
1257 u32 fwVersionMismatch:1;
1258 u32 hwIncompatible:1;
1259 u32 peerIsIncompatible:1;
1260 u32 peerIsPresent:1;
1261 #else
1262 u32 peerIsPresent:1;
1263 u32 peerIsIncompatible:1;
1264 u32 hwIncompatible:1;
1265 u32 fwVersionMismatch:1;
1266 u32 ctrlPropIncompatible:1;
1267 u32 premiumFeatureMismatch:1;
1268 u32 passive:1;
1269 u32 reserved:25;
1270 #endif
1271 } cluster;
1272
1273 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1274 struct {
1275 u8 maxVFsSupported; /*0x7E4*/
1276 u8 numVFsEnabled; /*0x7E5*/
1277 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1278 u8 reserved; /*0x7E7*/
1279 } iov;
1280
1281 struct {
1282 #if defined(__BIG_ENDIAN_BITFIELD)
1283 u32 reserved:7;
1284 u32 useSeqNumJbodFP:1;
1285 u32 supportExtendedSSCSize:1;
1286 u32 supportDiskCacheSettingForSysPDs:1;
1287 u32 supportCPLDUpdate:1;
1288 u32 supportTTYLogCompression:1;
1289 u32 discardCacheDuringLDDelete:1;
1290 u32 supportSecurityonJBOD:1;
1291 u32 supportCacheBypassModes:1;
1292 u32 supportDisableSESMonitoring:1;
1293 u32 supportForceFlash:1;
1294 u32 supportNVDRAM:1;
1295 u32 supportDrvActivityLEDSetting:1;
1296 u32 supportAllowedOpsforDrvRemoval:1;
1297 u32 supportHOQRebuild:1;
1298 u32 supportForceTo512e:1;
1299 u32 supportNVCacheErase:1;
1300 u32 supportDebugQueue:1;
1301 u32 supportSwZone:1;
1302 u32 supportCrashDump:1;
1303 u32 supportMaxExtLDs:1;
1304 u32 supportT10RebuildAssist:1;
1305 u32 supportDisableImmediateIO:1;
1306 u32 supportThermalPollInterval:1;
1307 u32 supportPersonalityChange:2;
1308 #else
1309 u32 supportPersonalityChange:2;
1310 u32 supportThermalPollInterval:1;
1311 u32 supportDisableImmediateIO:1;
1312 u32 supportT10RebuildAssist:1;
1313 u32 supportMaxExtLDs:1;
1314 u32 supportCrashDump:1;
1315 u32 supportSwZone:1;
1316 u32 supportDebugQueue:1;
1317 u32 supportNVCacheErase:1;
1318 u32 supportForceTo512e:1;
1319 u32 supportHOQRebuild:1;
1320 u32 supportAllowedOpsforDrvRemoval:1;
1321 u32 supportDrvActivityLEDSetting:1;
1322 u32 supportNVDRAM:1;
1323 u32 supportForceFlash:1;
1324 u32 supportDisableSESMonitoring:1;
1325 u32 supportCacheBypassModes:1;
1326 u32 supportSecurityonJBOD:1;
1327 u32 discardCacheDuringLDDelete:1;
1328 u32 supportTTYLogCompression:1;
1329 u32 supportCPLDUpdate:1;
1330 u32 supportDiskCacheSettingForSysPDs:1;
1331 u32 supportExtendedSSCSize:1;
1332 u32 useSeqNumJbodFP:1;
1333 u32 reserved:7;
1334 #endif
1335 } adapterOperations3;
1336
1337 struct {
1338 #if defined(__BIG_ENDIAN_BITFIELD)
1339 u8 reserved:7;
1340 /* Indicates whether the CPLD image is part of
1341 * the package and stored in flash
1342 */
1343 u8 cpld_in_flash:1;
1344 #else
1345 u8 cpld_in_flash:1;
1346 u8 reserved:7;
1347 #endif
1348 u8 reserved1[3];
1349 /* Null terminated string. Has the version
1350 * information if cpld_in_flash = FALSE
1351 */
1352 u8 userCodeDefinition[12];
1353 } cpld; /* Valid only if upgradableCPLD is TRUE */
1354
1355 struct {
1356 #if defined(__BIG_ENDIAN_BITFIELD)
1357 u16 reserved:2;
1358 u16 support_nvme_passthru:1;
1359 u16 support_pl_debug_info:1;
1360 u16 support_flash_comp_info:1;
1361 u16 support_host_info:1;
1362 u16 support_dual_fw_update:1;
1363 u16 support_ssc_rev3:1;
1364 u16 fw_swaps_bbu_vpd_info:1;
1365 u16 support_pd_map_target_id:1;
1366 u16 support_ses_ctrl_in_multipathcfg:1;
1367 u16 image_upload_supported:1;
1368 u16 support_encrypted_mfc:1;
1369 u16 supported_enc_algo:1;
1370 u16 support_ibutton_less:1;
1371 u16 ctrl_info_ext_supported:1;
1372 #else
1373
1374 u16 ctrl_info_ext_supported:1;
1375 u16 support_ibutton_less:1;
1376 u16 supported_enc_algo:1;
1377 u16 support_encrypted_mfc:1;
1378 u16 image_upload_supported:1;
1379 /* FW supports LUN based association and target port based */
1380 u16 support_ses_ctrl_in_multipathcfg:1;
1381 /* association for the SES device connected in multipath mode */
1382 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1383 u16 support_pd_map_target_id:1;
1384 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1385 * provide the data in little endian order
1386 */
1387 u16 fw_swaps_bbu_vpd_info:1;
1388 u16 support_ssc_rev3:1;
1389 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1390 u16 support_dual_fw_update:1;
1391 /* FW supports dual firmware update feature */
1392 u16 support_host_info:1;
1393 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1394 u16 support_flash_comp_info:1;
1395 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1396 u16 support_pl_debug_info:1;
1397 /* FW supports retrieval of PL debug information through apps */
1398 u16 support_nvme_passthru:1;
1399 /* FW supports NVMe passthru commands */
1400 u16 reserved:2;
1401 #endif
1402 } adapter_operations4;
1403 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1404
1405 u32 size;
1406 u32 pad1;
1407
1408 u8 reserved6[64];
1409
1410 u32 rsvdForAdptOp[64];
1411
1412 u8 reserved7[3];
1413
1414 u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1415 u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */
1416 u8 reserved8[3];
1417 } __packed;
1418
1419 /*
1420 * ===============================
1421 * MegaRAID SAS driver definitions
1422 * ===============================
1423 */
1424 #define MEGASAS_MAX_PD_CHANNELS 2
1425 #define MEGASAS_MAX_LD_CHANNELS 2
1426 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1427 MEGASAS_MAX_LD_CHANNELS)
1428 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1429 #define MEGASAS_DEFAULT_INIT_ID -1
1430 #define MEGASAS_MAX_LUN 8
1431 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1432 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1433 MEGASAS_MAX_DEV_PER_CHANNEL)
1434 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1435 MEGASAS_MAX_DEV_PER_CHANNEL)
1436
1437 #define MEGASAS_MAX_SECTORS (2*1024)
1438 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1439 #define MEGASAS_DBG_LVL 1
1440
1441 #define MEGASAS_FW_BUSY 1
1442
1443 /* Driver's internal Logging levels*/
1444 #define OCR_LOGS (1 << 0)
1445
1446 #define SCAN_PD_CHANNEL 0x1
1447 #define SCAN_VD_CHANNEL 0x2
1448
1449 #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1450 #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1451 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1452
1453 enum MR_SCSI_CMD_TYPE {
1454 READ_WRITE_LDIO = 0,
1455 NON_READ_WRITE_LDIO = 1,
1456 READ_WRITE_SYSPDIO = 2,
1457 NON_READ_WRITE_SYSPDIO = 3,
1458 };
1459
1460 enum DCMD_TIMEOUT_ACTION {
1461 INITIATE_OCR = 0,
1462 KILL_ADAPTER = 1,
1463 IGNORE_TIMEOUT = 2,
1464 };
1465
1466 enum FW_BOOT_CONTEXT {
1467 PROBE_CONTEXT = 0,
1468 OCR_CONTEXT = 1,
1469 };
1470
1471 /* Frame Type */
1472 #define IO_FRAME 0
1473 #define PTHRU_FRAME 1
1474
1475 /*
1476 * When SCSI mid-layer calls driver's reset routine, driver waits for
1477 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1478 * that the driver cannot _actually_ abort or reset pending commands. While
1479 * it is waiting for the commands to complete, it prints a diagnostic message
1480 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1481 */
1482 #define MEGASAS_RESET_WAIT_TIME 180
1483 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1484 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1485 #define MEGASAS_IOCTL_CMD 0
1486 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1487 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1488 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60
1489 #define MEGASAS_DEFAULT_TM_TIMEOUT 50
1490 /*
1491 * FW reports the maximum of number of commands that it can accept (maximum
1492 * commands that can be outstanding) at any time. The driver must report a
1493 * lower number to the mid layer because it can issue a few internal commands
1494 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1495 * is shown below
1496 */
1497 #define MEGASAS_INT_CMDS 32
1498 #define MEGASAS_SKINNY_INT_CMDS 5
1499 #define MEGASAS_FUSION_INTERNAL_CMDS 8
1500 #define MEGASAS_FUSION_IOCTL_CMDS 3
1501 #define MEGASAS_MFI_IOCTL_CMDS 27
1502
1503 #define MEGASAS_MAX_MSIX_QUEUES 128
1504 /*
1505 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1506 * SGLs based on the size of dma_addr_t
1507 */
1508 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1509
1510 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1511
1512 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1513 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1514 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1515
1516 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1517 #define MFI_POLL_TIMEOUT_SECS 60
1518 #define MFI_IO_TIMEOUT_SECS 180
1519 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1520 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1521 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1522 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1523 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1524 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1525 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1526 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1527
1528 #define MFI_1068_PCSR_OFFSET 0x84
1529 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1530 #define MFI_1068_FW_READY 0xDDDD0000
1531
1532 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1533 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1534 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1535 #define MR_MAX_MSIX_REG_ARRAY 16
1536 #define MR_RDPQ_MODE_OFFSET 0X00800000
1537
1538 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1539 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1540 #define MR_MIN_MAP_SIZE 0x10000
1541 /* 64k */
1542
1543 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1544
1545 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25)
1546
1547 enum MR_ADAPTER_TYPE {
1548 MFI_SERIES = 1,
1549 THUNDERBOLT_SERIES = 2,
1550 INVADER_SERIES = 3,
1551 VENTURA_SERIES = 4,
1552 };
1553
1554 /*
1555 * register set for both 1068 and 1078 controllers
1556 * structure extended for 1078 registers
1557 */
1558
1559 struct megasas_register_set {
1560 u32 doorbell; /*0000h*/
1561 u32 fusion_seq_offset; /*0004h*/
1562 u32 fusion_host_diag; /*0008h*/
1563 u32 reserved_01; /*000Ch*/
1564
1565 u32 inbound_msg_0; /*0010h*/
1566 u32 inbound_msg_1; /*0014h*/
1567 u32 outbound_msg_0; /*0018h*/
1568 u32 outbound_msg_1; /*001Ch*/
1569
1570 u32 inbound_doorbell; /*0020h*/
1571 u32 inbound_intr_status; /*0024h*/
1572 u32 inbound_intr_mask; /*0028h*/
1573
1574 u32 outbound_doorbell; /*002Ch*/
1575 u32 outbound_intr_status; /*0030h*/
1576 u32 outbound_intr_mask; /*0034h*/
1577
1578 u32 reserved_1[2]; /*0038h*/
1579
1580 u32 inbound_queue_port; /*0040h*/
1581 u32 outbound_queue_port; /*0044h*/
1582
1583 u32 reserved_2[9]; /*0048h*/
1584 u32 reply_post_host_index; /*006Ch*/
1585 u32 reserved_2_2[12]; /*0070h*/
1586
1587 u32 outbound_doorbell_clear; /*00A0h*/
1588
1589 u32 reserved_3[3]; /*00A4h*/
1590
1591 u32 outbound_scratch_pad ; /*00B0h*/
1592 u32 outbound_scratch_pad_2; /*00B4h*/
1593 u32 outbound_scratch_pad_3; /*00B8h*/
1594 u32 outbound_scratch_pad_4; /*00BCh*/
1595
1596
1597 u32 inbound_low_queue_port ; /*00C0h*/
1598
1599 u32 inbound_high_queue_port ; /*00C4h*/
1600
1601 u32 inbound_single_queue_port; /*00C8h*/
1602 u32 res_6[11]; /*CCh*/
1603 u32 host_diag;
1604 u32 seq_offset;
1605 u32 index_registers[807]; /*00CCh*/
1606 } __attribute__ ((packed));
1607
1608 struct megasas_sge32 {
1609
1610 __le32 phys_addr;
1611 __le32 length;
1612
1613 } __attribute__ ((packed));
1614
1615 struct megasas_sge64 {
1616
1617 __le64 phys_addr;
1618 __le32 length;
1619
1620 } __attribute__ ((packed));
1621
1622 struct megasas_sge_skinny {
1623 __le64 phys_addr;
1624 __le32 length;
1625 __le32 flag;
1626 } __packed;
1627
1628 union megasas_sgl {
1629
1630 struct megasas_sge32 sge32[1];
1631 struct megasas_sge64 sge64[1];
1632 struct megasas_sge_skinny sge_skinny[1];
1633
1634 } __attribute__ ((packed));
1635
1636 struct megasas_header {
1637
1638 u8 cmd; /*00h */
1639 u8 sense_len; /*01h */
1640 u8 cmd_status; /*02h */
1641 u8 scsi_status; /*03h */
1642
1643 u8 target_id; /*04h */
1644 u8 lun; /*05h */
1645 u8 cdb_len; /*06h */
1646 u8 sge_count; /*07h */
1647
1648 __le32 context; /*08h */
1649 __le32 pad_0; /*0Ch */
1650
1651 __le16 flags; /*10h */
1652 __le16 timeout; /*12h */
1653 __le32 data_xferlen; /*14h */
1654
1655 } __attribute__ ((packed));
1656
1657 union megasas_sgl_frame {
1658
1659 struct megasas_sge32 sge32[8];
1660 struct megasas_sge64 sge64[5];
1661
1662 } __attribute__ ((packed));
1663
1664 typedef union _MFI_CAPABILITIES {
1665 struct {
1666 #if defined(__BIG_ENDIAN_BITFIELD)
1667 u32 reserved:17;
1668 u32 support_nvme_passthru:1;
1669 u32 support_64bit_mode:1;
1670 u32 support_pd_map_target_id:1;
1671 u32 support_qd_throttling:1;
1672 u32 support_fp_rlbypass:1;
1673 u32 support_vfid_in_ioframe:1;
1674 u32 support_ext_io_size:1;
1675 u32 support_ext_queue_depth:1;
1676 u32 security_protocol_cmds_fw:1;
1677 u32 support_core_affinity:1;
1678 u32 support_ndrive_r1_lb:1;
1679 u32 support_max_255lds:1;
1680 u32 support_fastpath_wb:1;
1681 u32 support_additional_msix:1;
1682 u32 support_fp_remote_lun:1;
1683 #else
1684 u32 support_fp_remote_lun:1;
1685 u32 support_additional_msix:1;
1686 u32 support_fastpath_wb:1;
1687 u32 support_max_255lds:1;
1688 u32 support_ndrive_r1_lb:1;
1689 u32 support_core_affinity:1;
1690 u32 security_protocol_cmds_fw:1;
1691 u32 support_ext_queue_depth:1;
1692 u32 support_ext_io_size:1;
1693 u32 support_vfid_in_ioframe:1;
1694 u32 support_fp_rlbypass:1;
1695 u32 support_qd_throttling:1;
1696 u32 support_pd_map_target_id:1;
1697 u32 support_64bit_mode:1;
1698 u32 support_nvme_passthru:1;
1699 u32 reserved:17;
1700 #endif
1701 } mfi_capabilities;
1702 __le32 reg;
1703 } MFI_CAPABILITIES;
1704
1705 struct megasas_init_frame {
1706
1707 u8 cmd; /*00h */
1708 u8 reserved_0; /*01h */
1709 u8 cmd_status; /*02h */
1710
1711 u8 reserved_1; /*03h */
1712 MFI_CAPABILITIES driver_operations; /*04h*/
1713
1714 __le32 context; /*08h */
1715 __le32 pad_0; /*0Ch */
1716
1717 __le16 flags; /*10h */
1718 __le16 reserved_3; /*12h */
1719 __le32 data_xfer_len; /*14h */
1720
1721 __le32 queue_info_new_phys_addr_lo; /*18h */
1722 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1723 __le32 queue_info_old_phys_addr_lo; /*20h */
1724 __le32 queue_info_old_phys_addr_hi; /*24h */
1725 __le32 reserved_4[2]; /*28h */
1726 __le32 system_info_lo; /*30h */
1727 __le32 system_info_hi; /*34h */
1728 __le32 reserved_5[2]; /*38h */
1729
1730 } __attribute__ ((packed));
1731
1732 struct megasas_init_queue_info {
1733
1734 __le32 init_flags; /*00h */
1735 __le32 reply_queue_entries; /*04h */
1736
1737 __le32 reply_queue_start_phys_addr_lo; /*08h */
1738 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1739 __le32 producer_index_phys_addr_lo; /*10h */
1740 __le32 producer_index_phys_addr_hi; /*14h */
1741 __le32 consumer_index_phys_addr_lo; /*18h */
1742 __le32 consumer_index_phys_addr_hi; /*1Ch */
1743
1744 } __attribute__ ((packed));
1745
1746 struct megasas_io_frame {
1747
1748 u8 cmd; /*00h */
1749 u8 sense_len; /*01h */
1750 u8 cmd_status; /*02h */
1751 u8 scsi_status; /*03h */
1752
1753 u8 target_id; /*04h */
1754 u8 access_byte; /*05h */
1755 u8 reserved_0; /*06h */
1756 u8 sge_count; /*07h */
1757
1758 __le32 context; /*08h */
1759 __le32 pad_0; /*0Ch */
1760
1761 __le16 flags; /*10h */
1762 __le16 timeout; /*12h */
1763 __le32 lba_count; /*14h */
1764
1765 __le32 sense_buf_phys_addr_lo; /*18h */
1766 __le32 sense_buf_phys_addr_hi; /*1Ch */
1767
1768 __le32 start_lba_lo; /*20h */
1769 __le32 start_lba_hi; /*24h */
1770
1771 union megasas_sgl sgl; /*28h */
1772
1773 } __attribute__ ((packed));
1774
1775 struct megasas_pthru_frame {
1776
1777 u8 cmd; /*00h */
1778 u8 sense_len; /*01h */
1779 u8 cmd_status; /*02h */
1780 u8 scsi_status; /*03h */
1781
1782 u8 target_id; /*04h */
1783 u8 lun; /*05h */
1784 u8 cdb_len; /*06h */
1785 u8 sge_count; /*07h */
1786
1787 __le32 context; /*08h */
1788 __le32 pad_0; /*0Ch */
1789
1790 __le16 flags; /*10h */
1791 __le16 timeout; /*12h */
1792 __le32 data_xfer_len; /*14h */
1793
1794 __le32 sense_buf_phys_addr_lo; /*18h */
1795 __le32 sense_buf_phys_addr_hi; /*1Ch */
1796
1797 u8 cdb[16]; /*20h */
1798 union megasas_sgl sgl; /*30h */
1799
1800 } __attribute__ ((packed));
1801
1802 struct megasas_dcmd_frame {
1803
1804 u8 cmd; /*00h */
1805 u8 reserved_0; /*01h */
1806 u8 cmd_status; /*02h */
1807 u8 reserved_1[4]; /*03h */
1808 u8 sge_count; /*07h */
1809
1810 __le32 context; /*08h */
1811 __le32 pad_0; /*0Ch */
1812
1813 __le16 flags; /*10h */
1814 __le16 timeout; /*12h */
1815
1816 __le32 data_xfer_len; /*14h */
1817 __le32 opcode; /*18h */
1818
1819 union { /*1Ch */
1820 u8 b[12];
1821 __le16 s[6];
1822 __le32 w[3];
1823 } mbox;
1824
1825 union megasas_sgl sgl; /*28h */
1826
1827 } __attribute__ ((packed));
1828
1829 struct megasas_abort_frame {
1830
1831 u8 cmd; /*00h */
1832 u8 reserved_0; /*01h */
1833 u8 cmd_status; /*02h */
1834
1835 u8 reserved_1; /*03h */
1836 __le32 reserved_2; /*04h */
1837
1838 __le32 context; /*08h */
1839 __le32 pad_0; /*0Ch */
1840
1841 __le16 flags; /*10h */
1842 __le16 reserved_3; /*12h */
1843 __le32 reserved_4; /*14h */
1844
1845 __le32 abort_context; /*18h */
1846 __le32 pad_1; /*1Ch */
1847
1848 __le32 abort_mfi_phys_addr_lo; /*20h */
1849 __le32 abort_mfi_phys_addr_hi; /*24h */
1850
1851 __le32 reserved_5[6]; /*28h */
1852
1853 } __attribute__ ((packed));
1854
1855 struct megasas_smp_frame {
1856
1857 u8 cmd; /*00h */
1858 u8 reserved_1; /*01h */
1859 u8 cmd_status; /*02h */
1860 u8 connection_status; /*03h */
1861
1862 u8 reserved_2[3]; /*04h */
1863 u8 sge_count; /*07h */
1864
1865 __le32 context; /*08h */
1866 __le32 pad_0; /*0Ch */
1867
1868 __le16 flags; /*10h */
1869 __le16 timeout; /*12h */
1870
1871 __le32 data_xfer_len; /*14h */
1872 __le64 sas_addr; /*18h */
1873
1874 union {
1875 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1876 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1877 } sgl;
1878
1879 } __attribute__ ((packed));
1880
1881 struct megasas_stp_frame {
1882
1883 u8 cmd; /*00h */
1884 u8 reserved_1; /*01h */
1885 u8 cmd_status; /*02h */
1886 u8 reserved_2; /*03h */
1887
1888 u8 target_id; /*04h */
1889 u8 reserved_3[2]; /*05h */
1890 u8 sge_count; /*07h */
1891
1892 __le32 context; /*08h */
1893 __le32 pad_0; /*0Ch */
1894
1895 __le16 flags; /*10h */
1896 __le16 timeout; /*12h */
1897
1898 __le32 data_xfer_len; /*14h */
1899
1900 __le16 fis[10]; /*18h */
1901 __le32 stp_flags;
1902
1903 union {
1904 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1905 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1906 } sgl;
1907
1908 } __attribute__ ((packed));
1909
1910 union megasas_frame {
1911
1912 struct megasas_header hdr;
1913 struct megasas_init_frame init;
1914 struct megasas_io_frame io;
1915 struct megasas_pthru_frame pthru;
1916 struct megasas_dcmd_frame dcmd;
1917 struct megasas_abort_frame abort;
1918 struct megasas_smp_frame smp;
1919 struct megasas_stp_frame stp;
1920
1921 u8 raw_bytes[64];
1922 };
1923
1924 /**
1925 * struct MR_PRIV_DEVICE - sdev private hostdata
1926 * @is_tm_capable: firmware managed tm_capable flag
1927 * @tm_busy: TM request is in progress
1928 */
1929 struct MR_PRIV_DEVICE {
1930 bool is_tm_capable;
1931 bool tm_busy;
1932 atomic_t r1_ldio_hint;
1933 u8 interface_type;
1934 u8 task_abort_tmo;
1935 u8 target_reset_tmo;
1936 };
1937 struct megasas_cmd;
1938
1939 union megasas_evt_class_locale {
1940
1941 struct {
1942 #ifndef __BIG_ENDIAN_BITFIELD
1943 u16 locale;
1944 u8 reserved;
1945 s8 class;
1946 #else
1947 s8 class;
1948 u8 reserved;
1949 u16 locale;
1950 #endif
1951 } __attribute__ ((packed)) members;
1952
1953 u32 word;
1954
1955 } __attribute__ ((packed));
1956
1957 struct megasas_evt_log_info {
1958 __le32 newest_seq_num;
1959 __le32 oldest_seq_num;
1960 __le32 clear_seq_num;
1961 __le32 shutdown_seq_num;
1962 __le32 boot_seq_num;
1963
1964 } __attribute__ ((packed));
1965
1966 struct megasas_progress {
1967
1968 __le16 progress;
1969 __le16 elapsed_seconds;
1970
1971 } __attribute__ ((packed));
1972
1973 struct megasas_evtarg_ld {
1974
1975 u16 target_id;
1976 u8 ld_index;
1977 u8 reserved;
1978
1979 } __attribute__ ((packed));
1980
1981 struct megasas_evtarg_pd {
1982 u16 device_id;
1983 u8 encl_index;
1984 u8 slot_number;
1985
1986 } __attribute__ ((packed));
1987
1988 struct megasas_evt_detail {
1989
1990 __le32 seq_num;
1991 __le32 time_stamp;
1992 __le32 code;
1993 union megasas_evt_class_locale cl;
1994 u8 arg_type;
1995 u8 reserved1[15];
1996
1997 union {
1998 struct {
1999 struct megasas_evtarg_pd pd;
2000 u8 cdb_length;
2001 u8 sense_length;
2002 u8 reserved[2];
2003 u8 cdb[16];
2004 u8 sense[64];
2005 } __attribute__ ((packed)) cdbSense;
2006
2007 struct megasas_evtarg_ld ld;
2008
2009 struct {
2010 struct megasas_evtarg_ld ld;
2011 __le64 count;
2012 } __attribute__ ((packed)) ld_count;
2013
2014 struct {
2015 __le64 lba;
2016 struct megasas_evtarg_ld ld;
2017 } __attribute__ ((packed)) ld_lba;
2018
2019 struct {
2020 struct megasas_evtarg_ld ld;
2021 __le32 prevOwner;
2022 __le32 newOwner;
2023 } __attribute__ ((packed)) ld_owner;
2024
2025 struct {
2026 u64 ld_lba;
2027 u64 pd_lba;
2028 struct megasas_evtarg_ld ld;
2029 struct megasas_evtarg_pd pd;
2030 } __attribute__ ((packed)) ld_lba_pd_lba;
2031
2032 struct {
2033 struct megasas_evtarg_ld ld;
2034 struct megasas_progress prog;
2035 } __attribute__ ((packed)) ld_prog;
2036
2037 struct {
2038 struct megasas_evtarg_ld ld;
2039 u32 prev_state;
2040 u32 new_state;
2041 } __attribute__ ((packed)) ld_state;
2042
2043 struct {
2044 u64 strip;
2045 struct megasas_evtarg_ld ld;
2046 } __attribute__ ((packed)) ld_strip;
2047
2048 struct megasas_evtarg_pd pd;
2049
2050 struct {
2051 struct megasas_evtarg_pd pd;
2052 u32 err;
2053 } __attribute__ ((packed)) pd_err;
2054
2055 struct {
2056 u64 lba;
2057 struct megasas_evtarg_pd pd;
2058 } __attribute__ ((packed)) pd_lba;
2059
2060 struct {
2061 u64 lba;
2062 struct megasas_evtarg_pd pd;
2063 struct megasas_evtarg_ld ld;
2064 } __attribute__ ((packed)) pd_lba_ld;
2065
2066 struct {
2067 struct megasas_evtarg_pd pd;
2068 struct megasas_progress prog;
2069 } __attribute__ ((packed)) pd_prog;
2070
2071 struct {
2072 struct megasas_evtarg_pd pd;
2073 u32 prevState;
2074 u32 newState;
2075 } __attribute__ ((packed)) pd_state;
2076
2077 struct {
2078 u16 vendorId;
2079 __le16 deviceId;
2080 u16 subVendorId;
2081 u16 subDeviceId;
2082 } __attribute__ ((packed)) pci;
2083
2084 u32 rate;
2085 char str[96];
2086
2087 struct {
2088 u32 rtc;
2089 u32 elapsedSeconds;
2090 } __attribute__ ((packed)) time;
2091
2092 struct {
2093 u32 ecar;
2094 u32 elog;
2095 char str[64];
2096 } __attribute__ ((packed)) ecc;
2097
2098 u8 b[96];
2099 __le16 s[48];
2100 __le32 w[24];
2101 __le64 d[12];
2102 } args;
2103
2104 char description[128];
2105
2106 } __attribute__ ((packed));
2107
2108 struct megasas_aen_event {
2109 struct delayed_work hotplug_work;
2110 struct megasas_instance *instance;
2111 };
2112
2113 struct megasas_irq_context {
2114 struct megasas_instance *instance;
2115 u32 MSIxIndex;
2116 };
2117
2118 struct MR_DRV_SYSTEM_INFO {
2119 u8 infoVersion;
2120 u8 systemIdLength;
2121 u16 reserved0;
2122 u8 systemId[64];
2123 u8 reserved[1980];
2124 };
2125
2126 enum MR_PD_TYPE {
2127 UNKNOWN_DRIVE = 0,
2128 PARALLEL_SCSI = 1,
2129 SAS_PD = 2,
2130 SATA_PD = 3,
2131 FC_PD = 4,
2132 NVME_PD = 5,
2133 };
2134
2135 /* JBOD Queue depth definitions */
2136 #define MEGASAS_SATA_QD 32
2137 #define MEGASAS_SAS_QD 64
2138 #define MEGASAS_DEFAULT_PD_QD 64
2139 #define MEGASAS_NVME_QD 32
2140
2141 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
2142 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
2143 #define MR_DEFAULT_NVME_MDTS_KB 128
2144 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2145
2146 struct megasas_instance {
2147
2148 unsigned int *reply_map;
2149 __le32 *producer;
2150 dma_addr_t producer_h;
2151 __le32 *consumer;
2152 dma_addr_t consumer_h;
2153 struct MR_DRV_SYSTEM_INFO *system_info_buf;
2154 dma_addr_t system_info_h;
2155 struct MR_LD_VF_AFFILIATION *vf_affiliation;
2156 dma_addr_t vf_affiliation_h;
2157 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2158 dma_addr_t vf_affiliation_111_h;
2159 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2160 dma_addr_t hb_host_mem_h;
2161 struct MR_PD_INFO *pd_info;
2162 dma_addr_t pd_info_h;
2163 struct MR_TARGET_PROPERTIES *tgt_prop;
2164 dma_addr_t tgt_prop_h;
2165
2166 __le32 *reply_queue;
2167 dma_addr_t reply_queue_h;
2168
2169 u32 *crash_dump_buf;
2170 dma_addr_t crash_dump_h;
2171
2172 struct MR_PD_LIST *pd_list_buf;
2173 dma_addr_t pd_list_buf_h;
2174
2175 struct megasas_ctrl_info *ctrl_info_buf;
2176 dma_addr_t ctrl_info_buf_h;
2177
2178 struct MR_LD_LIST *ld_list_buf;
2179 dma_addr_t ld_list_buf_h;
2180
2181 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2182 dma_addr_t ld_targetid_list_buf_h;
2183
2184 void *crash_buf[MAX_CRASH_DUMP_SIZE];
2185 unsigned int fw_crash_buffer_size;
2186 unsigned int fw_crash_state;
2187 unsigned int fw_crash_buffer_offset;
2188 u32 drv_buf_index;
2189 u32 drv_buf_alloc;
2190 u32 crash_dump_fw_support;
2191 u32 crash_dump_drv_support;
2192 u32 crash_dump_app_support;
2193 u32 secure_jbod_support;
2194 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2195 bool use_seqnum_jbod_fp; /* Added for PD sequence */
2196 spinlock_t crashdump_lock;
2197
2198 struct megasas_register_set __iomem *reg_set;
2199 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2200 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
2201 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
2202 u8 ld_ids[MEGASAS_MAX_LD_IDS];
2203 s8 init_id;
2204
2205 u16 max_num_sge;
2206 u16 max_fw_cmds;
2207 u16 max_mpt_cmds;
2208 u16 max_mfi_cmds;
2209 u16 max_scsi_cmds;
2210 u16 ldio_threshold;
2211 u16 cur_can_queue;
2212 u32 max_sectors_per_req;
2213 struct megasas_aen_event *ev;
2214
2215 struct megasas_cmd **cmd_list;
2216 struct list_head cmd_pool;
2217 /* used to sync fire the cmd to fw */
2218 spinlock_t mfi_pool_lock;
2219 /* used to sync fire the cmd to fw */
2220 spinlock_t hba_lock;
2221 /* used to synch producer, consumer ptrs in dpc */
2222 spinlock_t stream_lock;
2223 spinlock_t completion_lock;
2224 struct dma_pool *frame_dma_pool;
2225 struct dma_pool *sense_dma_pool;
2226
2227 struct megasas_evt_detail *evt_detail;
2228 dma_addr_t evt_detail_h;
2229 struct megasas_cmd *aen_cmd;
2230 struct semaphore ioctl_sem;
2231
2232 struct Scsi_Host *host;
2233
2234 wait_queue_head_t int_cmd_wait_q;
2235 wait_queue_head_t abort_cmd_wait_q;
2236
2237 struct pci_dev *pdev;
2238 u32 unique_id;
2239 u32 fw_support_ieee;
2240
2241 atomic_t fw_outstanding;
2242 atomic_t ldio_outstanding;
2243 atomic_t fw_reset_no_pci_access;
2244 atomic_t ieee_sgl;
2245 atomic_t prp_sgl;
2246 atomic_t sge_holes_type1;
2247 atomic_t sge_holes_type2;
2248 atomic_t sge_holes_type3;
2249
2250 struct megasas_instance_template *instancet;
2251 struct tasklet_struct isr_tasklet;
2252 struct work_struct work_init;
2253 struct work_struct crash_init;
2254
2255 u8 flag;
2256 u8 unload;
2257 u8 flag_ieee;
2258 u8 issuepend_done;
2259 u8 disableOnlineCtrlReset;
2260 u8 UnevenSpanSupport;
2261
2262 u8 supportmax256vd;
2263 u8 pd_list_not_supported;
2264 u16 fw_supported_vd_count;
2265 u16 fw_supported_pd_count;
2266
2267 u16 drv_supported_vd_count;
2268 u16 drv_supported_pd_count;
2269
2270 atomic_t adprecovery;
2271 unsigned long last_time;
2272 u32 mfiStatus;
2273 u32 last_seq_num;
2274
2275 struct list_head internal_reset_pending_q;
2276
2277 /* Ptr to hba specific information */
2278 void *ctrl_context;
2279 unsigned int msix_vectors;
2280 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2281 u64 map_id;
2282 u64 pd_seq_map_id;
2283 struct megasas_cmd *map_update_cmd;
2284 struct megasas_cmd *jbod_seq_cmd;
2285 unsigned long bar;
2286 long reset_flags;
2287 struct mutex reset_mutex;
2288 struct timer_list sriov_heartbeat_timer;
2289 char skip_heartbeat_timer_del;
2290 u8 requestorId;
2291 char PlasmaFW111;
2292 char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2293 u8 peerIsPresent;
2294 u8 passive;
2295 u16 throttlequeuedepth;
2296 u8 mask_interrupts;
2297 u16 max_chain_frame_sz;
2298 u8 is_imr;
2299 u8 is_rdpq;
2300 bool dev_handle;
2301 bool fw_sync_cache_support;
2302 u32 mfi_frame_size;
2303 bool msix_combined;
2304 u16 max_raid_mapsize;
2305 /* preffered count to send as LDIO irrspective of FP capable.*/
2306 u8 r1_ldio_hint_default;
2307 u32 nvme_page_size;
2308 u8 adapter_type;
2309 bool consistent_mask_64bit;
2310 bool support_nvme_passthru;
2311 u8 task_abort_tmo;
2312 u8 max_reset_tmo;
2313 };
2314 struct MR_LD_VF_MAP {
2315 u32 size;
2316 union MR_LD_REF ref;
2317 u8 ldVfCount;
2318 u8 reserved[6];
2319 u8 policy[1];
2320 };
2321
2322 struct MR_LD_VF_AFFILIATION {
2323 u32 size;
2324 u8 ldCount;
2325 u8 vfCount;
2326 u8 thisVf;
2327 u8 reserved[9];
2328 struct MR_LD_VF_MAP map[1];
2329 };
2330
2331 /* Plasma 1.11 FW backward compatibility structures */
2332 #define IOV_111_OFFSET 0x7CE
2333 #define MAX_VIRTUAL_FUNCTIONS 8
2334 #define MR_LD_ACCESS_HIDDEN 15
2335
2336 struct IOV_111 {
2337 u8 maxVFsSupported;
2338 u8 numVFsEnabled;
2339 u8 requestorId;
2340 u8 reserved[5];
2341 };
2342
2343 struct MR_LD_VF_MAP_111 {
2344 u8 targetId;
2345 u8 reserved[3];
2346 u8 policy[MAX_VIRTUAL_FUNCTIONS];
2347 };
2348
2349 struct MR_LD_VF_AFFILIATION_111 {
2350 u8 vdCount;
2351 u8 vfCount;
2352 u8 thisVf;
2353 u8 reserved[5];
2354 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2355 };
2356
2357 struct MR_CTRL_HB_HOST_MEM {
2358 struct {
2359 u32 fwCounter; /* Firmware heart beat counter */
2360 struct {
2361 u32 debugmode:1; /* 1=Firmware is in debug mode.
2362 Heart beat will not be updated. */
2363 u32 reserved:31;
2364 } debug;
2365 u32 reserved_fw[6];
2366 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2367 u32 reserved_driver[7];
2368 } HB;
2369 u8 pad[0x400-0x40];
2370 };
2371
2372 enum {
2373 MEGASAS_HBA_OPERATIONAL = 0,
2374 MEGASAS_ADPRESET_SM_INFAULT = 1,
2375 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
2376 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
2377 MEGASAS_HW_CRITICAL_ERROR = 4,
2378 MEGASAS_ADPRESET_SM_POLLING = 5,
2379 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2380 };
2381
2382 struct megasas_instance_template {
2383 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2384 u32, struct megasas_register_set __iomem *);
2385
2386 void (*enable_intr)(struct megasas_instance *);
2387 void (*disable_intr)(struct megasas_instance *);
2388
2389 int (*clear_intr)(struct megasas_register_set __iomem *);
2390
2391 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
2392 int (*adp_reset)(struct megasas_instance *, \
2393 struct megasas_register_set __iomem *);
2394 int (*check_reset)(struct megasas_instance *, \
2395 struct megasas_register_set __iomem *);
2396 irqreturn_t (*service_isr)(int irq, void *devp);
2397 void (*tasklet)(unsigned long);
2398 u32 (*init_adapter)(struct megasas_instance *);
2399 u32 (*build_and_issue_cmd) (struct megasas_instance *,
2400 struct scsi_cmnd *);
2401 void (*issue_dcmd)(struct megasas_instance *instance,
2402 struct megasas_cmd *cmd);
2403 };
2404
2405 #define MEGASAS_IS_LOGICAL(sdev) \
2406 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2407
2408 #define MEGASAS_DEV_INDEX(scp) \
2409 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2410 scp->device->id)
2411
2412 #define MEGASAS_PD_INDEX(scp) \
2413 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2414 scp->device->id)
2415
2416 struct megasas_cmd {
2417
2418 union megasas_frame *frame;
2419 dma_addr_t frame_phys_addr;
2420 u8 *sense;
2421 dma_addr_t sense_phys_addr;
2422
2423 u32 index;
2424 u8 sync_cmd;
2425 u8 cmd_status_drv;
2426 u8 abort_aen;
2427 u8 retry_for_fw_reset;
2428
2429
2430 struct list_head list;
2431 struct scsi_cmnd *scmd;
2432 u8 flags;
2433
2434 struct megasas_instance *instance;
2435 union {
2436 struct {
2437 u16 smid;
2438 u16 resvd;
2439 } context;
2440 u32 frame_count;
2441 };
2442 };
2443
2444 #define MAX_MGMT_ADAPTERS 1024
2445 #define MAX_IOCTL_SGE 16
2446
2447 struct megasas_iocpacket {
2448
2449 u16 host_no;
2450 u16 __pad1;
2451 u32 sgl_off;
2452 u32 sge_count;
2453 u32 sense_off;
2454 u32 sense_len;
2455 union {
2456 u8 raw[128];
2457 struct megasas_header hdr;
2458 } frame;
2459
2460 struct iovec sgl[MAX_IOCTL_SGE];
2461
2462 } __attribute__ ((packed));
2463
2464 struct megasas_aen {
2465 u16 host_no;
2466 u16 __pad1;
2467 u32 seq_num;
2468 u32 class_locale_word;
2469 } __attribute__ ((packed));
2470
2471 #ifdef CONFIG_COMPAT
2472 struct compat_megasas_iocpacket {
2473 u16 host_no;
2474 u16 __pad1;
2475 u32 sgl_off;
2476 u32 sge_count;
2477 u32 sense_off;
2478 u32 sense_len;
2479 union {
2480 u8 raw[128];
2481 struct megasas_header hdr;
2482 } frame;
2483 struct compat_iovec sgl[MAX_IOCTL_SGE];
2484 } __attribute__ ((packed));
2485
2486 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2487 #endif
2488
2489 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2490 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2491
2492 struct megasas_mgmt_info {
2493
2494 u16 count;
2495 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2496 int max_index;
2497 };
2498
2499 enum MEGASAS_OCR_CAUSE {
2500 FW_FAULT_OCR = 0,
2501 SCSIIO_TIMEOUT_OCR = 1,
2502 MFI_IO_TIMEOUT_OCR = 2,
2503 };
2504
2505 enum DCMD_RETURN_STATUS {
2506 DCMD_SUCCESS = 0,
2507 DCMD_TIMEOUT = 1,
2508 DCMD_FAILED = 2,
2509 DCMD_NOT_FIRED = 3,
2510 };
2511
2512 u8
2513 MR_BuildRaidContext(struct megasas_instance *instance,
2514 struct IO_REQUEST_INFO *io_info,
2515 struct RAID_CONTEXT *pRAID_Context,
2516 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2517 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2518 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2519 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2520 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2521 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2522 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2523
2524 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2525 struct LD_LOAD_BALANCE_INFO *lbInfo,
2526 struct IO_REQUEST_INFO *in_info,
2527 struct MR_DRV_RAID_MAP_ALL *drv_map);
2528 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2529 struct LD_LOAD_BALANCE_INFO *lbInfo);
2530 int megasas_get_ctrl_info(struct megasas_instance *instance);
2531 /* PD sequence */
2532 int
2533 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2534 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2535 bool is_target_prop);
2536 int megasas_get_target_prop(struct megasas_instance *instance,
2537 struct scsi_device *sdev);
2538
2539 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2540 u8 crash_buf_state);
2541 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2542 void megasas_fusion_crash_dump_wq(struct work_struct *work);
2543
2544 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2545 struct megasas_cmd_fusion *cmd);
2546 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2547 struct megasas_cmd *cmd, int timeout);
2548 void __megasas_return_cmd(struct megasas_instance *instance,
2549 struct megasas_cmd *cmd);
2550
2551 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2552 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2553 int megasas_cmd_type(struct scsi_cmnd *cmd);
2554 void megasas_setup_jbod_map(struct megasas_instance *instance);
2555
2556 void megasas_update_sdev_properties(struct scsi_device *sdev);
2557 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2558 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2559 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2560 u32 mega_mod64(u64 dividend, u32 divisor);
2561 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2562 void megasas_free_fusion_context(struct megasas_instance *instance);
2563 void megasas_set_dma_settings(struct megasas_instance *instance,
2564 struct megasas_dcmd_frame *dcmd,
2565 dma_addr_t dma_addr, u32 dma_len);
2566 #endif /*LSI_MEGARAID_SAS_H */
Linux with added FPC-III support