2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
50 static void read_main_config_table(struct pm8001_hba_info
*pm8001_ha
)
52 void __iomem
*address
= pm8001_ha
->main_cfg_tbl_addr
;
53 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.signature
=
54 pm8001_mr32(address
, 0x00);
55 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.interface_rev
=
56 pm8001_mr32(address
, 0x04);
57 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.firmware_rev
=
58 pm8001_mr32(address
, 0x08);
59 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.max_out_io
=
60 pm8001_mr32(address
, 0x0C);
61 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.max_sgl
=
62 pm8001_mr32(address
, 0x10);
63 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.ctrl_cap_flag
=
64 pm8001_mr32(address
, 0x14);
65 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.gst_offset
=
66 pm8001_mr32(address
, 0x18);
67 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.inbound_queue_offset
=
68 pm8001_mr32(address
, MAIN_IBQ_OFFSET
);
69 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_queue_offset
=
70 pm8001_mr32(address
, MAIN_OBQ_OFFSET
);
71 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.hda_mode_flag
=
72 pm8001_mr32(address
, MAIN_HDA_FLAGS_OFFSET
);
74 /* read analog Setting offset from the configuration table */
75 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.anolog_setup_table_offset
=
76 pm8001_mr32(address
, MAIN_ANALOG_SETUP_OFFSET
);
78 /* read Error Dump Offset and Length */
79 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_dump_offset0
=
80 pm8001_mr32(address
, MAIN_FATAL_ERROR_RDUMP0_OFFSET
);
81 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_dump_length0
=
82 pm8001_mr32(address
, MAIN_FATAL_ERROR_RDUMP0_LENGTH
);
83 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_dump_offset1
=
84 pm8001_mr32(address
, MAIN_FATAL_ERROR_RDUMP1_OFFSET
);
85 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_dump_length1
=
86 pm8001_mr32(address
, MAIN_FATAL_ERROR_RDUMP1_LENGTH
);
90 * read_general_status_table - read the general status table and save it.
91 * @pm8001_ha: our hba card information
93 static void read_general_status_table(struct pm8001_hba_info
*pm8001_ha
)
95 void __iomem
*address
= pm8001_ha
->general_stat_tbl_addr
;
96 pm8001_ha
->gs_tbl
.pm8001_tbl
.gst_len_mpistate
=
97 pm8001_mr32(address
, 0x00);
98 pm8001_ha
->gs_tbl
.pm8001_tbl
.iq_freeze_state0
=
99 pm8001_mr32(address
, 0x04);
100 pm8001_ha
->gs_tbl
.pm8001_tbl
.iq_freeze_state1
=
101 pm8001_mr32(address
, 0x08);
102 pm8001_ha
->gs_tbl
.pm8001_tbl
.msgu_tcnt
=
103 pm8001_mr32(address
, 0x0C);
104 pm8001_ha
->gs_tbl
.pm8001_tbl
.iop_tcnt
=
105 pm8001_mr32(address
, 0x10);
106 pm8001_ha
->gs_tbl
.pm8001_tbl
.rsvd
=
107 pm8001_mr32(address
, 0x14);
108 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[0] =
109 pm8001_mr32(address
, 0x18);
110 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[1] =
111 pm8001_mr32(address
, 0x1C);
112 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[2] =
113 pm8001_mr32(address
, 0x20);
114 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[3] =
115 pm8001_mr32(address
, 0x24);
116 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[4] =
117 pm8001_mr32(address
, 0x28);
118 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[5] =
119 pm8001_mr32(address
, 0x2C);
120 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[6] =
121 pm8001_mr32(address
, 0x30);
122 pm8001_ha
->gs_tbl
.pm8001_tbl
.phy_state
[7] =
123 pm8001_mr32(address
, 0x34);
124 pm8001_ha
->gs_tbl
.pm8001_tbl
.gpio_input_val
=
125 pm8001_mr32(address
, 0x38);
126 pm8001_ha
->gs_tbl
.pm8001_tbl
.rsvd1
[0] =
127 pm8001_mr32(address
, 0x3C);
128 pm8001_ha
->gs_tbl
.pm8001_tbl
.rsvd1
[1] =
129 pm8001_mr32(address
, 0x40);
130 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[0] =
131 pm8001_mr32(address
, 0x44);
132 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[1] =
133 pm8001_mr32(address
, 0x48);
134 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[2] =
135 pm8001_mr32(address
, 0x4C);
136 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[3] =
137 pm8001_mr32(address
, 0x50);
138 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[4] =
139 pm8001_mr32(address
, 0x54);
140 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[5] =
141 pm8001_mr32(address
, 0x58);
142 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[6] =
143 pm8001_mr32(address
, 0x5C);
144 pm8001_ha
->gs_tbl
.pm8001_tbl
.recover_err_info
[7] =
145 pm8001_mr32(address
, 0x60);
149 * read_inbnd_queue_table - read the inbound queue table and save it.
150 * @pm8001_ha: our hba card information
152 static void read_inbnd_queue_table(struct pm8001_hba_info
*pm8001_ha
)
155 void __iomem
*address
= pm8001_ha
->inbnd_q_tbl_addr
;
156 for (i
= 0; i
< PM8001_MAX_INB_NUM
; i
++) {
157 u32 offset
= i
* 0x20;
158 pm8001_ha
->inbnd_q_tbl
[i
].pi_pci_bar
=
159 get_pci_bar_index(pm8001_mr32(address
, (offset
+ 0x14)));
160 pm8001_ha
->inbnd_q_tbl
[i
].pi_offset
=
161 pm8001_mr32(address
, (offset
+ 0x18));
166 * read_outbnd_queue_table - read the outbound queue table and save it.
167 * @pm8001_ha: our hba card information
169 static void read_outbnd_queue_table(struct pm8001_hba_info
*pm8001_ha
)
172 void __iomem
*address
= pm8001_ha
->outbnd_q_tbl_addr
;
173 for (i
= 0; i
< PM8001_MAX_OUTB_NUM
; i
++) {
174 u32 offset
= i
* 0x24;
175 pm8001_ha
->outbnd_q_tbl
[i
].ci_pci_bar
=
176 get_pci_bar_index(pm8001_mr32(address
, (offset
+ 0x14)));
177 pm8001_ha
->outbnd_q_tbl
[i
].ci_offset
=
178 pm8001_mr32(address
, (offset
+ 0x18));
183 * init_default_table_values - init the default table.
184 * @pm8001_ha: our hba card information
186 static void init_default_table_values(struct pm8001_hba_info
*pm8001_ha
)
189 u32 offsetib
, offsetob
;
190 void __iomem
*addressib
= pm8001_ha
->inbnd_q_tbl_addr
;
191 void __iomem
*addressob
= pm8001_ha
->outbnd_q_tbl_addr
;
193 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.inbound_q_nppd_hppd
= 0;
194 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_hw_event_pid0_3
= 0;
195 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_hw_event_pid4_7
= 0;
196 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_ncq_event_pid0_3
= 0;
197 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_ncq_event_pid4_7
= 0;
198 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_ITNexus_event_pid0_3
=
200 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_ITNexus_event_pid4_7
=
202 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_ssp_event_pid0_3
= 0;
203 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_ssp_event_pid4_7
= 0;
204 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_smp_event_pid0_3
= 0;
205 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_tgt_smp_event_pid4_7
= 0;
207 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.upper_event_log_addr
=
208 pm8001_ha
->memoryMap
.region
[AAP1
].phys_addr_hi
;
209 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.lower_event_log_addr
=
210 pm8001_ha
->memoryMap
.region
[AAP1
].phys_addr_lo
;
211 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.event_log_size
=
212 PM8001_EVENT_LOG_SIZE
;
213 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.event_log_option
= 0x01;
214 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.upper_iop_event_log_addr
=
215 pm8001_ha
->memoryMap
.region
[IOP
].phys_addr_hi
;
216 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.lower_iop_event_log_addr
=
217 pm8001_ha
->memoryMap
.region
[IOP
].phys_addr_lo
;
218 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.iop_event_log_size
=
219 PM8001_EVENT_LOG_SIZE
;
220 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.iop_event_log_option
= 0x01;
221 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_interrupt
= 0x01;
222 for (i
= 0; i
< PM8001_MAX_INB_NUM
; i
++) {
223 pm8001_ha
->inbnd_q_tbl
[i
].element_pri_size_cnt
=
224 PM8001_MPI_QUEUE
| (pm8001_ha
->iomb_size
<< 16) | (0x00<<30);
225 pm8001_ha
->inbnd_q_tbl
[i
].upper_base_addr
=
226 pm8001_ha
->memoryMap
.region
[IB
+ i
].phys_addr_hi
;
227 pm8001_ha
->inbnd_q_tbl
[i
].lower_base_addr
=
228 pm8001_ha
->memoryMap
.region
[IB
+ i
].phys_addr_lo
;
229 pm8001_ha
->inbnd_q_tbl
[i
].base_virt
=
230 (u8
*)pm8001_ha
->memoryMap
.region
[IB
+ i
].virt_ptr
;
231 pm8001_ha
->inbnd_q_tbl
[i
].total_length
=
232 pm8001_ha
->memoryMap
.region
[IB
+ i
].total_len
;
233 pm8001_ha
->inbnd_q_tbl
[i
].ci_upper_base_addr
=
234 pm8001_ha
->memoryMap
.region
[CI
+ i
].phys_addr_hi
;
235 pm8001_ha
->inbnd_q_tbl
[i
].ci_lower_base_addr
=
236 pm8001_ha
->memoryMap
.region
[CI
+ i
].phys_addr_lo
;
237 pm8001_ha
->inbnd_q_tbl
[i
].ci_virt
=
238 pm8001_ha
->memoryMap
.region
[CI
+ i
].virt_ptr
;
240 pm8001_ha
->inbnd_q_tbl
[i
].pi_pci_bar
=
241 get_pci_bar_index(pm8001_mr32(addressib
,
243 pm8001_ha
->inbnd_q_tbl
[i
].pi_offset
=
244 pm8001_mr32(addressib
, (offsetib
+ 0x18));
245 pm8001_ha
->inbnd_q_tbl
[i
].producer_idx
= 0;
246 pm8001_ha
->inbnd_q_tbl
[i
].consumer_index
= 0;
248 for (i
= 0; i
< PM8001_MAX_OUTB_NUM
; i
++) {
249 pm8001_ha
->outbnd_q_tbl
[i
].element_size_cnt
=
250 PM8001_MPI_QUEUE
| (pm8001_ha
->iomb_size
<< 16) | (0x01<<30);
251 pm8001_ha
->outbnd_q_tbl
[i
].upper_base_addr
=
252 pm8001_ha
->memoryMap
.region
[OB
+ i
].phys_addr_hi
;
253 pm8001_ha
->outbnd_q_tbl
[i
].lower_base_addr
=
254 pm8001_ha
->memoryMap
.region
[OB
+ i
].phys_addr_lo
;
255 pm8001_ha
->outbnd_q_tbl
[i
].base_virt
=
256 (u8
*)pm8001_ha
->memoryMap
.region
[OB
+ i
].virt_ptr
;
257 pm8001_ha
->outbnd_q_tbl
[i
].total_length
=
258 pm8001_ha
->memoryMap
.region
[OB
+ i
].total_len
;
259 pm8001_ha
->outbnd_q_tbl
[i
].pi_upper_base_addr
=
260 pm8001_ha
->memoryMap
.region
[PI
+ i
].phys_addr_hi
;
261 pm8001_ha
->outbnd_q_tbl
[i
].pi_lower_base_addr
=
262 pm8001_ha
->memoryMap
.region
[PI
+ i
].phys_addr_lo
;
263 pm8001_ha
->outbnd_q_tbl
[i
].interrup_vec_cnt_delay
=
264 0 | (10 << 16) | (i
<< 24);
265 pm8001_ha
->outbnd_q_tbl
[i
].pi_virt
=
266 pm8001_ha
->memoryMap
.region
[PI
+ i
].virt_ptr
;
268 pm8001_ha
->outbnd_q_tbl
[i
].ci_pci_bar
=
269 get_pci_bar_index(pm8001_mr32(addressob
,
271 pm8001_ha
->outbnd_q_tbl
[i
].ci_offset
=
272 pm8001_mr32(addressob
, (offsetob
+ 0x18));
273 pm8001_ha
->outbnd_q_tbl
[i
].consumer_idx
= 0;
274 pm8001_ha
->outbnd_q_tbl
[i
].producer_index
= 0;
279 * update_main_config_table - update the main default table to the HBA.
280 * @pm8001_ha: our hba card information
282 static void update_main_config_table(struct pm8001_hba_info
*pm8001_ha
)
284 void __iomem
*address
= pm8001_ha
->main_cfg_tbl_addr
;
285 pm8001_mw32(address
, 0x24,
286 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.inbound_q_nppd_hppd
);
287 pm8001_mw32(address
, 0x28,
288 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_hw_event_pid0_3
);
289 pm8001_mw32(address
, 0x2C,
290 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_hw_event_pid4_7
);
291 pm8001_mw32(address
, 0x30,
292 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_ncq_event_pid0_3
);
293 pm8001_mw32(address
, 0x34,
294 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.outbound_ncq_event_pid4_7
);
295 pm8001_mw32(address
, 0x38,
296 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
297 outbound_tgt_ITNexus_event_pid0_3
);
298 pm8001_mw32(address
, 0x3C,
299 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
300 outbound_tgt_ITNexus_event_pid4_7
);
301 pm8001_mw32(address
, 0x40,
302 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
303 outbound_tgt_ssp_event_pid0_3
);
304 pm8001_mw32(address
, 0x44,
305 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
306 outbound_tgt_ssp_event_pid4_7
);
307 pm8001_mw32(address
, 0x48,
308 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
309 outbound_tgt_smp_event_pid0_3
);
310 pm8001_mw32(address
, 0x4C,
311 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.
312 outbound_tgt_smp_event_pid4_7
);
313 pm8001_mw32(address
, 0x50,
314 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.upper_event_log_addr
);
315 pm8001_mw32(address
, 0x54,
316 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.lower_event_log_addr
);
317 pm8001_mw32(address
, 0x58,
318 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.event_log_size
);
319 pm8001_mw32(address
, 0x5C,
320 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.event_log_option
);
321 pm8001_mw32(address
, 0x60,
322 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.upper_iop_event_log_addr
);
323 pm8001_mw32(address
, 0x64,
324 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.lower_iop_event_log_addr
);
325 pm8001_mw32(address
, 0x68,
326 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.iop_event_log_size
);
327 pm8001_mw32(address
, 0x6C,
328 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.iop_event_log_option
);
329 pm8001_mw32(address
, 0x70,
330 pm8001_ha
->main_cfg_tbl
.pm8001_tbl
.fatal_err_interrupt
);
334 * update_inbnd_queue_table - update the inbound queue table to the HBA.
335 * @pm8001_ha: our hba card information
337 static void update_inbnd_queue_table(struct pm8001_hba_info
*pm8001_ha
,
340 void __iomem
*address
= pm8001_ha
->inbnd_q_tbl_addr
;
341 u16 offset
= number
* 0x20;
342 pm8001_mw32(address
, offset
+ 0x00,
343 pm8001_ha
->inbnd_q_tbl
[number
].element_pri_size_cnt
);
344 pm8001_mw32(address
, offset
+ 0x04,
345 pm8001_ha
->inbnd_q_tbl
[number
].upper_base_addr
);
346 pm8001_mw32(address
, offset
+ 0x08,
347 pm8001_ha
->inbnd_q_tbl
[number
].lower_base_addr
);
348 pm8001_mw32(address
, offset
+ 0x0C,
349 pm8001_ha
->inbnd_q_tbl
[number
].ci_upper_base_addr
);
350 pm8001_mw32(address
, offset
+ 0x10,
351 pm8001_ha
->inbnd_q_tbl
[number
].ci_lower_base_addr
);
355 * update_outbnd_queue_table - update the outbound queue table to the HBA.
356 * @pm8001_ha: our hba card information
358 static void update_outbnd_queue_table(struct pm8001_hba_info
*pm8001_ha
,
361 void __iomem
*address
= pm8001_ha
->outbnd_q_tbl_addr
;
362 u16 offset
= number
* 0x24;
363 pm8001_mw32(address
, offset
+ 0x00,
364 pm8001_ha
->outbnd_q_tbl
[number
].element_size_cnt
);
365 pm8001_mw32(address
, offset
+ 0x04,
366 pm8001_ha
->outbnd_q_tbl
[number
].upper_base_addr
);
367 pm8001_mw32(address
, offset
+ 0x08,
368 pm8001_ha
->outbnd_q_tbl
[number
].lower_base_addr
);
369 pm8001_mw32(address
, offset
+ 0x0C,
370 pm8001_ha
->outbnd_q_tbl
[number
].pi_upper_base_addr
);
371 pm8001_mw32(address
, offset
+ 0x10,
372 pm8001_ha
->outbnd_q_tbl
[number
].pi_lower_base_addr
);
373 pm8001_mw32(address
, offset
+ 0x1C,
374 pm8001_ha
->outbnd_q_tbl
[number
].interrup_vec_cnt_delay
);
378 * pm8001_bar4_shift - function is called to shift BAR base address
379 * @pm8001_ha : our hba card infomation
380 * @shiftValue : shifting value in memory bar.
382 int pm8001_bar4_shift(struct pm8001_hba_info
*pm8001_ha
, u32 shiftValue
)
387 /* program the inbound AXI translation Lower Address */
388 pm8001_cw32(pm8001_ha
, 1, SPC_IBW_AXI_TRANSLATION_LOW
, shiftValue
);
390 /* confirm the setting is written */
391 start
= jiffies
+ HZ
; /* 1 sec */
393 regVal
= pm8001_cr32(pm8001_ha
, 1, SPC_IBW_AXI_TRANSLATION_LOW
);
394 } while ((regVal
!= shiftValue
) && time_before(jiffies
, start
));
396 if (regVal
!= shiftValue
) {
397 PM8001_INIT_DBG(pm8001_ha
,
398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
399 " = 0x%x\n", regVal
));
406 * mpi_set_phys_g3_with_ssc
407 * @pm8001_ha: our hba card information
408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info
*pm8001_ha
,
413 u32 value
, offset
, i
;
416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
422 #define SNW3_PHY_CAPABILITIES_PARITY 31
425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
428 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
429 if (-1 == pm8001_bar4_shift(pm8001_ha
,
430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR
)) {
431 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
435 for (i
= 0; i
< 4; i
++) {
436 offset
= SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET
+ 0x4000 * i
;
437 pm8001_cw32(pm8001_ha
, 2, offset
, 0x80001501);
439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
440 if (-1 == pm8001_bar4_shift(pm8001_ha
,
441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR
)) {
442 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
445 for (i
= 4; i
< 8; i
++) {
446 offset
= SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET
+ 0x4000 * (i
-4);
447 pm8001_cw32(pm8001_ha
, 2, offset
, 0x80001501);
449 /*************************************************************
450 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
451 Device MABC SMOD0 Controls
452 Address: (via MEMBASE-III):
453 Using shifted destination address 0x0_0000: with Offset 0xD8
455 31:28 R/W Reserved Do not change
456 27:24 R/W SAS_SMOD_SPRDUP 0000
457 23:20 R/W SAS_SMOD_SPRDDN 0000
458 19:0 R/W Reserved Do not change
459 Upon power-up this register will read as 0x8990c016,
460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
461 so that the written value will be 0x8090c016.
462 This will ensure only down-spreading SSC is enabled on the SPC.
463 *************************************************************/
464 value
= pm8001_cr32(pm8001_ha
, 2, 0xd8);
465 pm8001_cw32(pm8001_ha
, 2, 0xd8, 0x8000C016);
467 /*set the shifted destination address to 0x0 to avoid error operation */
468 pm8001_bar4_shift(pm8001_ha
, 0x0);
469 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
474 * mpi_set_open_retry_interval_reg
475 * @pm8001_ha: our hba card information
476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info
*pm8001_ha
,
486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
492 value
= interval
& OPEN_RETRY_INTERVAL_REG_MASK
;
493 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
495 if (-1 == pm8001_bar4_shift(pm8001_ha
,
496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR
)) {
497 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
500 for (i
= 0; i
< 4; i
++) {
501 offset
= OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET
+ 0x4000 * i
;
502 pm8001_cw32(pm8001_ha
, 2, offset
, value
);
505 if (-1 == pm8001_bar4_shift(pm8001_ha
,
506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR
)) {
507 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
510 for (i
= 4; i
< 8; i
++) {
511 offset
= OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET
+ 0x4000 * (i
-4);
512 pm8001_cw32(pm8001_ha
, 2, offset
, value
);
514 /*set the shifted destination address to 0x0 to avoid error operation */
515 pm8001_bar4_shift(pm8001_ha
, 0x0);
516 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
521 * mpi_init_check - check firmware initialization status.
522 * @pm8001_ha: our hba card information
524 static int mpi_init_check(struct pm8001_hba_info
*pm8001_ha
)
528 u32 gst_len_mpistate
;
529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
531 pm8001_cw32(pm8001_ha
, 0, MSGU_IBDB_SET
, SPC_MSGU_CFG_TABLE_UPDATE
);
532 /* wait until Inbound DoorBell Clear Register toggled */
533 max_wait_count
= 1 * 1000 * 1000;/* 1 sec */
536 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_IBDB_SET
);
537 value
&= SPC_MSGU_CFG_TABLE_UPDATE
;
538 } while ((value
!= 0) && (--max_wait_count
));
542 /* check the MPI-State for initialization */
544 pm8001_mr32(pm8001_ha
->general_stat_tbl_addr
,
545 GST_GSTLEN_MPIS_OFFSET
);
546 if (GST_MPI_STATE_INIT
!= (gst_len_mpistate
& GST_MPI_STATE_MASK
))
548 /* check MPI Initialization error */
549 gst_len_mpistate
= gst_len_mpistate
>> 16;
550 if (0x0000 != gst_len_mpistate
)
556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
557 * @pm8001_ha: our hba card information
559 static int check_fw_ready(struct pm8001_hba_info
*pm8001_ha
)
563 /* check error state */
564 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
);
565 value1
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
);
566 /* check AAP error */
567 if (SCRATCH_PAD1_ERR
== (value
& SCRATCH_PAD_STATE_MASK
)) {
569 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_0
);
573 /* check IOP error */
574 if (SCRATCH_PAD2_ERR
== (value1
& SCRATCH_PAD_STATE_MASK
)) {
576 value1
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_3
);
580 /* bit 4-31 of scratch pad1 should be zeros if it is not
582 if (value
& SCRATCH_PAD1_STATE_MASK
) {
584 pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_0
);
588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
590 if (value1
& SCRATCH_PAD2_STATE_MASK
) {
595 max_wait_count
= 1 * 1000 * 1000;/* 1 sec timeout */
597 /* wait until scratch pad 1 and 2 registers in ready state */
600 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
)
602 value1
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
)
604 if ((--max_wait_count
) == 0)
606 } while ((value
!= SCRATCH_PAD1_RDY
) || (value1
!= SCRATCH_PAD2_RDY
));
610 static void init_pci_device_addresses(struct pm8001_hba_info
*pm8001_ha
)
612 void __iomem
*base_addr
;
618 value
= pm8001_cr32(pm8001_ha
, 0, 0x44);
619 offset
= value
& 0x03FFFFFF;
620 PM8001_INIT_DBG(pm8001_ha
,
621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset
));
622 pcilogic
= (value
& 0xFC000000) >> 26;
623 pcibar
= get_pci_bar_index(pcilogic
);
624 PM8001_INIT_DBG(pm8001_ha
,
625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar
));
626 pm8001_ha
->main_cfg_tbl_addr
= base_addr
=
627 pm8001_ha
->io_mem
[pcibar
].memvirtaddr
+ offset
;
628 pm8001_ha
->general_stat_tbl_addr
=
629 base_addr
+ pm8001_cr32(pm8001_ha
, pcibar
, offset
+ 0x18);
630 pm8001_ha
->inbnd_q_tbl_addr
=
631 base_addr
+ pm8001_cr32(pm8001_ha
, pcibar
, offset
+ 0x1C);
632 pm8001_ha
->outbnd_q_tbl_addr
=
633 base_addr
+ pm8001_cr32(pm8001_ha
, pcibar
, offset
+ 0x20);
637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
638 * @pm8001_ha: our hba card information
640 static int pm8001_chip_init(struct pm8001_hba_info
*pm8001_ha
)
644 pci_read_config_word(pm8001_ha
->pdev
, PCI_DEVICE_ID
, &deviceid
);
645 /* 8081 controllers need BAR shift to access MPI space
646 * as this is shared with BIOS data */
647 if (deviceid
== 0x8081 || deviceid
== 0x0042) {
648 if (-1 == pm8001_bar4_shift(pm8001_ha
, GSM_SM_BASE
)) {
649 PM8001_FAIL_DBG(pm8001_ha
,
650 pm8001_printk("Shift Bar4 to 0x%x failed\n",
655 /* check the firmware status */
656 if (-1 == check_fw_ready(pm8001_ha
)) {
657 PM8001_FAIL_DBG(pm8001_ha
,
658 pm8001_printk("Firmware is not ready!\n"));
662 /* Initialize pci space address eg: mpi offset */
663 init_pci_device_addresses(pm8001_ha
);
664 init_default_table_values(pm8001_ha
);
665 read_main_config_table(pm8001_ha
);
666 read_general_status_table(pm8001_ha
);
667 read_inbnd_queue_table(pm8001_ha
);
668 read_outbnd_queue_table(pm8001_ha
);
669 /* update main config table ,inbound table and outbound table */
670 update_main_config_table(pm8001_ha
);
671 for (i
= 0; i
< PM8001_MAX_INB_NUM
; i
++)
672 update_inbnd_queue_table(pm8001_ha
, i
);
673 for (i
= 0; i
< PM8001_MAX_OUTB_NUM
; i
++)
674 update_outbnd_queue_table(pm8001_ha
, i
);
675 /* 8081 controller donot require these operations */
676 if (deviceid
!= 0x8081 && deviceid
!= 0x0042) {
677 mpi_set_phys_g3_with_ssc(pm8001_ha
, 0);
678 /* 7->130ms, 34->500ms, 119->1.5s */
679 mpi_set_open_retry_interval_reg(pm8001_ha
, 119);
681 /* notify firmware update finished and check initialization status */
682 if (0 == mpi_init_check(pm8001_ha
)) {
683 PM8001_INIT_DBG(pm8001_ha
,
684 pm8001_printk("MPI initialize successful!\n"));
687 /*This register is a 16-bit timer with a resolution of 1us. This is the
688 timer used for interrupt delay/coalescing in the PCIe Application Layer.
689 Zero is not a valid value. A value of 1 in the register will cause the
690 interrupts to be normal. A value greater than 1 will cause coalescing
692 pm8001_cw32(pm8001_ha
, 1, 0x0033c0, 0x1);
693 pm8001_cw32(pm8001_ha
, 1, 0x0033c4, 0x0);
697 static int mpi_uninit_check(struct pm8001_hba_info
*pm8001_ha
)
701 u32 gst_len_mpistate
;
703 pci_read_config_word(pm8001_ha
->pdev
, PCI_DEVICE_ID
, &deviceid
);
704 if (deviceid
== 0x8081 || deviceid
== 0x0042) {
705 if (-1 == pm8001_bar4_shift(pm8001_ha
, GSM_SM_BASE
)) {
706 PM8001_FAIL_DBG(pm8001_ha
,
707 pm8001_printk("Shift Bar4 to 0x%x failed\n",
712 init_pci_device_addresses(pm8001_ha
);
713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
715 pm8001_cw32(pm8001_ha
, 0, MSGU_IBDB_SET
, SPC_MSGU_CFG_TABLE_RESET
);
717 /* wait until Inbound DoorBell Clear Register toggled */
718 max_wait_count
= 1 * 1000 * 1000;/* 1 sec */
721 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_IBDB_SET
);
722 value
&= SPC_MSGU_CFG_TABLE_RESET
;
723 } while ((value
!= 0) && (--max_wait_count
));
725 if (!max_wait_count
) {
726 PM8001_FAIL_DBG(pm8001_ha
,
727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value
));
731 /* check the MPI-State for termination in progress */
732 /* wait until Inbound DoorBell Clear Register toggled */
733 max_wait_count
= 1 * 1000 * 1000; /* 1 sec */
737 pm8001_mr32(pm8001_ha
->general_stat_tbl_addr
,
738 GST_GSTLEN_MPIS_OFFSET
);
739 if (GST_MPI_STATE_UNINIT
==
740 (gst_len_mpistate
& GST_MPI_STATE_MASK
))
742 } while (--max_wait_count
);
743 if (!max_wait_count
) {
744 PM8001_FAIL_DBG(pm8001_ha
,
745 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
746 gst_len_mpistate
& GST_MPI_STATE_MASK
));
753 * soft_reset_ready_check - Function to check FW is ready for soft reset.
754 * @pm8001_ha: our hba card information
756 static u32
soft_reset_ready_check(struct pm8001_hba_info
*pm8001_ha
)
758 u32 regVal
, regVal1
, regVal2
;
759 if (mpi_uninit_check(pm8001_ha
) != 0) {
760 PM8001_FAIL_DBG(pm8001_ha
,
761 pm8001_printk("MPI state is not ready\n"));
764 /* read the scratch pad 2 register bit 2 */
765 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
)
766 & SCRATCH_PAD2_FWRDY_RST
;
767 if (regVal
== SCRATCH_PAD2_FWRDY_RST
) {
768 PM8001_INIT_DBG(pm8001_ha
,
769 pm8001_printk("Firmware is ready for reset .\n"));
772 /* Trigger NMI twice via RB6 */
773 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
774 if (-1 == pm8001_bar4_shift(pm8001_ha
, RB6_ACCESS_REG
)) {
775 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
776 PM8001_FAIL_DBG(pm8001_ha
,
777 pm8001_printk("Shift Bar4 to 0x%x failed\n",
781 pm8001_cw32(pm8001_ha
, 2, SPC_RB6_OFFSET
,
782 RB6_MAGIC_NUMBER_RST
);
783 pm8001_cw32(pm8001_ha
, 2, SPC_RB6_OFFSET
, RB6_MAGIC_NUMBER_RST
);
784 /* wait for 100 ms */
786 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
) &
787 SCRATCH_PAD2_FWRDY_RST
;
788 if (regVal
!= SCRATCH_PAD2_FWRDY_RST
) {
789 regVal1
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
);
790 regVal2
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
);
791 PM8001_FAIL_DBG(pm8001_ha
,
792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
795 PM8001_FAIL_DBG(pm8001_ha
,
796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_0
)));
798 PM8001_FAIL_DBG(pm8001_ha
,
799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_3
)));
801 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
804 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
815 pm8001_chip_soft_rst(struct pm8001_hba_info
*pm8001_ha
)
817 u32 regVal
, toggleVal
;
819 u32 regVal1
, regVal2
, regVal3
;
820 u32 signature
= 0x252acbcd; /* for host scratch pad0 */
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha
) != 0) {
825 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("FW is not ready\n"));
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
832 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
833 if (-1 == pm8001_bar4_shift(pm8001_ha
, MBIC_AAP1_ADDR_BASE
)) {
834 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
835 PM8001_FAIL_DBG(pm8001_ha
,
836 pm8001_printk("Shift Bar4 to 0x%x failed\n",
837 MBIC_AAP1_ADDR_BASE
));
840 regVal
= pm8001_cr32(pm8001_ha
, 2, MBIC_NMI_ENABLE_VPE0_IOP
);
841 PM8001_INIT_DBG(pm8001_ha
,
842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal
));
843 pm8001_cw32(pm8001_ha
, 2, MBIC_NMI_ENABLE_VPE0_IOP
, 0x0);
844 /* map 0x70000 to BAR4(0x20), BAR2(win) */
845 if (-1 == pm8001_bar4_shift(pm8001_ha
, MBIC_IOP_ADDR_BASE
)) {
846 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
847 PM8001_FAIL_DBG(pm8001_ha
,
848 pm8001_printk("Shift Bar4 to 0x%x failed\n",
849 MBIC_IOP_ADDR_BASE
));
852 regVal
= pm8001_cr32(pm8001_ha
, 2, MBIC_NMI_ENABLE_VPE0_AAP1
);
853 PM8001_INIT_DBG(pm8001_ha
,
854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal
));
855 pm8001_cw32(pm8001_ha
, 2, MBIC_NMI_ENABLE_VPE0_AAP1
, 0x0);
857 regVal
= pm8001_cr32(pm8001_ha
, 1, PCIE_EVENT_INTERRUPT_ENABLE
);
858 PM8001_INIT_DBG(pm8001_ha
,
859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal
));
860 pm8001_cw32(pm8001_ha
, 1, PCIE_EVENT_INTERRUPT_ENABLE
, 0x0);
862 regVal
= pm8001_cr32(pm8001_ha
, 1, PCIE_EVENT_INTERRUPT
);
863 PM8001_INIT_DBG(pm8001_ha
,
864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal
));
865 pm8001_cw32(pm8001_ha
, 1, PCIE_EVENT_INTERRUPT
, regVal
);
867 regVal
= pm8001_cr32(pm8001_ha
, 1, PCIE_ERROR_INTERRUPT_ENABLE
);
868 PM8001_INIT_DBG(pm8001_ha
,
869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal
));
870 pm8001_cw32(pm8001_ha
, 1, PCIE_ERROR_INTERRUPT_ENABLE
, 0x0);
872 regVal
= pm8001_cr32(pm8001_ha
, 1, PCIE_ERROR_INTERRUPT
);
873 PM8001_INIT_DBG(pm8001_ha
,
874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal
));
875 pm8001_cw32(pm8001_ha
, 1, PCIE_ERROR_INTERRUPT
, regVal
);
877 /* read the scratch pad 1 register bit 2 */
878 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
)
880 toggleVal
= regVal
^ SCRATCH_PAD1_RST
;
882 /* set signature in host scratch pad0 register to tell SPC that the
883 host performs the soft reset */
884 pm8001_cw32(pm8001_ha
, 0, MSGU_HOST_SCRATCH_PAD_0
, signature
);
886 /* read required registers for confirmming */
887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
888 if (-1 == pm8001_bar4_shift(pm8001_ha
, GSM_ADDR_BASE
)) {
889 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
890 PM8001_FAIL_DBG(pm8001_ha
,
891 pm8001_printk("Shift Bar4 to 0x%x failed\n",
895 PM8001_INIT_DBG(pm8001_ha
,
896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
898 pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
)));
900 /* step 3: host read GSM Configuration and Reset register */
901 regVal
= pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
);
902 /* Put those bits to low */
903 /* GSM XCBI offset = 0x70 0000
904 0x00 Bit 13 COM_SLV_SW_RSTB 1
905 0x00 Bit 12 QSSP_SW_RSTB 1
906 0x00 Bit 11 RAAE_SW_RSTB 1
907 0x00 Bit 9 RB_1_SW_RSTB 1
908 0x00 Bit 8 SM_SW_RSTB 1
910 regVal
&= ~(0x00003b00);
911 /* host write GSM Configuration and Reset register */
912 pm8001_cw32(pm8001_ha
, 2, GSM_CONFIG_RESET
, regVal
);
913 PM8001_INIT_DBG(pm8001_ha
,
914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
915 "Configuration and Reset is set to = 0x%x\n",
916 pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
)));
919 /* disable GSM - Read Address Parity Check */
920 regVal1
= pm8001_cr32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
);
921 PM8001_INIT_DBG(pm8001_ha
,
922 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
923 "Enable = 0x%x\n", regVal1
));
924 pm8001_cw32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
, 0x0);
925 PM8001_INIT_DBG(pm8001_ha
,
926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
927 "is set to = 0x%x\n",
928 pm8001_cr32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
)));
930 /* disable GSM - Write Address Parity Check */
931 regVal2
= pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
);
932 PM8001_INIT_DBG(pm8001_ha
,
933 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
934 " Enable = 0x%x\n", regVal2
));
935 pm8001_cw32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
, 0x0);
936 PM8001_INIT_DBG(pm8001_ha
,
937 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
938 "Enable is set to = 0x%x\n",
939 pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
)));
941 /* disable GSM - Write Data Parity Check */
942 regVal3
= pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
);
943 PM8001_INIT_DBG(pm8001_ha
,
944 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
945 " Enable = 0x%x\n", regVal3
));
946 pm8001_cw32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
, 0x0);
947 PM8001_INIT_DBG(pm8001_ha
,
948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
949 "is set to = 0x%x\n",
950 pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
)));
952 /* step 5: delay 10 usec */
954 /* step 5-b: set GPIO-0 output control to tristate anyway */
955 if (-1 == pm8001_bar4_shift(pm8001_ha
, GPIO_ADDR_BASE
)) {
956 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
957 PM8001_INIT_DBG(pm8001_ha
,
958 pm8001_printk("Shift Bar4 to 0x%x failed\n",
962 regVal
= pm8001_cr32(pm8001_ha
, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET
);
963 PM8001_INIT_DBG(pm8001_ha
,
964 pm8001_printk("GPIO Output Control Register:"
965 " = 0x%x\n", regVal
));
966 /* set GPIO-0 output control to tri-state */
967 regVal
&= 0xFFFFFFFC;
968 pm8001_cw32(pm8001_ha
, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET
, regVal
);
970 /* Step 6: Reset the IOP and AAP1 */
971 /* map 0x00000 to BAR4(0x20), BAR2(win) */
972 if (-1 == pm8001_bar4_shift(pm8001_ha
, SPC_TOP_LEVEL_ADDR_BASE
)) {
973 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
974 PM8001_FAIL_DBG(pm8001_ha
,
975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
976 SPC_TOP_LEVEL_ADDR_BASE
));
979 regVal
= pm8001_cr32(pm8001_ha
, 2, SPC_REG_RESET
);
980 PM8001_INIT_DBG(pm8001_ha
,
981 pm8001_printk("Top Register before resetting IOP/AAP1"
982 ":= 0x%x\n", regVal
));
983 regVal
&= ~(SPC_REG_RESET_PCS_IOP_SS
| SPC_REG_RESET_PCS_AAP1_SS
);
984 pm8001_cw32(pm8001_ha
, 2, SPC_REG_RESET
, regVal
);
986 /* step 7: Reset the BDMA/OSSP */
987 regVal
= pm8001_cr32(pm8001_ha
, 2, SPC_REG_RESET
);
988 PM8001_INIT_DBG(pm8001_ha
,
989 pm8001_printk("Top Register before resetting BDMA/OSSP"
990 ": = 0x%x\n", regVal
));
991 regVal
&= ~(SPC_REG_RESET_BDMA_CORE
| SPC_REG_RESET_OSSP
);
992 pm8001_cw32(pm8001_ha
, 2, SPC_REG_RESET
, regVal
);
994 /* step 8: delay 10 usec */
997 /* step 9: bring the BDMA and OSSP out of reset */
998 regVal
= pm8001_cr32(pm8001_ha
, 2, SPC_REG_RESET
);
999 PM8001_INIT_DBG(pm8001_ha
,
1000 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001 ":= 0x%x\n", regVal
));
1002 regVal
|= (SPC_REG_RESET_BDMA_CORE
| SPC_REG_RESET_OSSP
);
1003 pm8001_cw32(pm8001_ha
, 2, SPC_REG_RESET
, regVal
);
1005 /* step 10: delay 10 usec */
1008 /* step 11: reads and sets the GSM Configuration and Reset Register */
1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010 if (-1 == pm8001_bar4_shift(pm8001_ha
, GSM_ADDR_BASE
)) {
1011 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1012 PM8001_FAIL_DBG(pm8001_ha
,
1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1017 PM8001_INIT_DBG(pm8001_ha
,
1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
)));
1020 regVal
= pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
);
1021 /* Put those bits to high */
1022 /* GSM XCBI offset = 0x70 0000
1023 0x00 Bit 13 COM_SLV_SW_RSTB 1
1024 0x00 Bit 12 QSSP_SW_RSTB 1
1025 0x00 Bit 11 RAAE_SW_RSTB 1
1026 0x00 Bit 9 RB_1_SW_RSTB 1
1027 0x00 Bit 8 SM_SW_RSTB 1
1029 regVal
|= (GSM_CONFIG_RESET_VALUE
);
1030 pm8001_cw32(pm8001_ha
, 2, GSM_CONFIG_RESET
, regVal
);
1031 PM8001_INIT_DBG(pm8001_ha
,
1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033 " Configuration and Reset is set to = 0x%x\n",
1034 pm8001_cr32(pm8001_ha
, 2, GSM_CONFIG_RESET
)));
1036 /* step 12: Restore GSM - Read Address Parity Check */
1037 regVal
= pm8001_cr32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
);
1038 /* just for debugging */
1039 PM8001_INIT_DBG(pm8001_ha
,
1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041 " = 0x%x\n", regVal
));
1042 pm8001_cw32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
, regVal1
);
1043 PM8001_INIT_DBG(pm8001_ha
,
1044 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045 " Check Enable is set to = 0x%x\n",
1046 pm8001_cr32(pm8001_ha
, 2, GSM_READ_ADDR_PARITY_CHECK
)));
1047 /* Restore GSM - Write Address Parity Check */
1048 regVal
= pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
);
1049 pm8001_cw32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
, regVal2
);
1050 PM8001_INIT_DBG(pm8001_ha
,
1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052 " Enable is set to = 0x%x\n",
1053 pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_ADDR_PARITY_CHECK
)));
1054 /* Restore GSM - Write Data Parity Check */
1055 regVal
= pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
);
1056 pm8001_cw32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
, regVal3
);
1057 PM8001_INIT_DBG(pm8001_ha
,
1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059 "is set to = 0x%x\n",
1060 pm8001_cr32(pm8001_ha
, 2, GSM_WRITE_DATA_PARITY_CHECK
)));
1062 /* step 13: bring the IOP and AAP1 out of reset */
1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064 if (-1 == pm8001_bar4_shift(pm8001_ha
, SPC_TOP_LEVEL_ADDR_BASE
)) {
1065 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1066 PM8001_FAIL_DBG(pm8001_ha
,
1067 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068 SPC_TOP_LEVEL_ADDR_BASE
));
1071 regVal
= pm8001_cr32(pm8001_ha
, 2, SPC_REG_RESET
);
1072 regVal
|= (SPC_REG_RESET_PCS_IOP_SS
| SPC_REG_RESET_PCS_AAP1_SS
);
1073 pm8001_cw32(pm8001_ha
, 2, SPC_REG_RESET
, regVal
);
1075 /* step 14: delay 10 usec - Normal Mode */
1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078 if (signature
== SPC_SOFT_RESET_SIGNATURE
) {
1079 /* step 15 (Normal Mode): wait until scratch pad1 register
1081 max_wait_count
= 2 * 1000 * 1000;/* 2 sec */
1084 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
) &
1086 } while ((regVal
!= toggleVal
) && (--max_wait_count
));
1088 if (!max_wait_count
) {
1089 regVal
= pm8001_cr32(pm8001_ha
, 0,
1090 MSGU_SCRATCH_PAD_1
);
1091 PM8001_FAIL_DBG(pm8001_ha
,
1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094 toggleVal
, regVal
));
1095 PM8001_FAIL_DBG(pm8001_ha
,
1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097 pm8001_cr32(pm8001_ha
, 0,
1098 MSGU_SCRATCH_PAD_0
)));
1099 PM8001_FAIL_DBG(pm8001_ha
,
1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101 pm8001_cr32(pm8001_ha
, 0,
1102 MSGU_SCRATCH_PAD_2
)));
1103 PM8001_FAIL_DBG(pm8001_ha
,
1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105 pm8001_cr32(pm8001_ha
, 0,
1106 MSGU_SCRATCH_PAD_3
)));
1107 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1111 /* step 16 (Normal) - Clear ODMR and ODCR */
1112 pm8001_cw32(pm8001_ha
, 0, MSGU_ODCR
, ODCR_CLEAR_ALL
);
1113 pm8001_cw32(pm8001_ha
, 0, MSGU_ODMR
, ODMR_CLEAR_ALL
);
1115 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116 ready - 1 sec timeout */
1117 /* Wait for the SPC Configuration Table to be ready */
1118 if (check_fw_ready(pm8001_ha
) == -1) {
1119 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_1
);
1120 /* return error if MPI Configuration Table not ready */
1121 PM8001_INIT_DBG(pm8001_ha
,
1122 pm8001_printk("FW not ready SCRATCH_PAD1"
1123 " = 0x%x\n", regVal
));
1124 regVal
= pm8001_cr32(pm8001_ha
, 0, MSGU_SCRATCH_PAD_2
);
1125 /* return error if MPI Configuration Table not ready */
1126 PM8001_INIT_DBG(pm8001_ha
,
1127 pm8001_printk("FW not ready SCRATCH_PAD2"
1128 " = 0x%x\n", regVal
));
1129 PM8001_INIT_DBG(pm8001_ha
,
1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131 pm8001_cr32(pm8001_ha
, 0,
1132 MSGU_SCRATCH_PAD_0
)));
1133 PM8001_INIT_DBG(pm8001_ha
,
1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135 pm8001_cr32(pm8001_ha
, 0,
1136 MSGU_SCRATCH_PAD_3
)));
1137 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1141 pm8001_bar4_shift(pm8001_ha
, 0);
1142 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1144 PM8001_INIT_DBG(pm8001_ha
,
1145 pm8001_printk("SPC soft reset Complete\n"));
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info
*pm8001_ha
)
1153 PM8001_INIT_DBG(pm8001_ha
,
1154 pm8001_printk("chip reset start\n"));
1156 /* do SPC chip reset. */
1157 regVal
= pm8001_cr32(pm8001_ha
, 1, SPC_REG_RESET
);
1158 regVal
&= ~(SPC_REG_RESET_DEVICE
);
1159 pm8001_cw32(pm8001_ha
, 1, SPC_REG_RESET
, regVal
);
1164 /* bring chip reset out of reset */
1165 regVal
= pm8001_cr32(pm8001_ha
, 1, SPC_REG_RESET
);
1166 regVal
|= SPC_REG_RESET_DEVICE
;
1167 pm8001_cw32(pm8001_ha
, 1, SPC_REG_RESET
, regVal
);
1172 /* wait for 20 msec until the firmware gets reloaded */
1176 } while ((--i
) != 0);
1178 PM8001_INIT_DBG(pm8001_ha
,
1179 pm8001_printk("chip reset finished\n"));
1183 * pm8001_chip_iounmap - which maped when initialized.
1184 * @pm8001_ha: our hba card information
1186 void pm8001_chip_iounmap(struct pm8001_hba_info
*pm8001_ha
)
1188 s8 bar
, logical
= 0;
1189 for (bar
= 0; bar
< 6; bar
++) {
1191 ** logical BARs for SPC:
1192 ** bar 0 and 1 - logical BAR0
1193 ** bar 2 and 3 - logical BAR1
1194 ** bar4 - logical BAR2
1195 ** bar5 - logical BAR3
1196 ** Skip the appropriate assignments:
1198 if ((bar
== 1) || (bar
== 3))
1200 if (pm8001_ha
->io_mem
[logical
].memvirtaddr
) {
1201 iounmap(pm8001_ha
->io_mem
[logical
].memvirtaddr
);
1208 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209 * @pm8001_ha: our hba card information
1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info
*pm8001_ha
)
1214 pm8001_cw32(pm8001_ha
, 0, MSGU_ODMR
, ODMR_CLEAR_ALL
);
1215 pm8001_cw32(pm8001_ha
, 0, MSGU_ODCR
, ODCR_CLEAR_ALL
);
1219 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220 * @pm8001_ha: our hba card information
1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info
*pm8001_ha
)
1225 pm8001_cw32(pm8001_ha
, 0, MSGU_ODMR
, ODMR_MASK_ALL
);
1229 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230 * @pm8001_ha: our hba card information
1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info
*pm8001_ha
,
1238 msi_index
= int_vec_idx
* MSIX_TABLE_ELEMENT_SIZE
;
1239 msi_index
+= MSIX_TABLE_BASE
;
1240 pm8001_cw32(pm8001_ha
, 0, msi_index
, MSIX_INTERRUPT_ENABLE
);
1241 value
= (1 << int_vec_idx
);
1242 pm8001_cw32(pm8001_ha
, 0, MSGU_ODCR
, value
);
1247 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248 * @pm8001_ha: our hba card information
1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info
*pm8001_ha
,
1255 msi_index
= int_vec_idx
* MSIX_TABLE_ELEMENT_SIZE
;
1256 msi_index
+= MSIX_TABLE_BASE
;
1257 pm8001_cw32(pm8001_ha
, 0, msi_index
, MSIX_INTERRUPT_DISABLE
);
1261 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262 * @pm8001_ha: our hba card information
1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info
*pm8001_ha
, u8 vec
)
1267 #ifdef PM8001_USE_MSIX
1268 pm8001_chip_msix_interrupt_enable(pm8001_ha
, 0);
1271 pm8001_chip_intx_interrupt_enable(pm8001_ha
);
1276 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277 * @pm8001_ha: our hba card information
1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info
*pm8001_ha
, u8 vec
)
1282 #ifdef PM8001_USE_MSIX
1283 pm8001_chip_msix_interrupt_disable(pm8001_ha
, 0);
1286 pm8001_chip_intx_interrupt_disable(pm8001_ha
);
1291 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1293 * @circularQ: the inbound queue we want to transfer to HBA.
1294 * @messageSize: the message size of this transfer, normally it is 64 bytes
1295 * @messagePtr: the pointer to message.
1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table
*circularQ
,
1298 u16 messageSize
, void **messagePtr
)
1300 u32 offset
, consumer_index
;
1301 struct mpi_msg_hdr
*msgHeader
;
1302 u8 bcCount
= 1; /* only support single buffer */
1304 /* Checks is the requested message size can be allocated in this queue*/
1305 if (messageSize
> IOMB_SIZE_SPCV
) {
1310 /* Stores the new consumer index */
1311 consumer_index
= pm8001_read_32(circularQ
->ci_virt
);
1312 circularQ
->consumer_index
= cpu_to_le32(consumer_index
);
1313 if (((circularQ
->producer_idx
+ bcCount
) % PM8001_MPI_QUEUE
) ==
1314 le32_to_cpu(circularQ
->consumer_index
)) {
1318 /* get memory IOMB buffer address */
1319 offset
= circularQ
->producer_idx
* messageSize
;
1320 /* increment to next bcCount element */
1321 circularQ
->producer_idx
= (circularQ
->producer_idx
+ bcCount
)
1323 /* Adds that distance to the base of the region virtual address plus
1324 the message header size*/
1325 msgHeader
= (struct mpi_msg_hdr
*)(circularQ
->base_virt
+ offset
);
1326 *messagePtr
= ((void *)msgHeader
) + sizeof(struct mpi_msg_hdr
);
1331 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332 * FW to tell the fw to get this message from IOMB.
1333 * @pm8001_ha: our hba card information
1334 * @circularQ: the inbound queue we want to transfer to HBA.
1335 * @opCode: the operation code represents commands which LLDD and fw recognized.
1336 * @payload: the command payload of each operation command.
1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info
*pm8001_ha
,
1339 struct inbound_queue_table
*circularQ
,
1340 u32 opCode
, void *payload
, u32 responseQueue
)
1342 u32 Header
= 0, hpriority
= 0, bc
= 1, category
= 0x02;
1345 if (pm8001_mpi_msg_free_get(circularQ
, pm8001_ha
->iomb_size
,
1347 PM8001_IO_DBG(pm8001_ha
,
1348 pm8001_printk("No free mpi buffer\n"));
1352 /*Copy to the payload*/
1353 memcpy(pMessage
, payload
, (pm8001_ha
->iomb_size
-
1354 sizeof(struct mpi_msg_hdr
)));
1356 /*Build the header*/
1357 Header
= ((1 << 31) | (hpriority
<< 30) | ((bc
& 0x1f) << 24)
1358 | ((responseQueue
& 0x3F) << 16)
1359 | ((category
& 0xF) << 12) | (opCode
& 0xFFF));
1361 pm8001_write_32((pMessage
- 4), 0, cpu_to_le32(Header
));
1362 /*Update the PI to the firmware*/
1363 pm8001_cw32(pm8001_ha
, circularQ
->pi_pci_bar
,
1364 circularQ
->pi_offset
, circularQ
->producer_idx
);
1365 PM8001_IO_DBG(pm8001_ha
,
1366 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367 responseQueue
, opCode
, circularQ
->producer_idx
,
1368 circularQ
->consumer_index
));
1372 u32
pm8001_mpi_msg_free_set(struct pm8001_hba_info
*pm8001_ha
, void *pMsg
,
1373 struct outbound_queue_table
*circularQ
, u8 bc
)
1376 struct mpi_msg_hdr
*msgHeader
;
1377 struct mpi_msg_hdr
*pOutBoundMsgHeader
;
1379 msgHeader
= (struct mpi_msg_hdr
*)(pMsg
- sizeof(struct mpi_msg_hdr
));
1380 pOutBoundMsgHeader
= (struct mpi_msg_hdr
*)(circularQ
->base_virt
+
1381 circularQ
->consumer_idx
* pm8001_ha
->iomb_size
);
1382 if (pOutBoundMsgHeader
!= msgHeader
) {
1383 PM8001_FAIL_DBG(pm8001_ha
,
1384 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385 circularQ
->consumer_idx
, msgHeader
));
1387 /* Update the producer index from SPC */
1388 producer_index
= pm8001_read_32(circularQ
->pi_virt
);
1389 circularQ
->producer_index
= cpu_to_le32(producer_index
);
1390 PM8001_FAIL_DBG(pm8001_ha
,
1391 pm8001_printk("consumer_idx = %d producer_index = %d"
1392 "msgHeader = %p\n", circularQ
->consumer_idx
,
1393 circularQ
->producer_index
, msgHeader
));
1396 /* free the circular queue buffer elements associated with the message*/
1397 circularQ
->consumer_idx
= (circularQ
->consumer_idx
+ bc
)
1399 /* update the CI of outbound queue */
1400 pm8001_cw32(pm8001_ha
, circularQ
->ci_pci_bar
, circularQ
->ci_offset
,
1401 circularQ
->consumer_idx
);
1402 /* Update the producer index from SPC*/
1403 producer_index
= pm8001_read_32(circularQ
->pi_virt
);
1404 circularQ
->producer_index
= cpu_to_le32(producer_index
);
1405 PM8001_IO_DBG(pm8001_ha
,
1406 pm8001_printk(" CI=%d PI=%d\n", circularQ
->consumer_idx
,
1407 circularQ
->producer_index
));
1412 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1414 * @pm8001_ha: our hba card information
1415 * @circularQ: the outbound queue table.
1416 * @messagePtr1: the message contents of this outbound message.
1417 * @pBC: the message size.
1419 u32
pm8001_mpi_msg_consume(struct pm8001_hba_info
*pm8001_ha
,
1420 struct outbound_queue_table
*circularQ
,
1421 void **messagePtr1
, u8
*pBC
)
1423 struct mpi_msg_hdr
*msgHeader
;
1424 __le32 msgHeader_tmp
;
1427 /* If there are not-yet-delivered messages ... */
1428 if (le32_to_cpu(circularQ
->producer_index
)
1429 != circularQ
->consumer_idx
) {
1430 /*Get the pointer to the circular queue buffer element*/
1431 msgHeader
= (struct mpi_msg_hdr
*)
1432 (circularQ
->base_virt
+
1433 circularQ
->consumer_idx
* pm8001_ha
->iomb_size
);
1435 header_tmp
= pm8001_read_32(msgHeader
);
1436 msgHeader_tmp
= cpu_to_le32(header_tmp
);
1437 if (0 != (le32_to_cpu(msgHeader_tmp
) & 0x80000000)) {
1438 if (OPC_OUB_SKIP_ENTRY
!=
1439 (le32_to_cpu(msgHeader_tmp
) & 0xfff)) {
1442 sizeof(struct mpi_msg_hdr
);
1443 *pBC
= (u8
)((le32_to_cpu(msgHeader_tmp
)
1445 PM8001_IO_DBG(pm8001_ha
,
1446 pm8001_printk(": CI=%d PI=%d "
1448 circularQ
->consumer_idx
,
1449 circularQ
->producer_index
,
1451 return MPI_IO_STATUS_SUCCESS
;
1453 circularQ
->consumer_idx
=
1454 (circularQ
->consumer_idx
+
1455 ((le32_to_cpu(msgHeader_tmp
)
1459 pm8001_write_32(msgHeader
, 0, 0);
1460 /* update the CI of outbound queue */
1461 pm8001_cw32(pm8001_ha
,
1462 circularQ
->ci_pci_bar
,
1463 circularQ
->ci_offset
,
1464 circularQ
->consumer_idx
);
1467 circularQ
->consumer_idx
=
1468 (circularQ
->consumer_idx
+
1469 ((le32_to_cpu(msgHeader_tmp
) >> 24) &
1470 0x1f)) % PM8001_MPI_QUEUE
;
1472 pm8001_write_32(msgHeader
, 0, 0);
1473 /* update the CI of outbound queue */
1474 pm8001_cw32(pm8001_ha
, circularQ
->ci_pci_bar
,
1475 circularQ
->ci_offset
,
1476 circularQ
->consumer_idx
);
1477 return MPI_IO_STATUS_FAIL
;
1481 void *pi_virt
= circularQ
->pi_virt
;
1482 /* spurious interrupt during setup if
1483 * kexec-ing and driver doing a doorbell access
1484 * with the pre-kexec oq interrupt setup
1488 /* Update the producer index from SPC */
1489 producer_index
= pm8001_read_32(pi_virt
);
1490 circularQ
->producer_index
= cpu_to_le32(producer_index
);
1492 } while (le32_to_cpu(circularQ
->producer_index
) !=
1493 circularQ
->consumer_idx
);
1494 /* while we don't have any more not-yet-delivered message */
1496 return MPI_IO_STATUS_BUSY
;
1499 void pm8001_work_fn(struct work_struct
*work
)
1501 struct pm8001_work
*pw
= container_of(work
, struct pm8001_work
, work
);
1502 struct pm8001_device
*pm8001_dev
;
1503 struct domain_device
*dev
;
1506 * So far, all users of this stash an associated structure here.
1507 * If we get here, and this pointer is null, then the action
1508 * was cancelled. This nullification happens when the device
1511 pm8001_dev
= pw
->data
; /* Most stash device structure */
1512 if ((pm8001_dev
== NULL
)
1513 || ((pw
->handler
!= IO_XFER_ERROR_BREAK
)
1514 && (pm8001_dev
->dev_type
== SAS_PHY_UNUSED
))) {
1519 switch (pw
->handler
) {
1520 case IO_XFER_ERROR_BREAK
:
1521 { /* This one stashes the sas_task instead */
1522 struct sas_task
*t
= (struct sas_task
*)pm8001_dev
;
1524 struct pm8001_ccb_info
*ccb
;
1525 struct pm8001_hba_info
*pm8001_ha
= pw
->pm8001_ha
;
1526 unsigned long flags
, flags1
;
1527 struct task_status_struct
*ts
;
1530 if (pm8001_query_task(t
) == TMF_RESP_FUNC_SUCC
)
1531 break; /* Task still on lu */
1532 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
1534 spin_lock_irqsave(&t
->task_state_lock
, flags1
);
1535 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_DONE
))) {
1536 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1537 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1538 break; /* Task got completed by another */
1540 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1542 /* Search for a possible ccb that matches the task */
1543 for (i
= 0; ccb
= NULL
, i
< PM8001_MAX_CCB
; i
++) {
1544 ccb
= &pm8001_ha
->ccb_info
[i
];
1546 if ((tag
!= 0xFFFFFFFF) && (ccb
->task
== t
))
1550 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1551 break; /* Task got freed by another */
1553 ts
= &t
->task_status
;
1554 ts
->resp
= SAS_TASK_COMPLETE
;
1555 /* Force the midlayer to retry */
1556 ts
->stat
= SAS_QUEUE_FULL
;
1557 pm8001_dev
= ccb
->device
;
1559 pm8001_dev
->running_req
--;
1560 spin_lock_irqsave(&t
->task_state_lock
, flags1
);
1561 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
1562 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
1563 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1564 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
1565 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1566 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("task 0x%p"
1567 " done with event 0x%x resp 0x%x stat 0x%x but"
1568 " aborted by upper layer!\n",
1569 t
, pw
->handler
, ts
->resp
, ts
->stat
));
1570 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
1571 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1573 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1574 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
1575 mb();/* in order to force CPU ordering */
1576 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1580 case IO_XFER_OPEN_RETRY_TIMEOUT
:
1581 { /* This one stashes the sas_task instead */
1582 struct sas_task
*t
= (struct sas_task
*)pm8001_dev
;
1584 struct pm8001_ccb_info
*ccb
;
1585 struct pm8001_hba_info
*pm8001_ha
= pw
->pm8001_ha
;
1586 unsigned long flags
, flags1
;
1589 PM8001_IO_DBG(pm8001_ha
,
1590 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1592 ret
= pm8001_query_task(t
);
1594 PM8001_IO_DBG(pm8001_ha
,
1596 case TMF_RESP_FUNC_SUCC
:
1597 pm8001_printk("...Task on lu\n");
1600 case TMF_RESP_FUNC_COMPLETE
:
1601 pm8001_printk("...Task NOT on lu\n");
1605 pm8001_printk("...query task failed!!!\n");
1609 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
1611 spin_lock_irqsave(&t
->task_state_lock
, flags1
);
1613 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_DONE
))) {
1614 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1615 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1616 if (ret
== TMF_RESP_FUNC_SUCC
) /* task on lu */
1617 (void)pm8001_abort_task(t
);
1618 break; /* Task got completed by another */
1621 spin_unlock_irqrestore(&t
->task_state_lock
, flags1
);
1623 /* Search for a possible ccb that matches the task */
1624 for (i
= 0; ccb
= NULL
, i
< PM8001_MAX_CCB
; i
++) {
1625 ccb
= &pm8001_ha
->ccb_info
[i
];
1627 if ((tag
!= 0xFFFFFFFF) && (ccb
->task
== t
))
1631 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1632 if (ret
== TMF_RESP_FUNC_SUCC
) /* task on lu */
1633 (void)pm8001_abort_task(t
);
1634 break; /* Task got freed by another */
1637 pm8001_dev
= ccb
->device
;
1638 dev
= pm8001_dev
->sas_device
;
1641 case TMF_RESP_FUNC_SUCC
: /* task on lu */
1642 ccb
->open_retry
= 1; /* Snub completion */
1643 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1644 ret
= pm8001_abort_task(t
);
1645 ccb
->open_retry
= 0;
1647 case TMF_RESP_FUNC_SUCC
:
1648 case TMF_RESP_FUNC_COMPLETE
:
1650 default: /* device misbehavior */
1651 ret
= TMF_RESP_FUNC_FAILED
;
1652 PM8001_IO_DBG(pm8001_ha
,
1653 pm8001_printk("...Reset phy\n"));
1654 pm8001_I_T_nexus_reset(dev
);
1659 case TMF_RESP_FUNC_COMPLETE
: /* task not on lu */
1660 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1661 /* Do we need to abort the task locally? */
1664 default: /* device misbehavior */
1665 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
1666 ret
= TMF_RESP_FUNC_FAILED
;
1667 PM8001_IO_DBG(pm8001_ha
,
1668 pm8001_printk("...Reset phy\n"));
1669 pm8001_I_T_nexus_reset(dev
);
1672 if (ret
== TMF_RESP_FUNC_FAILED
)
1674 pm8001_open_reject_retry(pm8001_ha
, t
, pm8001_dev
);
1675 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("...Complete\n"));
1677 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
1678 dev
= pm8001_dev
->sas_device
;
1679 pm8001_I_T_nexus_event_handler(dev
);
1681 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
:
1682 dev
= pm8001_dev
->sas_device
;
1683 pm8001_I_T_nexus_reset(dev
);
1685 case IO_DS_IN_ERROR
:
1686 dev
= pm8001_dev
->sas_device
;
1687 pm8001_I_T_nexus_reset(dev
);
1689 case IO_DS_NON_OPERATIONAL
:
1690 dev
= pm8001_dev
->sas_device
;
1691 pm8001_I_T_nexus_reset(dev
);
1697 int pm8001_handle_event(struct pm8001_hba_info
*pm8001_ha
, void *data
,
1700 struct pm8001_work
*pw
;
1703 pw
= kmalloc(sizeof(struct pm8001_work
), GFP_ATOMIC
);
1705 pw
->pm8001_ha
= pm8001_ha
;
1707 pw
->handler
= handler
;
1708 INIT_WORK(&pw
->work
, pm8001_work_fn
);
1709 queue_work(pm8001_wq
, &pw
->work
);
1716 static void pm8001_send_abort_all(struct pm8001_hba_info
*pm8001_ha
,
1717 struct pm8001_device
*pm8001_ha_dev
)
1721 struct pm8001_ccb_info
*ccb
;
1722 struct sas_task
*task
= NULL
;
1723 struct task_abort_req task_abort
;
1724 struct inbound_queue_table
*circularQ
;
1725 u32 opc
= OPC_INB_SATA_ABORT
;
1728 if (!pm8001_ha_dev
) {
1729 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("dev is null\n"));
1733 task
= sas_alloc_slow_task(GFP_ATOMIC
);
1736 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("cannot "
1737 "allocate task\n"));
1741 task
->task_done
= pm8001_task_done
;
1743 res
= pm8001_tag_alloc(pm8001_ha
, &ccb_tag
);
1747 ccb
= &pm8001_ha
->ccb_info
[ccb_tag
];
1748 ccb
->device
= pm8001_ha_dev
;
1749 ccb
->ccb_tag
= ccb_tag
;
1752 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
1754 memset(&task_abort
, 0, sizeof(task_abort
));
1755 task_abort
.abort_all
= cpu_to_le32(1);
1756 task_abort
.device_id
= cpu_to_le32(pm8001_ha_dev
->device_id
);
1757 task_abort
.tag
= cpu_to_le32(ccb_tag
);
1759 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &task_abort
, 0);
1761 pm8001_tag_free(pm8001_ha
, ccb_tag
);
1765 static void pm8001_send_read_log(struct pm8001_hba_info
*pm8001_ha
,
1766 struct pm8001_device
*pm8001_ha_dev
)
1768 struct sata_start_req sata_cmd
;
1771 struct pm8001_ccb_info
*ccb
;
1772 struct sas_task
*task
= NULL
;
1773 struct host_to_dev_fis fis
;
1774 struct domain_device
*dev
;
1775 struct inbound_queue_table
*circularQ
;
1776 u32 opc
= OPC_INB_SATA_HOST_OPSTART
;
1778 task
= sas_alloc_slow_task(GFP_ATOMIC
);
1781 PM8001_FAIL_DBG(pm8001_ha
,
1782 pm8001_printk("cannot allocate task !!!\n"));
1785 task
->task_done
= pm8001_task_done
;
1787 res
= pm8001_tag_alloc(pm8001_ha
, &ccb_tag
);
1789 sas_free_task(task
);
1790 PM8001_FAIL_DBG(pm8001_ha
,
1791 pm8001_printk("cannot allocate tag !!!\n"));
1795 /* allocate domain device by ourselves as libsas
1796 * is not going to provide any
1798 dev
= kzalloc(sizeof(struct domain_device
), GFP_ATOMIC
);
1800 sas_free_task(task
);
1801 pm8001_tag_free(pm8001_ha
, ccb_tag
);
1802 PM8001_FAIL_DBG(pm8001_ha
,
1803 pm8001_printk("Domain device cannot be allocated\n"));
1807 task
->dev
->lldd_dev
= pm8001_ha_dev
;
1809 ccb
= &pm8001_ha
->ccb_info
[ccb_tag
];
1810 ccb
->device
= pm8001_ha_dev
;
1811 ccb
->ccb_tag
= ccb_tag
;
1813 pm8001_ha_dev
->id
|= NCQ_READ_LOG_FLAG
;
1814 pm8001_ha_dev
->id
|= NCQ_2ND_RLE_FLAG
;
1816 memset(&sata_cmd
, 0, sizeof(sata_cmd
));
1817 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
1819 /* construct read log FIS */
1820 memset(&fis
, 0, sizeof(struct host_to_dev_fis
));
1821 fis
.fis_type
= 0x27;
1823 fis
.command
= ATA_CMD_READ_LOG_EXT
;
1825 fis
.sector_count
= 0x1;
1827 sata_cmd
.tag
= cpu_to_le32(ccb_tag
);
1828 sata_cmd
.device_id
= cpu_to_le32(pm8001_ha_dev
->device_id
);
1829 sata_cmd
.ncqtag_atap_dir_m
|= ((0x1 << 7) | (0x5 << 9));
1830 memcpy(&sata_cmd
.sata_fis
, &fis
, sizeof(struct host_to_dev_fis
));
1832 res
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &sata_cmd
, 0);
1834 sas_free_task(task
);
1835 pm8001_tag_free(pm8001_ha
, ccb_tag
);
1841 * mpi_ssp_completion- process the event that FW response to the SSP request.
1842 * @pm8001_ha: our hba card information
1843 * @piomb: the message contents of this outbound message.
1845 * When FW has completed a ssp request for example a IO request, after it has
1846 * filled the SG data with the data, it will trigger this event represent
1847 * that he has finished the job,please check the coresponding buffer.
1848 * So we will tell the caller who maybe waiting the result to tell upper layer
1849 * that the task has been finished.
1852 mpi_ssp_completion(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
1855 struct pm8001_ccb_info
*ccb
;
1856 unsigned long flags
;
1860 struct ssp_completion_resp
*psspPayload
;
1861 struct task_status_struct
*ts
;
1862 struct ssp_response_iu
*iu
;
1863 struct pm8001_device
*pm8001_dev
;
1864 psspPayload
= (struct ssp_completion_resp
*)(piomb
+ 4);
1865 status
= le32_to_cpu(psspPayload
->status
);
1866 tag
= le32_to_cpu(psspPayload
->tag
);
1867 ccb
= &pm8001_ha
->ccb_info
[tag
];
1868 if ((status
== IO_ABORTED
) && ccb
->open_retry
) {
1869 /* Being completed by another */
1870 ccb
->open_retry
= 0;
1873 pm8001_dev
= ccb
->device
;
1874 param
= le32_to_cpu(psspPayload
->param
);
1878 if (status
&& status
!= IO_UNDERFLOW
)
1879 PM8001_FAIL_DBG(pm8001_ha
,
1880 pm8001_printk("sas IO status 0x%x\n", status
));
1881 if (unlikely(!t
|| !t
->lldd_task
|| !t
->dev
))
1883 ts
= &t
->task_status
;
1884 /* Print sas address of IO failed device */
1885 if ((status
!= IO_SUCCESS
) && (status
!= IO_OVERFLOW
) &&
1886 (status
!= IO_UNDERFLOW
))
1887 PM8001_FAIL_DBG(pm8001_ha
,
1888 pm8001_printk("SAS Address of IO Failure Drive:"
1889 "%016llx", SAS_ADDR(t
->dev
->sas_addr
)));
1893 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_SUCCESS"
1894 ",param = %d\n", param
));
1896 ts
->resp
= SAS_TASK_COMPLETE
;
1897 ts
->stat
= SAM_STAT_GOOD
;
1899 ts
->resp
= SAS_TASK_COMPLETE
;
1900 ts
->stat
= SAS_PROTO_RESPONSE
;
1901 ts
->residual
= param
;
1902 iu
= &psspPayload
->ssp_resp_iu
;
1903 sas_ssp_task_response(pm8001_ha
->dev
, t
, iu
);
1906 pm8001_dev
->running_req
--;
1909 PM8001_IO_DBG(pm8001_ha
,
1910 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1911 ts
->resp
= SAS_TASK_COMPLETE
;
1912 ts
->stat
= SAS_ABORTED_TASK
;
1915 /* SSP Completion with error */
1916 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_UNDERFLOW"
1917 ",param = %d\n", param
));
1918 ts
->resp
= SAS_TASK_COMPLETE
;
1919 ts
->stat
= SAS_DATA_UNDERRUN
;
1920 ts
->residual
= param
;
1922 pm8001_dev
->running_req
--;
1925 PM8001_IO_DBG(pm8001_ha
,
1926 pm8001_printk("IO_NO_DEVICE\n"));
1927 ts
->resp
= SAS_TASK_UNDELIVERED
;
1928 ts
->stat
= SAS_PHY_DOWN
;
1930 case IO_XFER_ERROR_BREAK
:
1931 PM8001_IO_DBG(pm8001_ha
,
1932 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1933 ts
->resp
= SAS_TASK_COMPLETE
;
1934 ts
->stat
= SAS_OPEN_REJECT
;
1935 /* Force the midlayer to retry */
1936 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1938 case IO_XFER_ERROR_PHY_NOT_READY
:
1939 PM8001_IO_DBG(pm8001_ha
,
1940 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1941 ts
->resp
= SAS_TASK_COMPLETE
;
1942 ts
->stat
= SAS_OPEN_REJECT
;
1943 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1945 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
:
1946 PM8001_IO_DBG(pm8001_ha
,
1947 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1948 ts
->resp
= SAS_TASK_COMPLETE
;
1949 ts
->stat
= SAS_OPEN_REJECT
;
1950 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
1952 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION
:
1953 PM8001_IO_DBG(pm8001_ha
,
1954 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1955 ts
->resp
= SAS_TASK_COMPLETE
;
1956 ts
->stat
= SAS_OPEN_REJECT
;
1957 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1959 case IO_OPEN_CNX_ERROR_BREAK
:
1960 PM8001_IO_DBG(pm8001_ha
,
1961 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1962 ts
->resp
= SAS_TASK_COMPLETE
;
1963 ts
->stat
= SAS_OPEN_REJECT
;
1964 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1966 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
1967 PM8001_IO_DBG(pm8001_ha
,
1968 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1969 ts
->resp
= SAS_TASK_COMPLETE
;
1970 ts
->stat
= SAS_OPEN_REJECT
;
1971 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1973 pm8001_handle_event(pm8001_ha
,
1975 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
1977 case IO_OPEN_CNX_ERROR_BAD_DESTINATION
:
1978 PM8001_IO_DBG(pm8001_ha
,
1979 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1980 ts
->resp
= SAS_TASK_COMPLETE
;
1981 ts
->stat
= SAS_OPEN_REJECT
;
1982 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
1984 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
:
1985 PM8001_IO_DBG(pm8001_ha
,
1986 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1987 "NOT_SUPPORTED\n"));
1988 ts
->resp
= SAS_TASK_COMPLETE
;
1989 ts
->stat
= SAS_OPEN_REJECT
;
1990 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
1992 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION
:
1993 PM8001_IO_DBG(pm8001_ha
,
1994 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1995 ts
->resp
= SAS_TASK_UNDELIVERED
;
1996 ts
->stat
= SAS_OPEN_REJECT
;
1997 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
1999 case IO_XFER_ERROR_NAK_RECEIVED
:
2000 PM8001_IO_DBG(pm8001_ha
,
2001 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2002 ts
->resp
= SAS_TASK_COMPLETE
;
2003 ts
->stat
= SAS_OPEN_REJECT
;
2004 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2006 case IO_XFER_ERROR_ACK_NAK_TIMEOUT
:
2007 PM8001_IO_DBG(pm8001_ha
,
2008 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2009 ts
->resp
= SAS_TASK_COMPLETE
;
2010 ts
->stat
= SAS_NAK_R_ERR
;
2012 case IO_XFER_ERROR_DMA
:
2013 PM8001_IO_DBG(pm8001_ha
,
2014 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2015 ts
->resp
= SAS_TASK_COMPLETE
;
2016 ts
->stat
= SAS_OPEN_REJECT
;
2018 case IO_XFER_OPEN_RETRY_TIMEOUT
:
2019 PM8001_IO_DBG(pm8001_ha
,
2020 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2021 ts
->resp
= SAS_TASK_COMPLETE
;
2022 ts
->stat
= SAS_OPEN_REJECT
;
2023 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2025 case IO_XFER_ERROR_OFFSET_MISMATCH
:
2026 PM8001_IO_DBG(pm8001_ha
,
2027 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2028 ts
->resp
= SAS_TASK_COMPLETE
;
2029 ts
->stat
= SAS_OPEN_REJECT
;
2031 case IO_PORT_IN_RESET
:
2032 PM8001_IO_DBG(pm8001_ha
,
2033 pm8001_printk("IO_PORT_IN_RESET\n"));
2034 ts
->resp
= SAS_TASK_COMPLETE
;
2035 ts
->stat
= SAS_OPEN_REJECT
;
2037 case IO_DS_NON_OPERATIONAL
:
2038 PM8001_IO_DBG(pm8001_ha
,
2039 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2040 ts
->resp
= SAS_TASK_COMPLETE
;
2041 ts
->stat
= SAS_OPEN_REJECT
;
2043 pm8001_handle_event(pm8001_ha
,
2045 IO_DS_NON_OPERATIONAL
);
2047 case IO_DS_IN_RECOVERY
:
2048 PM8001_IO_DBG(pm8001_ha
,
2049 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2050 ts
->resp
= SAS_TASK_COMPLETE
;
2051 ts
->stat
= SAS_OPEN_REJECT
;
2053 case IO_TM_TAG_NOT_FOUND
:
2054 PM8001_IO_DBG(pm8001_ha
,
2055 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2056 ts
->resp
= SAS_TASK_COMPLETE
;
2057 ts
->stat
= SAS_OPEN_REJECT
;
2059 case IO_SSP_EXT_IU_ZERO_LEN_ERROR
:
2060 PM8001_IO_DBG(pm8001_ha
,
2061 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2062 ts
->resp
= SAS_TASK_COMPLETE
;
2063 ts
->stat
= SAS_OPEN_REJECT
;
2065 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
:
2066 PM8001_IO_DBG(pm8001_ha
,
2067 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2068 ts
->resp
= SAS_TASK_COMPLETE
;
2069 ts
->stat
= SAS_OPEN_REJECT
;
2070 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2073 PM8001_IO_DBG(pm8001_ha
,
2074 pm8001_printk("Unknown status 0x%x\n", status
));
2075 /* not allowed case. Therefore, return failed status */
2076 ts
->resp
= SAS_TASK_COMPLETE
;
2077 ts
->stat
= SAS_OPEN_REJECT
;
2080 PM8001_IO_DBG(pm8001_ha
,
2081 pm8001_printk("scsi_status = %x\n ",
2082 psspPayload
->ssp_resp_iu
.status
));
2083 spin_lock_irqsave(&t
->task_state_lock
, flags
);
2084 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
2085 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
2086 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2087 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
2088 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2089 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("task 0x%p done with"
2090 " io_status 0x%x resp 0x%x "
2091 "stat 0x%x but aborted by upper layer!\n",
2092 t
, status
, ts
->resp
, ts
->stat
));
2093 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2095 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2096 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2097 mb();/* in order to force CPU ordering */
2102 /*See the comments for mpi_ssp_completion */
2103 static void mpi_ssp_event(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
2106 unsigned long flags
;
2107 struct task_status_struct
*ts
;
2108 struct pm8001_ccb_info
*ccb
;
2109 struct pm8001_device
*pm8001_dev
;
2110 struct ssp_event_resp
*psspPayload
=
2111 (struct ssp_event_resp
*)(piomb
+ 4);
2112 u32 event
= le32_to_cpu(psspPayload
->event
);
2113 u32 tag
= le32_to_cpu(psspPayload
->tag
);
2114 u32 port_id
= le32_to_cpu(psspPayload
->port_id
);
2115 u32 dev_id
= le32_to_cpu(psspPayload
->device_id
);
2117 ccb
= &pm8001_ha
->ccb_info
[tag
];
2119 pm8001_dev
= ccb
->device
;
2121 PM8001_FAIL_DBG(pm8001_ha
,
2122 pm8001_printk("sas IO status 0x%x\n", event
));
2123 if (unlikely(!t
|| !t
->lldd_task
|| !t
->dev
))
2125 ts
= &t
->task_status
;
2126 PM8001_IO_DBG(pm8001_ha
,
2127 pm8001_printk("port_id = %x,device_id = %x\n",
2131 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_UNDERFLOW\n");)
2132 ts
->resp
= SAS_TASK_COMPLETE
;
2133 ts
->stat
= SAS_DATA_OVERRUN
;
2136 pm8001_dev
->running_req
--;
2138 case IO_XFER_ERROR_BREAK
:
2139 PM8001_IO_DBG(pm8001_ha
,
2140 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2141 pm8001_handle_event(pm8001_ha
, t
, IO_XFER_ERROR_BREAK
);
2143 case IO_XFER_ERROR_PHY_NOT_READY
:
2144 PM8001_IO_DBG(pm8001_ha
,
2145 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2146 ts
->resp
= SAS_TASK_COMPLETE
;
2147 ts
->stat
= SAS_OPEN_REJECT
;
2148 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2150 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
:
2151 PM8001_IO_DBG(pm8001_ha
,
2152 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2154 ts
->resp
= SAS_TASK_COMPLETE
;
2155 ts
->stat
= SAS_OPEN_REJECT
;
2156 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2158 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION
:
2159 PM8001_IO_DBG(pm8001_ha
,
2160 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2161 ts
->resp
= SAS_TASK_COMPLETE
;
2162 ts
->stat
= SAS_OPEN_REJECT
;
2163 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2165 case IO_OPEN_CNX_ERROR_BREAK
:
2166 PM8001_IO_DBG(pm8001_ha
,
2167 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2168 ts
->resp
= SAS_TASK_COMPLETE
;
2169 ts
->stat
= SAS_OPEN_REJECT
;
2170 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2172 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
2173 PM8001_IO_DBG(pm8001_ha
,
2174 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2175 ts
->resp
= SAS_TASK_COMPLETE
;
2176 ts
->stat
= SAS_OPEN_REJECT
;
2177 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2179 pm8001_handle_event(pm8001_ha
,
2181 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
2183 case IO_OPEN_CNX_ERROR_BAD_DESTINATION
:
2184 PM8001_IO_DBG(pm8001_ha
,
2185 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2186 ts
->resp
= SAS_TASK_COMPLETE
;
2187 ts
->stat
= SAS_OPEN_REJECT
;
2188 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2190 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
:
2191 PM8001_IO_DBG(pm8001_ha
,
2192 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2193 "NOT_SUPPORTED\n"));
2194 ts
->resp
= SAS_TASK_COMPLETE
;
2195 ts
->stat
= SAS_OPEN_REJECT
;
2196 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2198 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION
:
2199 PM8001_IO_DBG(pm8001_ha
,
2200 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2201 ts
->resp
= SAS_TASK_COMPLETE
;
2202 ts
->stat
= SAS_OPEN_REJECT
;
2203 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2205 case IO_XFER_ERROR_NAK_RECEIVED
:
2206 PM8001_IO_DBG(pm8001_ha
,
2207 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2208 ts
->resp
= SAS_TASK_COMPLETE
;
2209 ts
->stat
= SAS_OPEN_REJECT
;
2210 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2212 case IO_XFER_ERROR_ACK_NAK_TIMEOUT
:
2213 PM8001_IO_DBG(pm8001_ha
,
2214 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2215 ts
->resp
= SAS_TASK_COMPLETE
;
2216 ts
->stat
= SAS_NAK_R_ERR
;
2218 case IO_XFER_OPEN_RETRY_TIMEOUT
:
2219 PM8001_IO_DBG(pm8001_ha
,
2220 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2221 pm8001_handle_event(pm8001_ha
, t
, IO_XFER_OPEN_RETRY_TIMEOUT
);
2223 case IO_XFER_ERROR_UNEXPECTED_PHASE
:
2224 PM8001_IO_DBG(pm8001_ha
,
2225 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2226 ts
->resp
= SAS_TASK_COMPLETE
;
2227 ts
->stat
= SAS_DATA_OVERRUN
;
2229 case IO_XFER_ERROR_XFER_RDY_OVERRUN
:
2230 PM8001_IO_DBG(pm8001_ha
,
2231 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2232 ts
->resp
= SAS_TASK_COMPLETE
;
2233 ts
->stat
= SAS_DATA_OVERRUN
;
2235 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED
:
2236 PM8001_IO_DBG(pm8001_ha
,
2237 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2238 ts
->resp
= SAS_TASK_COMPLETE
;
2239 ts
->stat
= SAS_DATA_OVERRUN
;
2241 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT
:
2242 PM8001_IO_DBG(pm8001_ha
,
2243 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2244 ts
->resp
= SAS_TASK_COMPLETE
;
2245 ts
->stat
= SAS_DATA_OVERRUN
;
2247 case IO_XFER_ERROR_OFFSET_MISMATCH
:
2248 PM8001_IO_DBG(pm8001_ha
,
2249 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2250 ts
->resp
= SAS_TASK_COMPLETE
;
2251 ts
->stat
= SAS_DATA_OVERRUN
;
2253 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN
:
2254 PM8001_IO_DBG(pm8001_ha
,
2255 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2256 ts
->resp
= SAS_TASK_COMPLETE
;
2257 ts
->stat
= SAS_DATA_OVERRUN
;
2259 case IO_XFER_CMD_FRAME_ISSUED
:
2260 PM8001_IO_DBG(pm8001_ha
,
2261 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
2264 PM8001_IO_DBG(pm8001_ha
,
2265 pm8001_printk("Unknown status 0x%x\n", event
));
2266 /* not allowed case. Therefore, return failed status */
2267 ts
->resp
= SAS_TASK_COMPLETE
;
2268 ts
->stat
= SAS_DATA_OVERRUN
;
2271 spin_lock_irqsave(&t
->task_state_lock
, flags
);
2272 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
2273 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
2274 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2275 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
2276 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2277 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("task 0x%p done with"
2278 " event 0x%x resp 0x%x "
2279 "stat 0x%x but aborted by upper layer!\n",
2280 t
, event
, ts
->resp
, ts
->stat
));
2281 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2283 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2284 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2285 mb();/* in order to force CPU ordering */
2290 /*See the comments for mpi_ssp_completion */
2292 mpi_sata_completion(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
2295 struct pm8001_ccb_info
*ccb
;
2300 u8 sata_addr_low
[4];
2301 u32 temp_sata_addr_low
;
2303 u32 temp_sata_addr_hi
;
2304 struct sata_completion_resp
*psataPayload
;
2305 struct task_status_struct
*ts
;
2306 struct ata_task_resp
*resp
;
2308 struct pm8001_device
*pm8001_dev
;
2309 unsigned long flags
;
2311 psataPayload
= (struct sata_completion_resp
*)(piomb
+ 4);
2312 status
= le32_to_cpu(psataPayload
->status
);
2313 tag
= le32_to_cpu(psataPayload
->tag
);
2316 PM8001_FAIL_DBG(pm8001_ha
,
2317 pm8001_printk("tag null\n"));
2320 ccb
= &pm8001_ha
->ccb_info
[tag
];
2321 param
= le32_to_cpu(psataPayload
->param
);
2324 pm8001_dev
= ccb
->device
;
2326 PM8001_FAIL_DBG(pm8001_ha
,
2327 pm8001_printk("ccb null\n"));
2332 if (t
->dev
&& (t
->dev
->lldd_dev
))
2333 pm8001_dev
= t
->dev
->lldd_dev
;
2335 PM8001_FAIL_DBG(pm8001_ha
,
2336 pm8001_printk("task null\n"));
2340 if ((pm8001_dev
&& !(pm8001_dev
->id
& NCQ_READ_LOG_FLAG
))
2341 && unlikely(!t
|| !t
->lldd_task
|| !t
->dev
)) {
2342 PM8001_FAIL_DBG(pm8001_ha
,
2343 pm8001_printk("task or dev null\n"));
2347 ts
= &t
->task_status
;
2349 PM8001_FAIL_DBG(pm8001_ha
,
2350 pm8001_printk("ts null\n"));
2353 /* Print sas address of IO failed device */
2354 if ((status
!= IO_SUCCESS
) && (status
!= IO_OVERFLOW
) &&
2355 (status
!= IO_UNDERFLOW
)) {
2356 if (!((t
->dev
->parent
) &&
2357 (DEV_IS_EXPANDER(t
->dev
->parent
->dev_type
)))) {
2358 for (i
= 0 , j
= 4; j
<= 7 && i
<= 3; i
++ , j
++)
2359 sata_addr_low
[i
] = pm8001_ha
->sas_addr
[j
];
2360 for (i
= 0 , j
= 0; j
<= 3 && i
<= 3; i
++ , j
++)
2361 sata_addr_hi
[i
] = pm8001_ha
->sas_addr
[j
];
2362 memcpy(&temp_sata_addr_low
, sata_addr_low
,
2363 sizeof(sata_addr_low
));
2364 memcpy(&temp_sata_addr_hi
, sata_addr_hi
,
2365 sizeof(sata_addr_hi
));
2366 temp_sata_addr_hi
= (((temp_sata_addr_hi
>> 24) & 0xff)
2367 |((temp_sata_addr_hi
<< 8) &
2369 ((temp_sata_addr_hi
>> 8)
2371 ((temp_sata_addr_hi
<< 24) &
2373 temp_sata_addr_low
= ((((temp_sata_addr_low
>> 24)
2375 ((temp_sata_addr_low
<< 8)
2377 ((temp_sata_addr_low
>> 8)
2379 ((temp_sata_addr_low
<< 24)
2381 pm8001_dev
->attached_phy
+
2383 PM8001_FAIL_DBG(pm8001_ha
,
2384 pm8001_printk("SAS Address of IO Failure Drive:"
2385 "%08x%08x", temp_sata_addr_hi
,
2386 temp_sata_addr_low
));
2388 PM8001_FAIL_DBG(pm8001_ha
,
2389 pm8001_printk("SAS Address of IO Failure Drive:"
2390 "%016llx", SAS_ADDR(t
->dev
->sas_addr
)));
2395 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_SUCCESS\n"));
2397 ts
->resp
= SAS_TASK_COMPLETE
;
2398 ts
->stat
= SAM_STAT_GOOD
;
2399 /* check if response is for SEND READ LOG */
2401 (pm8001_dev
->id
& NCQ_READ_LOG_FLAG
)) {
2402 /* set new bit for abort_all */
2403 pm8001_dev
->id
|= NCQ_ABORT_ALL_FLAG
;
2404 /* clear bit for read log */
2405 pm8001_dev
->id
= pm8001_dev
->id
& 0x7FFFFFFF;
2406 pm8001_send_abort_all(pm8001_ha
, pm8001_dev
);
2408 pm8001_tag_free(pm8001_ha
, tag
);
2414 ts
->resp
= SAS_TASK_COMPLETE
;
2415 ts
->stat
= SAS_PROTO_RESPONSE
;
2416 ts
->residual
= param
;
2417 PM8001_IO_DBG(pm8001_ha
,
2418 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2420 sata_resp
= &psataPayload
->sata_resp
[0];
2421 resp
= (struct ata_task_resp
*)ts
->buf
;
2422 if (t
->ata_task
.dma_xfer
== 0 &&
2423 t
->data_dir
== PCI_DMA_FROMDEVICE
) {
2424 len
= sizeof(struct pio_setup_fis
);
2425 PM8001_IO_DBG(pm8001_ha
,
2426 pm8001_printk("PIO read len = %d\n", len
));
2427 } else if (t
->ata_task
.use_ncq
) {
2428 len
= sizeof(struct set_dev_bits_fis
);
2429 PM8001_IO_DBG(pm8001_ha
,
2430 pm8001_printk("FPDMA len = %d\n", len
));
2432 len
= sizeof(struct dev_to_host_fis
);
2433 PM8001_IO_DBG(pm8001_ha
,
2434 pm8001_printk("other len = %d\n", len
));
2436 if (SAS_STATUS_BUF_SIZE
>= sizeof(*resp
)) {
2437 resp
->frame_len
= len
;
2438 memcpy(&resp
->ending_fis
[0], sata_resp
, len
);
2439 ts
->buf_valid_size
= sizeof(*resp
);
2441 PM8001_IO_DBG(pm8001_ha
,
2442 pm8001_printk("response to large\n"));
2445 pm8001_dev
->running_req
--;
2448 PM8001_IO_DBG(pm8001_ha
,
2449 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2450 ts
->resp
= SAS_TASK_COMPLETE
;
2451 ts
->stat
= SAS_ABORTED_TASK
;
2453 pm8001_dev
->running_req
--;
2455 /* following cases are to do cases */
2457 /* SATA Completion with error */
2458 PM8001_IO_DBG(pm8001_ha
,
2459 pm8001_printk("IO_UNDERFLOW param = %d\n", param
));
2460 ts
->resp
= SAS_TASK_COMPLETE
;
2461 ts
->stat
= SAS_DATA_UNDERRUN
;
2462 ts
->residual
= param
;
2464 pm8001_dev
->running_req
--;
2467 PM8001_IO_DBG(pm8001_ha
,
2468 pm8001_printk("IO_NO_DEVICE\n"));
2469 ts
->resp
= SAS_TASK_UNDELIVERED
;
2470 ts
->stat
= SAS_PHY_DOWN
;
2472 case IO_XFER_ERROR_BREAK
:
2473 PM8001_IO_DBG(pm8001_ha
,
2474 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2475 ts
->resp
= SAS_TASK_COMPLETE
;
2476 ts
->stat
= SAS_INTERRUPTED
;
2478 case IO_XFER_ERROR_PHY_NOT_READY
:
2479 PM8001_IO_DBG(pm8001_ha
,
2480 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2481 ts
->resp
= SAS_TASK_COMPLETE
;
2482 ts
->stat
= SAS_OPEN_REJECT
;
2483 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2485 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
:
2486 PM8001_IO_DBG(pm8001_ha
,
2487 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2489 ts
->resp
= SAS_TASK_COMPLETE
;
2490 ts
->stat
= SAS_OPEN_REJECT
;
2491 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2493 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION
:
2494 PM8001_IO_DBG(pm8001_ha
,
2495 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2496 ts
->resp
= SAS_TASK_COMPLETE
;
2497 ts
->stat
= SAS_OPEN_REJECT
;
2498 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2500 case IO_OPEN_CNX_ERROR_BREAK
:
2501 PM8001_IO_DBG(pm8001_ha
,
2502 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2503 ts
->resp
= SAS_TASK_COMPLETE
;
2504 ts
->stat
= SAS_OPEN_REJECT
;
2505 ts
->open_rej_reason
= SAS_OREJ_RSVD_CONT0
;
2507 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
2508 PM8001_IO_DBG(pm8001_ha
,
2509 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2510 ts
->resp
= SAS_TASK_COMPLETE
;
2511 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2512 if (!t
->uldd_task
) {
2513 pm8001_handle_event(pm8001_ha
,
2515 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
2516 ts
->resp
= SAS_TASK_UNDELIVERED
;
2517 ts
->stat
= SAS_QUEUE_FULL
;
2518 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2522 case IO_OPEN_CNX_ERROR_BAD_DESTINATION
:
2523 PM8001_IO_DBG(pm8001_ha
,
2524 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2525 ts
->resp
= SAS_TASK_UNDELIVERED
;
2526 ts
->stat
= SAS_OPEN_REJECT
;
2527 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2528 if (!t
->uldd_task
) {
2529 pm8001_handle_event(pm8001_ha
,
2531 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
2532 ts
->resp
= SAS_TASK_UNDELIVERED
;
2533 ts
->stat
= SAS_QUEUE_FULL
;
2534 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2538 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
:
2539 PM8001_IO_DBG(pm8001_ha
,
2540 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2541 "NOT_SUPPORTED\n"));
2542 ts
->resp
= SAS_TASK_COMPLETE
;
2543 ts
->stat
= SAS_OPEN_REJECT
;
2544 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2546 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
:
2547 PM8001_IO_DBG(pm8001_ha
,
2548 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2550 ts
->resp
= SAS_TASK_COMPLETE
;
2551 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2552 if (!t
->uldd_task
) {
2553 pm8001_handle_event(pm8001_ha
,
2555 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
);
2556 ts
->resp
= SAS_TASK_UNDELIVERED
;
2557 ts
->stat
= SAS_QUEUE_FULL
;
2558 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2562 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION
:
2563 PM8001_IO_DBG(pm8001_ha
,
2564 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2565 ts
->resp
= SAS_TASK_COMPLETE
;
2566 ts
->stat
= SAS_OPEN_REJECT
;
2567 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2569 case IO_XFER_ERROR_NAK_RECEIVED
:
2570 PM8001_IO_DBG(pm8001_ha
,
2571 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2572 ts
->resp
= SAS_TASK_COMPLETE
;
2573 ts
->stat
= SAS_NAK_R_ERR
;
2575 case IO_XFER_ERROR_ACK_NAK_TIMEOUT
:
2576 PM8001_IO_DBG(pm8001_ha
,
2577 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2578 ts
->resp
= SAS_TASK_COMPLETE
;
2579 ts
->stat
= SAS_NAK_R_ERR
;
2581 case IO_XFER_ERROR_DMA
:
2582 PM8001_IO_DBG(pm8001_ha
,
2583 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2584 ts
->resp
= SAS_TASK_COMPLETE
;
2585 ts
->stat
= SAS_ABORTED_TASK
;
2587 case IO_XFER_ERROR_SATA_LINK_TIMEOUT
:
2588 PM8001_IO_DBG(pm8001_ha
,
2589 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2590 ts
->resp
= SAS_TASK_UNDELIVERED
;
2591 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2593 case IO_XFER_ERROR_REJECTED_NCQ_MODE
:
2594 PM8001_IO_DBG(pm8001_ha
,
2595 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2596 ts
->resp
= SAS_TASK_COMPLETE
;
2597 ts
->stat
= SAS_DATA_UNDERRUN
;
2599 case IO_XFER_OPEN_RETRY_TIMEOUT
:
2600 PM8001_IO_DBG(pm8001_ha
,
2601 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2602 ts
->resp
= SAS_TASK_COMPLETE
;
2603 ts
->stat
= SAS_OPEN_TO
;
2605 case IO_PORT_IN_RESET
:
2606 PM8001_IO_DBG(pm8001_ha
,
2607 pm8001_printk("IO_PORT_IN_RESET\n"));
2608 ts
->resp
= SAS_TASK_COMPLETE
;
2609 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2611 case IO_DS_NON_OPERATIONAL
:
2612 PM8001_IO_DBG(pm8001_ha
,
2613 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2614 ts
->resp
= SAS_TASK_COMPLETE
;
2615 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2616 if (!t
->uldd_task
) {
2617 pm8001_handle_event(pm8001_ha
, pm8001_dev
,
2618 IO_DS_NON_OPERATIONAL
);
2619 ts
->resp
= SAS_TASK_UNDELIVERED
;
2620 ts
->stat
= SAS_QUEUE_FULL
;
2621 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2625 case IO_DS_IN_RECOVERY
:
2626 PM8001_IO_DBG(pm8001_ha
,
2627 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2628 ts
->resp
= SAS_TASK_COMPLETE
;
2629 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2631 case IO_DS_IN_ERROR
:
2632 PM8001_IO_DBG(pm8001_ha
,
2633 pm8001_printk("IO_DS_IN_ERROR\n"));
2634 ts
->resp
= SAS_TASK_COMPLETE
;
2635 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2636 if (!t
->uldd_task
) {
2637 pm8001_handle_event(pm8001_ha
, pm8001_dev
,
2639 ts
->resp
= SAS_TASK_UNDELIVERED
;
2640 ts
->stat
= SAS_QUEUE_FULL
;
2641 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2645 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
:
2646 PM8001_IO_DBG(pm8001_ha
,
2647 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2648 ts
->resp
= SAS_TASK_COMPLETE
;
2649 ts
->stat
= SAS_OPEN_REJECT
;
2650 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2653 PM8001_IO_DBG(pm8001_ha
,
2654 pm8001_printk("Unknown status 0x%x\n", status
));
2655 /* not allowed case. Therefore, return failed status */
2656 ts
->resp
= SAS_TASK_COMPLETE
;
2657 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2660 spin_lock_irqsave(&t
->task_state_lock
, flags
);
2661 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
2662 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
2663 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2664 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
2665 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2666 PM8001_FAIL_DBG(pm8001_ha
,
2667 pm8001_printk("task 0x%p done with io_status 0x%x"
2668 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2669 t
, status
, ts
->resp
, ts
->stat
));
2670 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2672 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2673 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2677 /*See the comments for mpi_ssp_completion */
2678 static void mpi_sata_event(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
2681 struct task_status_struct
*ts
;
2682 struct pm8001_ccb_info
*ccb
;
2683 struct pm8001_device
*pm8001_dev
;
2684 struct sata_event_resp
*psataPayload
=
2685 (struct sata_event_resp
*)(piomb
+ 4);
2686 u32 event
= le32_to_cpu(psataPayload
->event
);
2687 u32 tag
= le32_to_cpu(psataPayload
->tag
);
2688 u32 port_id
= le32_to_cpu(psataPayload
->port_id
);
2689 u32 dev_id
= le32_to_cpu(psataPayload
->device_id
);
2690 unsigned long flags
;
2692 ccb
= &pm8001_ha
->ccb_info
[tag
];
2696 pm8001_dev
= ccb
->device
;
2698 PM8001_FAIL_DBG(pm8001_ha
,
2699 pm8001_printk("No CCB !!!. returning\n"));
2702 PM8001_FAIL_DBG(pm8001_ha
,
2703 pm8001_printk("SATA EVENT 0x%x\n", event
));
2705 /* Check if this is NCQ error */
2706 if (event
== IO_XFER_ERROR_ABORTED_NCQ_MODE
) {
2707 /* find device using device id */
2708 pm8001_dev
= pm8001_find_dev(pm8001_ha
, dev_id
);
2709 /* send read log extension */
2711 pm8001_send_read_log(pm8001_ha
, pm8001_dev
);
2715 ccb
= &pm8001_ha
->ccb_info
[tag
];
2717 pm8001_dev
= ccb
->device
;
2719 PM8001_FAIL_DBG(pm8001_ha
,
2720 pm8001_printk("sata IO status 0x%x\n", event
));
2721 if (unlikely(!t
|| !t
->lldd_task
|| !t
->dev
))
2723 ts
= &t
->task_status
;
2724 PM8001_IO_DBG(pm8001_ha
, pm8001_printk(
2725 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2726 port_id
, dev_id
, tag
, event
));
2729 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_UNDERFLOW\n"));
2730 ts
->resp
= SAS_TASK_COMPLETE
;
2731 ts
->stat
= SAS_DATA_OVERRUN
;
2734 pm8001_dev
->running_req
--;
2736 case IO_XFER_ERROR_BREAK
:
2737 PM8001_IO_DBG(pm8001_ha
,
2738 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2739 ts
->resp
= SAS_TASK_COMPLETE
;
2740 ts
->stat
= SAS_INTERRUPTED
;
2742 case IO_XFER_ERROR_PHY_NOT_READY
:
2743 PM8001_IO_DBG(pm8001_ha
,
2744 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2745 ts
->resp
= SAS_TASK_COMPLETE
;
2746 ts
->stat
= SAS_OPEN_REJECT
;
2747 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
2749 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
:
2750 PM8001_IO_DBG(pm8001_ha
,
2751 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2753 ts
->resp
= SAS_TASK_COMPLETE
;
2754 ts
->stat
= SAS_OPEN_REJECT
;
2755 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2757 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION
:
2758 PM8001_IO_DBG(pm8001_ha
,
2759 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2760 ts
->resp
= SAS_TASK_COMPLETE
;
2761 ts
->stat
= SAS_OPEN_REJECT
;
2762 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2764 case IO_OPEN_CNX_ERROR_BREAK
:
2765 PM8001_IO_DBG(pm8001_ha
,
2766 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2767 ts
->resp
= SAS_TASK_COMPLETE
;
2768 ts
->stat
= SAS_OPEN_REJECT
;
2769 ts
->open_rej_reason
= SAS_OREJ_RSVD_CONT0
;
2771 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
2772 PM8001_IO_DBG(pm8001_ha
,
2773 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2774 ts
->resp
= SAS_TASK_UNDELIVERED
;
2775 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2776 if (!t
->uldd_task
) {
2777 pm8001_handle_event(pm8001_ha
,
2779 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
2780 ts
->resp
= SAS_TASK_COMPLETE
;
2781 ts
->stat
= SAS_QUEUE_FULL
;
2782 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2786 case IO_OPEN_CNX_ERROR_BAD_DESTINATION
:
2787 PM8001_IO_DBG(pm8001_ha
,
2788 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2789 ts
->resp
= SAS_TASK_UNDELIVERED
;
2790 ts
->stat
= SAS_OPEN_REJECT
;
2791 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2793 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
:
2794 PM8001_IO_DBG(pm8001_ha
,
2795 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2796 "NOT_SUPPORTED\n"));
2797 ts
->resp
= SAS_TASK_COMPLETE
;
2798 ts
->stat
= SAS_OPEN_REJECT
;
2799 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2801 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION
:
2802 PM8001_IO_DBG(pm8001_ha
,
2803 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2804 ts
->resp
= SAS_TASK_COMPLETE
;
2805 ts
->stat
= SAS_OPEN_REJECT
;
2806 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2808 case IO_XFER_ERROR_NAK_RECEIVED
:
2809 PM8001_IO_DBG(pm8001_ha
,
2810 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2811 ts
->resp
= SAS_TASK_COMPLETE
;
2812 ts
->stat
= SAS_NAK_R_ERR
;
2814 case IO_XFER_ERROR_PEER_ABORTED
:
2815 PM8001_IO_DBG(pm8001_ha
,
2816 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2817 ts
->resp
= SAS_TASK_COMPLETE
;
2818 ts
->stat
= SAS_NAK_R_ERR
;
2820 case IO_XFER_ERROR_REJECTED_NCQ_MODE
:
2821 PM8001_IO_DBG(pm8001_ha
,
2822 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2823 ts
->resp
= SAS_TASK_COMPLETE
;
2824 ts
->stat
= SAS_DATA_UNDERRUN
;
2826 case IO_XFER_OPEN_RETRY_TIMEOUT
:
2827 PM8001_IO_DBG(pm8001_ha
,
2828 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2829 ts
->resp
= SAS_TASK_COMPLETE
;
2830 ts
->stat
= SAS_OPEN_TO
;
2832 case IO_XFER_ERROR_UNEXPECTED_PHASE
:
2833 PM8001_IO_DBG(pm8001_ha
,
2834 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2835 ts
->resp
= SAS_TASK_COMPLETE
;
2836 ts
->stat
= SAS_OPEN_TO
;
2838 case IO_XFER_ERROR_XFER_RDY_OVERRUN
:
2839 PM8001_IO_DBG(pm8001_ha
,
2840 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2841 ts
->resp
= SAS_TASK_COMPLETE
;
2842 ts
->stat
= SAS_OPEN_TO
;
2844 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED
:
2845 PM8001_IO_DBG(pm8001_ha
,
2846 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2847 ts
->resp
= SAS_TASK_COMPLETE
;
2848 ts
->stat
= SAS_OPEN_TO
;
2850 case IO_XFER_ERROR_OFFSET_MISMATCH
:
2851 PM8001_IO_DBG(pm8001_ha
,
2852 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2853 ts
->resp
= SAS_TASK_COMPLETE
;
2854 ts
->stat
= SAS_OPEN_TO
;
2856 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN
:
2857 PM8001_IO_DBG(pm8001_ha
,
2858 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2859 ts
->resp
= SAS_TASK_COMPLETE
;
2860 ts
->stat
= SAS_OPEN_TO
;
2862 case IO_XFER_CMD_FRAME_ISSUED
:
2863 PM8001_IO_DBG(pm8001_ha
,
2864 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2866 case IO_XFER_PIO_SETUP_ERROR
:
2867 PM8001_IO_DBG(pm8001_ha
,
2868 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2869 ts
->resp
= SAS_TASK_COMPLETE
;
2870 ts
->stat
= SAS_OPEN_TO
;
2873 PM8001_IO_DBG(pm8001_ha
,
2874 pm8001_printk("Unknown status 0x%x\n", event
));
2875 /* not allowed case. Therefore, return failed status */
2876 ts
->resp
= SAS_TASK_COMPLETE
;
2877 ts
->stat
= SAS_OPEN_TO
;
2880 spin_lock_irqsave(&t
->task_state_lock
, flags
);
2881 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
2882 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
2883 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2884 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
2885 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2886 PM8001_FAIL_DBG(pm8001_ha
,
2887 pm8001_printk("task 0x%p done with io_status 0x%x"
2888 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2889 t
, event
, ts
->resp
, ts
->stat
));
2890 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
2892 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
2893 pm8001_ccb_task_free_done(pm8001_ha
, t
, ccb
, tag
);
2897 /*See the comments for mpi_ssp_completion */
2899 mpi_smp_completion(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
2903 struct pm8001_ccb_info
*ccb
;
2904 unsigned long flags
;
2907 struct smp_completion_resp
*psmpPayload
;
2908 struct task_status_struct
*ts
;
2909 struct pm8001_device
*pm8001_dev
;
2911 psmpPayload
= (struct smp_completion_resp
*)(piomb
+ 4);
2912 status
= le32_to_cpu(psmpPayload
->status
);
2913 tag
= le32_to_cpu(psmpPayload
->tag
);
2915 ccb
= &pm8001_ha
->ccb_info
[tag
];
2916 param
= le32_to_cpu(psmpPayload
->param
);
2918 ts
= &t
->task_status
;
2919 pm8001_dev
= ccb
->device
;
2921 PM8001_FAIL_DBG(pm8001_ha
,
2922 pm8001_printk("smp IO status 0x%x\n", status
));
2923 if (unlikely(!t
|| !t
->lldd_task
|| !t
->dev
))
2928 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_SUCCESS\n"));
2929 ts
->resp
= SAS_TASK_COMPLETE
;
2930 ts
->stat
= SAM_STAT_GOOD
;
2932 pm8001_dev
->running_req
--;
2935 PM8001_IO_DBG(pm8001_ha
,
2936 pm8001_printk("IO_ABORTED IOMB\n"));
2937 ts
->resp
= SAS_TASK_COMPLETE
;
2938 ts
->stat
= SAS_ABORTED_TASK
;
2940 pm8001_dev
->running_req
--;
2943 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_UNDERFLOW\n"));
2944 ts
->resp
= SAS_TASK_COMPLETE
;
2945 ts
->stat
= SAS_DATA_OVERRUN
;
2948 pm8001_dev
->running_req
--;
2951 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("IO_NO_DEVICE\n"));
2952 ts
->resp
= SAS_TASK_COMPLETE
;
2953 ts
->stat
= SAS_PHY_DOWN
;
2955 case IO_ERROR_HW_TIMEOUT
:
2956 PM8001_IO_DBG(pm8001_ha
,
2957 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2958 ts
->resp
= SAS_TASK_COMPLETE
;
2959 ts
->stat
= SAM_STAT_BUSY
;
2961 case IO_XFER_ERROR_BREAK
:
2962 PM8001_IO_DBG(pm8001_ha
,
2963 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2964 ts
->resp
= SAS_TASK_COMPLETE
;
2965 ts
->stat
= SAM_STAT_BUSY
;
2967 case IO_XFER_ERROR_PHY_NOT_READY
:
2968 PM8001_IO_DBG(pm8001_ha
,
2969 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2970 ts
->resp
= SAS_TASK_COMPLETE
;
2971 ts
->stat
= SAM_STAT_BUSY
;
2973 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
:
2974 PM8001_IO_DBG(pm8001_ha
,
2975 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2976 ts
->resp
= SAS_TASK_COMPLETE
;
2977 ts
->stat
= SAS_OPEN_REJECT
;
2978 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2980 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION
:
2981 PM8001_IO_DBG(pm8001_ha
,
2982 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2983 ts
->resp
= SAS_TASK_COMPLETE
;
2984 ts
->stat
= SAS_OPEN_REJECT
;
2985 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2987 case IO_OPEN_CNX_ERROR_BREAK
:
2988 PM8001_IO_DBG(pm8001_ha
,
2989 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2990 ts
->resp
= SAS_TASK_COMPLETE
;
2991 ts
->stat
= SAS_OPEN_REJECT
;
2992 ts
->open_rej_reason
= SAS_OREJ_RSVD_CONT0
;
2994 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
:
2995 PM8001_IO_DBG(pm8001_ha
,
2996 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2997 ts
->resp
= SAS_TASK_COMPLETE
;
2998 ts
->stat
= SAS_OPEN_REJECT
;
2999 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
3000 pm8001_handle_event(pm8001_ha
,
3002 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
);
3004 case IO_OPEN_CNX_ERROR_BAD_DESTINATION
:
3005 PM8001_IO_DBG(pm8001_ha
,
3006 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3007 ts
->resp
= SAS_TASK_COMPLETE
;
3008 ts
->stat
= SAS_OPEN_REJECT
;
3009 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
3011 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
:
3012 PM8001_IO_DBG(pm8001_ha
,
3013 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3014 "NOT_SUPPORTED\n"));
3015 ts
->resp
= SAS_TASK_COMPLETE
;
3016 ts
->stat
= SAS_OPEN_REJECT
;
3017 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
3019 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION
:
3020 PM8001_IO_DBG(pm8001_ha
,
3021 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3022 ts
->resp
= SAS_TASK_COMPLETE
;
3023 ts
->stat
= SAS_OPEN_REJECT
;
3024 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
3026 case IO_XFER_ERROR_RX_FRAME
:
3027 PM8001_IO_DBG(pm8001_ha
,
3028 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3029 ts
->resp
= SAS_TASK_COMPLETE
;
3030 ts
->stat
= SAS_DEV_NO_RESPONSE
;
3032 case IO_XFER_OPEN_RETRY_TIMEOUT
:
3033 PM8001_IO_DBG(pm8001_ha
,
3034 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3035 ts
->resp
= SAS_TASK_COMPLETE
;
3036 ts
->stat
= SAS_OPEN_REJECT
;
3037 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
3039 case IO_ERROR_INTERNAL_SMP_RESOURCE
:
3040 PM8001_IO_DBG(pm8001_ha
,
3041 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3042 ts
->resp
= SAS_TASK_COMPLETE
;
3043 ts
->stat
= SAS_QUEUE_FULL
;
3045 case IO_PORT_IN_RESET
:
3046 PM8001_IO_DBG(pm8001_ha
,
3047 pm8001_printk("IO_PORT_IN_RESET\n"));
3048 ts
->resp
= SAS_TASK_COMPLETE
;
3049 ts
->stat
= SAS_OPEN_REJECT
;
3050 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
3052 case IO_DS_NON_OPERATIONAL
:
3053 PM8001_IO_DBG(pm8001_ha
,
3054 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3055 ts
->resp
= SAS_TASK_COMPLETE
;
3056 ts
->stat
= SAS_DEV_NO_RESPONSE
;
3058 case IO_DS_IN_RECOVERY
:
3059 PM8001_IO_DBG(pm8001_ha
,
3060 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3061 ts
->resp
= SAS_TASK_COMPLETE
;
3062 ts
->stat
= SAS_OPEN_REJECT
;
3063 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
3065 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
:
3066 PM8001_IO_DBG(pm8001_ha
,
3067 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3068 ts
->resp
= SAS_TASK_COMPLETE
;
3069 ts
->stat
= SAS_OPEN_REJECT
;
3070 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
3073 PM8001_IO_DBG(pm8001_ha
,
3074 pm8001_printk("Unknown status 0x%x\n", status
));
3075 ts
->resp
= SAS_TASK_COMPLETE
;
3076 ts
->stat
= SAS_DEV_NO_RESPONSE
;
3077 /* not allowed case. Therefore, return failed status */
3080 spin_lock_irqsave(&t
->task_state_lock
, flags
);
3081 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
3082 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
3083 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
3084 if (unlikely((t
->task_state_flags
& SAS_TASK_STATE_ABORTED
))) {
3085 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
3086 PM8001_FAIL_DBG(pm8001_ha
, pm8001_printk("task 0x%p done with"
3087 " io_status 0x%x resp 0x%x "
3088 "stat 0x%x but aborted by upper layer!\n",
3089 t
, status
, ts
->resp
, ts
->stat
));
3090 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
3092 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
3093 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
3094 mb();/* in order to force CPU ordering */
3099 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info
*pm8001_ha
,
3102 struct set_dev_state_resp
*pPayload
=
3103 (struct set_dev_state_resp
*)(piomb
+ 4);
3104 u32 tag
= le32_to_cpu(pPayload
->tag
);
3105 struct pm8001_ccb_info
*ccb
= &pm8001_ha
->ccb_info
[tag
];
3106 struct pm8001_device
*pm8001_dev
= ccb
->device
;
3107 u32 status
= le32_to_cpu(pPayload
->status
);
3108 u32 device_id
= le32_to_cpu(pPayload
->device_id
);
3109 u8 pds
= le32_to_cpu(pPayload
->pds_nds
) & PDS_BITS
;
3110 u8 nds
= le32_to_cpu(pPayload
->pds_nds
) & NDS_BITS
;
3111 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("Set device id = 0x%x state "
3112 "from 0x%x to 0x%x status = 0x%x!\n",
3113 device_id
, pds
, nds
, status
));
3114 complete(pm8001_dev
->setds_completion
);
3116 ccb
->ccb_tag
= 0xFFFFFFFF;
3117 pm8001_tag_free(pm8001_ha
, tag
);
3120 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3122 struct get_nvm_data_resp
*pPayload
=
3123 (struct get_nvm_data_resp
*)(piomb
+ 4);
3124 u32 tag
= le32_to_cpu(pPayload
->tag
);
3125 struct pm8001_ccb_info
*ccb
= &pm8001_ha
->ccb_info
[tag
];
3126 u32 dlen_status
= le32_to_cpu(pPayload
->dlen_status
);
3127 complete(pm8001_ha
->nvmd_completion
);
3128 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("Set nvm data complete!\n"));
3129 if ((dlen_status
& NVMD_STAT
) != 0) {
3130 PM8001_FAIL_DBG(pm8001_ha
,
3131 pm8001_printk("Set nvm data error!\n"));
3135 ccb
->ccb_tag
= 0xFFFFFFFF;
3136 pm8001_tag_free(pm8001_ha
, tag
);
3140 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3142 struct fw_control_ex
*fw_control_context
;
3143 struct get_nvm_data_resp
*pPayload
=
3144 (struct get_nvm_data_resp
*)(piomb
+ 4);
3145 u32 tag
= le32_to_cpu(pPayload
->tag
);
3146 struct pm8001_ccb_info
*ccb
= &pm8001_ha
->ccb_info
[tag
];
3147 u32 dlen_status
= le32_to_cpu(pPayload
->dlen_status
);
3148 u32 ir_tds_bn_dps_das_nvm
=
3149 le32_to_cpu(pPayload
->ir_tda_bn_dps_das_nvm
);
3150 void *virt_addr
= pm8001_ha
->memoryMap
.region
[NVMD
].virt_ptr
;
3151 fw_control_context
= ccb
->fw_control_context
;
3153 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("Get nvm data complete!\n"));
3154 if ((dlen_status
& NVMD_STAT
) != 0) {
3155 PM8001_FAIL_DBG(pm8001_ha
,
3156 pm8001_printk("Get nvm data error!\n"));
3157 complete(pm8001_ha
->nvmd_completion
);
3161 if (ir_tds_bn_dps_das_nvm
& IPMode
) {
3162 /* indirect mode - IR bit set */
3163 PM8001_MSG_DBG(pm8001_ha
,
3164 pm8001_printk("Get NVMD success, IR=1\n"));
3165 if ((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == TWI_DEVICE
) {
3166 if (ir_tds_bn_dps_das_nvm
== 0x80a80200) {
3167 memcpy(pm8001_ha
->sas_addr
,
3168 ((u8
*)virt_addr
+ 4),
3170 PM8001_MSG_DBG(pm8001_ha
,
3171 pm8001_printk("Get SAS address"
3172 " from VPD successfully!\n"));
3174 } else if (((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == C_SEEPROM
)
3175 || ((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == VPD_FLASH
) ||
3176 ((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == EXPAN_ROM
)) {
3178 } else if (((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == AAP1_RDUMP
)
3179 || ((ir_tds_bn_dps_das_nvm
& NVMD_TYPE
) == IOP_RDUMP
)) {
3182 /* Should not be happened*/
3183 PM8001_MSG_DBG(pm8001_ha
,
3184 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3185 ir_tds_bn_dps_das_nvm
));
3187 } else /* direct mode */{
3188 PM8001_MSG_DBG(pm8001_ha
,
3189 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3190 (dlen_status
& NVMD_LEN
) >> 24));
3192 /* Though fw_control_context is freed below, usrAddr still needs
3193 * to be updated as this holds the response to the request function
3195 memcpy(fw_control_context
->usrAddr
,
3196 pm8001_ha
->memoryMap
.region
[NVMD
].virt_ptr
,
3197 fw_control_context
->len
);
3198 kfree(ccb
->fw_control_context
);
3200 ccb
->ccb_tag
= 0xFFFFFFFF;
3201 pm8001_tag_free(pm8001_ha
, tag
);
3202 complete(pm8001_ha
->nvmd_completion
);
3205 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3208 struct local_phy_ctl_resp
*pPayload
=
3209 (struct local_phy_ctl_resp
*)(piomb
+ 4);
3210 u32 status
= le32_to_cpu(pPayload
->status
);
3211 u32 phy_id
= le32_to_cpu(pPayload
->phyop_phyid
) & ID_BITS
;
3212 u32 phy_op
= le32_to_cpu(pPayload
->phyop_phyid
) & OP_BITS
;
3213 tag
= le32_to_cpu(pPayload
->tag
);
3215 PM8001_MSG_DBG(pm8001_ha
,
3216 pm8001_printk("%x phy execute %x phy op failed!\n",
3219 PM8001_MSG_DBG(pm8001_ha
,
3220 pm8001_printk("%x phy execute %x phy op success!\n",
3222 pm8001_ha
->phy
[phy_id
].reset_success
= true;
3224 if (pm8001_ha
->phy
[phy_id
].enable_completion
) {
3225 complete(pm8001_ha
->phy
[phy_id
].enable_completion
);
3226 pm8001_ha
->phy
[phy_id
].enable_completion
= NULL
;
3228 pm8001_tag_free(pm8001_ha
, tag
);
3233 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3234 * @pm8001_ha: our hba card information
3235 * @i: which phy that received the event.
3237 * when HBA driver received the identify done event or initiate FIS received
3238 * event(for SATA), it will invoke this function to notify the sas layer that
3239 * the sas toplogy has formed, please discover the the whole sas domain,
3240 * while receive a broadcast(change) primitive just tell the sas
3241 * layer to discover the changed domain rather than the whole domain.
3243 void pm8001_bytes_dmaed(struct pm8001_hba_info
*pm8001_ha
, int i
)
3245 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[i
];
3246 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
3247 struct sas_ha_struct
*sas_ha
;
3248 if (!phy
->phy_attached
)
3251 sas_ha
= pm8001_ha
->sas
;
3253 struct sas_phy
*sphy
= sas_phy
->phy
;
3254 sphy
->negotiated_linkrate
= sas_phy
->linkrate
;
3255 sphy
->minimum_linkrate
= phy
->minimum_linkrate
;
3256 sphy
->minimum_linkrate_hw
= SAS_LINK_RATE_1_5_GBPS
;
3257 sphy
->maximum_linkrate
= phy
->maximum_linkrate
;
3258 sphy
->maximum_linkrate_hw
= phy
->maximum_linkrate
;
3261 if (phy
->phy_type
& PORT_TYPE_SAS
) {
3262 struct sas_identify_frame
*id
;
3263 id
= (struct sas_identify_frame
*)phy
->frame_rcvd
;
3264 id
->dev_type
= phy
->identify
.device_type
;
3265 id
->initiator_bits
= SAS_PROTOCOL_ALL
;
3266 id
->target_bits
= phy
->identify
.target_port_protocols
;
3267 } else if (phy
->phy_type
& PORT_TYPE_SATA
) {
3270 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("phy %d byte dmaded.\n", i
));
3272 sas_phy
->frame_rcvd_size
= phy
->frame_rcvd_size
;
3273 pm8001_ha
->sas
->notify_port_event(sas_phy
, PORTE_BYTES_DMAED
);
3276 /* Get the link rate speed */
3277 void pm8001_get_lrate_mode(struct pm8001_phy
*phy
, u8 link_rate
)
3279 struct sas_phy
*sas_phy
= phy
->sas_phy
.phy
;
3281 switch (link_rate
) {
3283 phy
->sas_phy
.linkrate
= SAS_LINK_RATE_12_0_GBPS
;
3284 phy
->sas_phy
.phy
->negotiated_linkrate
= SAS_LINK_RATE_12_0_GBPS
;
3287 phy
->sas_phy
.linkrate
= SAS_LINK_RATE_6_0_GBPS
;
3288 phy
->sas_phy
.phy
->negotiated_linkrate
= SAS_LINK_RATE_6_0_GBPS
;
3291 phy
->sas_phy
.linkrate
= SAS_LINK_RATE_3_0_GBPS
;
3292 phy
->sas_phy
.phy
->negotiated_linkrate
= SAS_LINK_RATE_3_0_GBPS
;
3295 phy
->sas_phy
.linkrate
= SAS_LINK_RATE_1_5_GBPS
;
3296 phy
->sas_phy
.phy
->negotiated_linkrate
= SAS_LINK_RATE_1_5_GBPS
;
3299 sas_phy
->negotiated_linkrate
= phy
->sas_phy
.linkrate
;
3300 sas_phy
->maximum_linkrate_hw
= SAS_LINK_RATE_6_0_GBPS
;
3301 sas_phy
->minimum_linkrate_hw
= SAS_LINK_RATE_1_5_GBPS
;
3302 sas_phy
->maximum_linkrate
= SAS_LINK_RATE_6_0_GBPS
;
3303 sas_phy
->minimum_linkrate
= SAS_LINK_RATE_1_5_GBPS
;
3307 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3308 * @phy: pointer to asd_phy
3309 * @sas_addr: pointer to buffer where the SAS address is to be written
3311 * This function extracts the SAS address from an IDENTIFY frame
3312 * received. If OOB is SATA, then a SAS address is generated from the
3315 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3318 void pm8001_get_attached_sas_addr(struct pm8001_phy
*phy
,
3321 if (phy
->sas_phy
.frame_rcvd
[0] == 0x34
3322 && phy
->sas_phy
.oob_mode
== SATA_OOB_MODE
) {
3323 struct pm8001_hba_info
*pm8001_ha
= phy
->sas_phy
.ha
->lldd_ha
;
3324 /* FIS device-to-host */
3325 u64 addr
= be64_to_cpu(*(__be64
*)pm8001_ha
->sas_addr
);
3326 addr
+= phy
->sas_phy
.id
;
3327 *(__be64
*)sas_addr
= cpu_to_be64(addr
);
3329 struct sas_identify_frame
*idframe
=
3330 (void *) phy
->sas_phy
.frame_rcvd
;
3331 memcpy(sas_addr
, idframe
->sas_addr
, SAS_ADDR_SIZE
);
3336 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3337 * @pm8001_ha: our hba card information
3338 * @Qnum: the outbound queue message number.
3339 * @SEA: source of event to ack
3340 * @port_id: port id.
3342 * @param0: parameter 0.
3343 * @param1: parameter 1.
3345 static void pm8001_hw_event_ack_req(struct pm8001_hba_info
*pm8001_ha
,
3346 u32 Qnum
, u32 SEA
, u32 port_id
, u32 phyId
, u32 param0
, u32 param1
)
3348 struct hw_event_ack_req payload
;
3349 u32 opc
= OPC_INB_SAS_HW_EVENT_ACK
;
3351 struct inbound_queue_table
*circularQ
;
3353 memset((u8
*)&payload
, 0, sizeof(payload
));
3354 circularQ
= &pm8001_ha
->inbnd_q_tbl
[Qnum
];
3355 payload
.tag
= cpu_to_le32(1);
3356 payload
.sea_phyid_portid
= cpu_to_le32(((SEA
& 0xFFFF) << 8) |
3357 ((phyId
& 0x0F) << 4) | (port_id
& 0x0F));
3358 payload
.param0
= cpu_to_le32(param0
);
3359 payload
.param1
= cpu_to_le32(param1
);
3360 pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
3363 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info
*pm8001_ha
,
3364 u32 phyId
, u32 phy_op
);
3367 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3368 * @pm8001_ha: our hba card information
3369 * @piomb: IO message buffer
3372 hw_event_sas_phy_up(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3374 struct hw_event_resp
*pPayload
=
3375 (struct hw_event_resp
*)(piomb
+ 4);
3376 u32 lr_evt_status_phyid_portid
=
3377 le32_to_cpu(pPayload
->lr_evt_status_phyid_portid
);
3379 (u8
)((lr_evt_status_phyid_portid
& 0xF0000000) >> 28);
3380 u8 port_id
= (u8
)(lr_evt_status_phyid_portid
& 0x0000000F);
3382 (u8
)((lr_evt_status_phyid_portid
& 0x000000F0) >> 4);
3383 u32 npip_portstate
= le32_to_cpu(pPayload
->npip_portstate
);
3384 u8 portstate
= (u8
)(npip_portstate
& 0x0000000F);
3385 struct pm8001_port
*port
= &pm8001_ha
->port
[port_id
];
3386 struct sas_ha_struct
*sas_ha
= pm8001_ha
->sas
;
3387 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[phy_id
];
3388 unsigned long flags
;
3389 u8 deviceType
= pPayload
->sas_identify
.dev_type
;
3390 port
->port_state
= portstate
;
3391 phy
->phy_state
= PHY_STATE_LINK_UP_SPC
;
3392 PM8001_MSG_DBG(pm8001_ha
,
3393 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3396 switch (deviceType
) {
3397 case SAS_PHY_UNUSED
:
3398 PM8001_MSG_DBG(pm8001_ha
,
3399 pm8001_printk("device type no device.\n"));
3401 case SAS_END_DEVICE
:
3402 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("end device.\n"));
3403 pm8001_chip_phy_ctl_req(pm8001_ha
, phy_id
,
3404 PHY_NOTIFY_ENABLE_SPINUP
);
3405 port
->port_attached
= 1;
3406 pm8001_get_lrate_mode(phy
, link_rate
);
3408 case SAS_EDGE_EXPANDER_DEVICE
:
3409 PM8001_MSG_DBG(pm8001_ha
,
3410 pm8001_printk("expander device.\n"));
3411 port
->port_attached
= 1;
3412 pm8001_get_lrate_mode(phy
, link_rate
);
3414 case SAS_FANOUT_EXPANDER_DEVICE
:
3415 PM8001_MSG_DBG(pm8001_ha
,
3416 pm8001_printk("fanout expander device.\n"));
3417 port
->port_attached
= 1;
3418 pm8001_get_lrate_mode(phy
, link_rate
);
3421 PM8001_MSG_DBG(pm8001_ha
,
3422 pm8001_printk("unknown device type(%x)\n", deviceType
));
3425 phy
->phy_type
|= PORT_TYPE_SAS
;
3426 phy
->identify
.device_type
= deviceType
;
3427 phy
->phy_attached
= 1;
3428 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
3429 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SSP
;
3430 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
)
3431 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SMP
;
3432 phy
->sas_phy
.oob_mode
= SAS_OOB_MODE
;
3433 sas_ha
->notify_phy_event(&phy
->sas_phy
, PHYE_OOB_DONE
);
3434 spin_lock_irqsave(&phy
->sas_phy
.frame_rcvd_lock
, flags
);
3435 memcpy(phy
->frame_rcvd
, &pPayload
->sas_identify
,
3436 sizeof(struct sas_identify_frame
)-4);
3437 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
) - 4;
3438 pm8001_get_attached_sas_addr(phy
, phy
->sas_phy
.attached_sas_addr
);
3439 spin_unlock_irqrestore(&phy
->sas_phy
.frame_rcvd_lock
, flags
);
3440 if (pm8001_ha
->flags
== PM8001F_RUN_TIME
)
3441 mdelay(200);/*delay a moment to wait disk to spinup*/
3442 pm8001_bytes_dmaed(pm8001_ha
, phy_id
);
3446 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3447 * @pm8001_ha: our hba card information
3448 * @piomb: IO message buffer
3451 hw_event_sata_phy_up(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3453 struct hw_event_resp
*pPayload
=
3454 (struct hw_event_resp
*)(piomb
+ 4);
3455 u32 lr_evt_status_phyid_portid
=
3456 le32_to_cpu(pPayload
->lr_evt_status_phyid_portid
);
3458 (u8
)((lr_evt_status_phyid_portid
& 0xF0000000) >> 28);
3459 u8 port_id
= (u8
)(lr_evt_status_phyid_portid
& 0x0000000F);
3461 (u8
)((lr_evt_status_phyid_portid
& 0x000000F0) >> 4);
3462 u32 npip_portstate
= le32_to_cpu(pPayload
->npip_portstate
);
3463 u8 portstate
= (u8
)(npip_portstate
& 0x0000000F);
3464 struct pm8001_port
*port
= &pm8001_ha
->port
[port_id
];
3465 struct sas_ha_struct
*sas_ha
= pm8001_ha
->sas
;
3466 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[phy_id
];
3467 unsigned long flags
;
3468 PM8001_MSG_DBG(pm8001_ha
,
3469 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3470 " phy id = %d\n", port_id
, phy_id
));
3471 port
->port_state
= portstate
;
3472 phy
->phy_state
= PHY_STATE_LINK_UP_SPC
;
3473 port
->port_attached
= 1;
3474 pm8001_get_lrate_mode(phy
, link_rate
);
3475 phy
->phy_type
|= PORT_TYPE_SATA
;
3476 phy
->phy_attached
= 1;
3477 phy
->sas_phy
.oob_mode
= SATA_OOB_MODE
;
3478 sas_ha
->notify_phy_event(&phy
->sas_phy
, PHYE_OOB_DONE
);
3479 spin_lock_irqsave(&phy
->sas_phy
.frame_rcvd_lock
, flags
);
3480 memcpy(phy
->frame_rcvd
, ((u8
*)&pPayload
->sata_fis
- 4),
3481 sizeof(struct dev_to_host_fis
));
3482 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
3483 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
3484 phy
->identify
.device_type
= SAS_SATA_DEV
;
3485 pm8001_get_attached_sas_addr(phy
, phy
->sas_phy
.attached_sas_addr
);
3486 spin_unlock_irqrestore(&phy
->sas_phy
.frame_rcvd_lock
, flags
);
3487 pm8001_bytes_dmaed(pm8001_ha
, phy_id
);
3491 * hw_event_phy_down -we should notify the libsas the phy is down.
3492 * @pm8001_ha: our hba card information
3493 * @piomb: IO message buffer
3496 hw_event_phy_down(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3498 struct hw_event_resp
*pPayload
=
3499 (struct hw_event_resp
*)(piomb
+ 4);
3500 u32 lr_evt_status_phyid_portid
=
3501 le32_to_cpu(pPayload
->lr_evt_status_phyid_portid
);
3502 u8 port_id
= (u8
)(lr_evt_status_phyid_portid
& 0x0000000F);
3504 (u8
)((lr_evt_status_phyid_portid
& 0x000000F0) >> 4);
3505 u32 npip_portstate
= le32_to_cpu(pPayload
->npip_portstate
);
3506 u8 portstate
= (u8
)(npip_portstate
& 0x0000000F);
3507 struct pm8001_port
*port
= &pm8001_ha
->port
[port_id
];
3508 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[phy_id
];
3509 port
->port_state
= portstate
;
3511 phy
->identify
.device_type
= 0;
3512 phy
->phy_attached
= 0;
3513 memset(&phy
->dev_sas_addr
, 0, SAS_ADDR_SIZE
);
3514 switch (portstate
) {
3518 PM8001_MSG_DBG(pm8001_ha
,
3519 pm8001_printk(" PortInvalid portID %d\n", port_id
));
3520 PM8001_MSG_DBG(pm8001_ha
,
3521 pm8001_printk(" Last phy Down and port invalid\n"));
3522 port
->port_attached
= 0;
3523 pm8001_hw_event_ack_req(pm8001_ha
, 0, HW_EVENT_PHY_DOWN
,
3524 port_id
, phy_id
, 0, 0);
3527 PM8001_MSG_DBG(pm8001_ha
,
3528 pm8001_printk(" Port In Reset portID %d\n", port_id
));
3530 case PORT_NOT_ESTABLISHED
:
3531 PM8001_MSG_DBG(pm8001_ha
,
3532 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3533 port
->port_attached
= 0;
3536 PM8001_MSG_DBG(pm8001_ha
,
3537 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3538 PM8001_MSG_DBG(pm8001_ha
,
3539 pm8001_printk(" Last phy Down and port invalid\n"));
3540 port
->port_attached
= 0;
3541 pm8001_hw_event_ack_req(pm8001_ha
, 0, HW_EVENT_PHY_DOWN
,
3542 port_id
, phy_id
, 0, 0);
3545 port
->port_attached
= 0;
3546 PM8001_MSG_DBG(pm8001_ha
,
3547 pm8001_printk(" phy Down and(default) = %x\n",
3555 * pm8001_mpi_reg_resp -process register device ID response.
3556 * @pm8001_ha: our hba card information
3557 * @piomb: IO message buffer
3559 * when sas layer find a device it will notify LLDD, then the driver register
3560 * the domain device to FW, this event is the return device ID which the FW
3561 * has assigned, from now,inter-communication with FW is no longer using the
3562 * SAS address, use device ID which FW assigned.
3564 int pm8001_mpi_reg_resp(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3569 struct pm8001_ccb_info
*ccb
;
3570 struct pm8001_device
*pm8001_dev
;
3571 struct dev_reg_resp
*registerRespPayload
=
3572 (struct dev_reg_resp
*)(piomb
+ 4);
3574 htag
= le32_to_cpu(registerRespPayload
->tag
);
3575 ccb
= &pm8001_ha
->ccb_info
[htag
];
3576 pm8001_dev
= ccb
->device
;
3577 status
= le32_to_cpu(registerRespPayload
->status
);
3578 device_id
= le32_to_cpu(registerRespPayload
->device_id
);
3579 PM8001_MSG_DBG(pm8001_ha
,
3580 pm8001_printk(" register device is status = %d\n", status
));
3582 case DEVREG_SUCCESS
:
3583 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("DEVREG_SUCCESS\n"));
3584 pm8001_dev
->device_id
= device_id
;
3586 case DEVREG_FAILURE_OUT_OF_RESOURCE
:
3587 PM8001_MSG_DBG(pm8001_ha
,
3588 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3590 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED
:
3591 PM8001_MSG_DBG(pm8001_ha
,
3592 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3594 case DEVREG_FAILURE_INVALID_PHY_ID
:
3595 PM8001_MSG_DBG(pm8001_ha
,
3596 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3598 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED
:
3599 PM8001_MSG_DBG(pm8001_ha
,
3600 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3602 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE
:
3603 PM8001_MSG_DBG(pm8001_ha
,
3604 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3606 case DEVREG_FAILURE_PORT_NOT_VALID_STATE
:
3607 PM8001_MSG_DBG(pm8001_ha
,
3608 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3610 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID
:
3611 PM8001_MSG_DBG(pm8001_ha
,
3612 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3615 PM8001_MSG_DBG(pm8001_ha
,
3616 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"));
3619 complete(pm8001_dev
->dcompletion
);
3621 ccb
->ccb_tag
= 0xFFFFFFFF;
3622 pm8001_tag_free(pm8001_ha
, htag
);
3626 int pm8001_mpi_dereg_resp(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3630 struct dev_reg_resp
*registerRespPayload
=
3631 (struct dev_reg_resp
*)(piomb
+ 4);
3633 status
= le32_to_cpu(registerRespPayload
->status
);
3634 device_id
= le32_to_cpu(registerRespPayload
->device_id
);
3636 PM8001_MSG_DBG(pm8001_ha
,
3637 pm8001_printk(" deregister device failed ,status = %x"
3638 ", device_id = %x\n", status
, device_id
));
3643 * fw_flash_update_resp - Response from FW for flash update command.
3644 * @pm8001_ha: our hba card information
3645 * @piomb: IO message buffer
3647 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info
*pm8001_ha
,
3651 struct fw_flash_Update_resp
*ppayload
=
3652 (struct fw_flash_Update_resp
*)(piomb
+ 4);
3653 u32 tag
= le32_to_cpu(ppayload
->tag
);
3654 struct pm8001_ccb_info
*ccb
= &pm8001_ha
->ccb_info
[tag
];
3655 status
= le32_to_cpu(ppayload
->status
);
3657 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT
:
3658 PM8001_MSG_DBG(pm8001_ha
,
3659 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3661 case FLASH_UPDATE_IN_PROGRESS
:
3662 PM8001_MSG_DBG(pm8001_ha
,
3663 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3665 case FLASH_UPDATE_HDR_ERR
:
3666 PM8001_MSG_DBG(pm8001_ha
,
3667 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3669 case FLASH_UPDATE_OFFSET_ERR
:
3670 PM8001_MSG_DBG(pm8001_ha
,
3671 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3673 case FLASH_UPDATE_CRC_ERR
:
3674 PM8001_MSG_DBG(pm8001_ha
,
3675 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3677 case FLASH_UPDATE_LENGTH_ERR
:
3678 PM8001_MSG_DBG(pm8001_ha
,
3679 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3681 case FLASH_UPDATE_HW_ERR
:
3682 PM8001_MSG_DBG(pm8001_ha
,
3683 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3685 case FLASH_UPDATE_DNLD_NOT_SUPPORTED
:
3686 PM8001_MSG_DBG(pm8001_ha
,
3687 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3689 case FLASH_UPDATE_DISABLED
:
3690 PM8001_MSG_DBG(pm8001_ha
,
3691 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3694 PM8001_MSG_DBG(pm8001_ha
,
3695 pm8001_printk("No matched status = %d\n", status
));
3698 kfree(ccb
->fw_control_context
);
3700 ccb
->ccb_tag
= 0xFFFFFFFF;
3701 pm8001_tag_free(pm8001_ha
, tag
);
3702 complete(pm8001_ha
->nvmd_completion
);
3706 int pm8001_mpi_general_event(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3710 struct general_event_resp
*pPayload
=
3711 (struct general_event_resp
*)(piomb
+ 4);
3712 status
= le32_to_cpu(pPayload
->status
);
3713 PM8001_MSG_DBG(pm8001_ha
,
3714 pm8001_printk(" status = 0x%x\n", status
));
3715 for (i
= 0; i
< GENERAL_EVENT_PAYLOAD
; i
++)
3716 PM8001_MSG_DBG(pm8001_ha
,
3717 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i
,
3718 pPayload
->inb_IOMB_payload
[i
]));
3722 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
3725 struct pm8001_ccb_info
*ccb
;
3726 unsigned long flags
;
3729 struct task_status_struct
*ts
;
3730 struct pm8001_device
*pm8001_dev
;
3732 struct task_abort_resp
*pPayload
=
3733 (struct task_abort_resp
*)(piomb
+ 4);
3735 status
= le32_to_cpu(pPayload
->status
);
3736 tag
= le32_to_cpu(pPayload
->tag
);
3738 PM8001_FAIL_DBG(pm8001_ha
,
3739 pm8001_printk(" TAG NULL. RETURNING !!!"));
3743 scp
= le32_to_cpu(pPayload
->scp
);
3744 ccb
= &pm8001_ha
->ccb_info
[tag
];
3746 pm8001_dev
= ccb
->device
; /* retrieve device */
3749 PM8001_FAIL_DBG(pm8001_ha
,
3750 pm8001_printk(" TASK NULL. RETURNING !!!"));
3753 ts
= &t
->task_status
;
3755 PM8001_FAIL_DBG(pm8001_ha
,
3756 pm8001_printk("task abort failed status 0x%x ,"
3757 "tag = 0x%x, scp= 0x%x\n", status
, tag
, scp
));
3760 PM8001_EH_DBG(pm8001_ha
, pm8001_printk("IO_SUCCESS\n"));
3761 ts
->resp
= SAS_TASK_COMPLETE
;
3762 ts
->stat
= SAM_STAT_GOOD
;
3765 PM8001_EH_DBG(pm8001_ha
, pm8001_printk("IO_NOT_VALID\n"));
3766 ts
->resp
= TMF_RESP_FUNC_FAILED
;
3769 spin_lock_irqsave(&t
->task_state_lock
, flags
);
3770 t
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
3771 t
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
3772 t
->task_state_flags
|= SAS_TASK_STATE_DONE
;
3773 spin_unlock_irqrestore(&t
->task_state_lock
, flags
);
3774 pm8001_ccb_task_free(pm8001_ha
, t
, ccb
, tag
);
3777 if (pm8001_dev
->id
& NCQ_ABORT_ALL_FLAG
) {
3778 pm8001_tag_free(pm8001_ha
, tag
);
3780 /* clear the flag */
3781 pm8001_dev
->id
&= 0xBFFFFFFF;
3789 * mpi_hw_event -The hw event has come.
3790 * @pm8001_ha: our hba card information
3791 * @piomb: IO message buffer
3793 static int mpi_hw_event(struct pm8001_hba_info
*pm8001_ha
, void* piomb
)
3795 unsigned long flags
;
3796 struct hw_event_resp
*pPayload
=
3797 (struct hw_event_resp
*)(piomb
+ 4);
3798 u32 lr_evt_status_phyid_portid
=
3799 le32_to_cpu(pPayload
->lr_evt_status_phyid_portid
);
3800 u8 port_id
= (u8
)(lr_evt_status_phyid_portid
& 0x0000000F);
3802 (u8
)((lr_evt_status_phyid_portid
& 0x000000F0) >> 4);
3804 (u16
)((lr_evt_status_phyid_portid
& 0x00FFFF00) >> 8);
3806 (u8
)((lr_evt_status_phyid_portid
& 0x0F000000) >> 24);
3807 struct sas_ha_struct
*sas_ha
= pm8001_ha
->sas
;
3808 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[phy_id
];
3809 struct asd_sas_phy
*sas_phy
= sas_ha
->sas_phy
[phy_id
];
3810 PM8001_MSG_DBG(pm8001_ha
,
3811 pm8001_printk("outbound queue HW event & event type : "));
3812 switch (eventType
) {
3813 case HW_EVENT_PHY_START_STATUS
:
3814 PM8001_MSG_DBG(pm8001_ha
,
3815 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3816 " status = %x\n", status
));
3819 if (pm8001_ha
->flags
== PM8001F_RUN_TIME
)
3820 complete(phy
->enable_completion
);
3823 case HW_EVENT_SAS_PHY_UP
:
3824 PM8001_MSG_DBG(pm8001_ha
,
3825 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3826 hw_event_sas_phy_up(pm8001_ha
, piomb
);
3828 case HW_EVENT_SATA_PHY_UP
:
3829 PM8001_MSG_DBG(pm8001_ha
,
3830 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3831 hw_event_sata_phy_up(pm8001_ha
, piomb
);
3833 case HW_EVENT_PHY_STOP_STATUS
:
3834 PM8001_MSG_DBG(pm8001_ha
,
3835 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3836 "status = %x\n", status
));
3840 case HW_EVENT_SATA_SPINUP_HOLD
:
3841 PM8001_MSG_DBG(pm8001_ha
,
3842 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3843 sas_ha
->notify_phy_event(&phy
->sas_phy
, PHYE_SPINUP_HOLD
);
3845 case HW_EVENT_PHY_DOWN
:
3846 PM8001_MSG_DBG(pm8001_ha
,
3847 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3848 sas_ha
->notify_phy_event(&phy
->sas_phy
, PHYE_LOSS_OF_SIGNAL
);
3849 phy
->phy_attached
= 0;
3851 hw_event_phy_down(pm8001_ha
, piomb
);
3853 case HW_EVENT_PORT_INVALID
:
3854 PM8001_MSG_DBG(pm8001_ha
,
3855 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3856 sas_phy_disconnected(sas_phy
);
3857 phy
->phy_attached
= 0;
3858 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3860 /* the broadcast change primitive received, tell the LIBSAS this event
3861 to revalidate the sas domain*/
3862 case HW_EVENT_BROADCAST_CHANGE
:
3863 PM8001_MSG_DBG(pm8001_ha
,
3864 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3865 pm8001_hw_event_ack_req(pm8001_ha
, 0, HW_EVENT_BROADCAST_CHANGE
,
3866 port_id
, phy_id
, 1, 0);
3867 spin_lock_irqsave(&sas_phy
->sas_prim_lock
, flags
);
3868 sas_phy
->sas_prim
= HW_EVENT_BROADCAST_CHANGE
;
3869 spin_unlock_irqrestore(&sas_phy
->sas_prim_lock
, flags
);
3870 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
3872 case HW_EVENT_PHY_ERROR
:
3873 PM8001_MSG_DBG(pm8001_ha
,
3874 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3875 sas_phy_disconnected(&phy
->sas_phy
);
3876 phy
->phy_attached
= 0;
3877 sas_ha
->notify_phy_event(&phy
->sas_phy
, PHYE_OOB_ERROR
);
3879 case HW_EVENT_BROADCAST_EXP
:
3880 PM8001_MSG_DBG(pm8001_ha
,
3881 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3882 spin_lock_irqsave(&sas_phy
->sas_prim_lock
, flags
);
3883 sas_phy
->sas_prim
= HW_EVENT_BROADCAST_EXP
;
3884 spin_unlock_irqrestore(&sas_phy
->sas_prim_lock
, flags
);
3885 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
3887 case HW_EVENT_LINK_ERR_INVALID_DWORD
:
3888 PM8001_MSG_DBG(pm8001_ha
,
3889 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3890 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3891 HW_EVENT_LINK_ERR_INVALID_DWORD
, port_id
, phy_id
, 0, 0);
3892 sas_phy_disconnected(sas_phy
);
3893 phy
->phy_attached
= 0;
3894 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3896 case HW_EVENT_LINK_ERR_DISPARITY_ERROR
:
3897 PM8001_MSG_DBG(pm8001_ha
,
3898 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3899 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3900 HW_EVENT_LINK_ERR_DISPARITY_ERROR
,
3901 port_id
, phy_id
, 0, 0);
3902 sas_phy_disconnected(sas_phy
);
3903 phy
->phy_attached
= 0;
3904 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3906 case HW_EVENT_LINK_ERR_CODE_VIOLATION
:
3907 PM8001_MSG_DBG(pm8001_ha
,
3908 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3909 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3910 HW_EVENT_LINK_ERR_CODE_VIOLATION
,
3911 port_id
, phy_id
, 0, 0);
3912 sas_phy_disconnected(sas_phy
);
3913 phy
->phy_attached
= 0;
3914 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3916 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH
:
3917 PM8001_MSG_DBG(pm8001_ha
,
3918 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3919 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3920 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH
,
3921 port_id
, phy_id
, 0, 0);
3922 sas_phy_disconnected(sas_phy
);
3923 phy
->phy_attached
= 0;
3924 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3926 case HW_EVENT_MALFUNCTION
:
3927 PM8001_MSG_DBG(pm8001_ha
,
3928 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3930 case HW_EVENT_BROADCAST_SES
:
3931 PM8001_MSG_DBG(pm8001_ha
,
3932 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3933 spin_lock_irqsave(&sas_phy
->sas_prim_lock
, flags
);
3934 sas_phy
->sas_prim
= HW_EVENT_BROADCAST_SES
;
3935 spin_unlock_irqrestore(&sas_phy
->sas_prim_lock
, flags
);
3936 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
3938 case HW_EVENT_INBOUND_CRC_ERROR
:
3939 PM8001_MSG_DBG(pm8001_ha
,
3940 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3941 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3942 HW_EVENT_INBOUND_CRC_ERROR
,
3943 port_id
, phy_id
, 0, 0);
3945 case HW_EVENT_HARD_RESET_RECEIVED
:
3946 PM8001_MSG_DBG(pm8001_ha
,
3947 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3948 sas_ha
->notify_port_event(sas_phy
, PORTE_HARD_RESET
);
3950 case HW_EVENT_ID_FRAME_TIMEOUT
:
3951 PM8001_MSG_DBG(pm8001_ha
,
3952 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3953 sas_phy_disconnected(sas_phy
);
3954 phy
->phy_attached
= 0;
3955 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3957 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED
:
3958 PM8001_MSG_DBG(pm8001_ha
,
3959 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3960 pm8001_hw_event_ack_req(pm8001_ha
, 0,
3961 HW_EVENT_LINK_ERR_PHY_RESET_FAILED
,
3962 port_id
, phy_id
, 0, 0);
3963 sas_phy_disconnected(sas_phy
);
3964 phy
->phy_attached
= 0;
3965 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3967 case HW_EVENT_PORT_RESET_TIMER_TMO
:
3968 PM8001_MSG_DBG(pm8001_ha
,
3969 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3970 sas_phy_disconnected(sas_phy
);
3971 phy
->phy_attached
= 0;
3972 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3974 case HW_EVENT_PORT_RECOVERY_TIMER_TMO
:
3975 PM8001_MSG_DBG(pm8001_ha
,
3976 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3977 sas_phy_disconnected(sas_phy
);
3978 phy
->phy_attached
= 0;
3979 sas_ha
->notify_port_event(sas_phy
, PORTE_LINK_RESET_ERR
);
3981 case HW_EVENT_PORT_RECOVER
:
3982 PM8001_MSG_DBG(pm8001_ha
,
3983 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3985 case HW_EVENT_PORT_RESET_COMPLETE
:
3986 PM8001_MSG_DBG(pm8001_ha
,
3987 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3989 case EVENT_BROADCAST_ASYNCH_EVENT
:
3990 PM8001_MSG_DBG(pm8001_ha
,
3991 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3994 PM8001_MSG_DBG(pm8001_ha
,
3995 pm8001_printk("Unknown event type = %x\n", eventType
));
4002 * process_one_iomb - process one outbound Queue memory block
4003 * @pm8001_ha: our hba card information
4004 * @piomb: IO message buffer
4006 static void process_one_iomb(struct pm8001_hba_info
*pm8001_ha
, void *piomb
)
4008 __le32 pHeader
= *(__le32
*)piomb
;
4009 u8 opc
= (u8
)((le32_to_cpu(pHeader
)) & 0xFFF);
4011 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("process_one_iomb:"));
4015 PM8001_MSG_DBG(pm8001_ha
, pm8001_printk("OPC_OUB_ECHO\n"));
4017 case OPC_OUB_HW_EVENT
:
4018 PM8001_MSG_DBG(pm8001_ha
,
4019 pm8001_printk("OPC_OUB_HW_EVENT\n"));
4020 mpi_hw_event(pm8001_ha
, piomb
);
4022 case OPC_OUB_SSP_COMP
:
4023 PM8001_MSG_DBG(pm8001_ha
,
4024 pm8001_printk("OPC_OUB_SSP_COMP\n"));
4025 mpi_ssp_completion(pm8001_ha
, piomb
);
4027 case OPC_OUB_SMP_COMP
:
4028 PM8001_MSG_DBG(pm8001_ha
,
4029 pm8001_printk("OPC_OUB_SMP_COMP\n"));
4030 mpi_smp_completion(pm8001_ha
, piomb
);
4032 case OPC_OUB_LOCAL_PHY_CNTRL
:
4033 PM8001_MSG_DBG(pm8001_ha
,
4034 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4035 pm8001_mpi_local_phy_ctl(pm8001_ha
, piomb
);
4037 case OPC_OUB_DEV_REGIST
:
4038 PM8001_MSG_DBG(pm8001_ha
,
4039 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4040 pm8001_mpi_reg_resp(pm8001_ha
, piomb
);
4042 case OPC_OUB_DEREG_DEV
:
4043 PM8001_MSG_DBG(pm8001_ha
,
4044 pm8001_printk("unregister the device\n"));
4045 pm8001_mpi_dereg_resp(pm8001_ha
, piomb
);
4047 case OPC_OUB_GET_DEV_HANDLE
:
4048 PM8001_MSG_DBG(pm8001_ha
,
4049 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4051 case OPC_OUB_SATA_COMP
:
4052 PM8001_MSG_DBG(pm8001_ha
,
4053 pm8001_printk("OPC_OUB_SATA_COMP\n"));
4054 mpi_sata_completion(pm8001_ha
, piomb
);
4056 case OPC_OUB_SATA_EVENT
:
4057 PM8001_MSG_DBG(pm8001_ha
,
4058 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4059 mpi_sata_event(pm8001_ha
, piomb
);
4061 case OPC_OUB_SSP_EVENT
:
4062 PM8001_MSG_DBG(pm8001_ha
,
4063 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4064 mpi_ssp_event(pm8001_ha
, piomb
);
4066 case OPC_OUB_DEV_HANDLE_ARRIV
:
4067 PM8001_MSG_DBG(pm8001_ha
,
4068 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4069 /*This is for target*/
4071 case OPC_OUB_SSP_RECV_EVENT
:
4072 PM8001_MSG_DBG(pm8001_ha
,
4073 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4074 /*This is for target*/
4076 case OPC_OUB_DEV_INFO
:
4077 PM8001_MSG_DBG(pm8001_ha
,
4078 pm8001_printk("OPC_OUB_DEV_INFO\n"));
4080 case OPC_OUB_FW_FLASH_UPDATE
:
4081 PM8001_MSG_DBG(pm8001_ha
,
4082 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4083 pm8001_mpi_fw_flash_update_resp(pm8001_ha
, piomb
);
4085 case OPC_OUB_GPIO_RESPONSE
:
4086 PM8001_MSG_DBG(pm8001_ha
,
4087 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4089 case OPC_OUB_GPIO_EVENT
:
4090 PM8001_MSG_DBG(pm8001_ha
,
4091 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4093 case OPC_OUB_GENERAL_EVENT
:
4094 PM8001_MSG_DBG(pm8001_ha
,
4095 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4096 pm8001_mpi_general_event(pm8001_ha
, piomb
);
4098 case OPC_OUB_SSP_ABORT_RSP
:
4099 PM8001_MSG_DBG(pm8001_ha
,
4100 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4101 pm8001_mpi_task_abort_resp(pm8001_ha
, piomb
);
4103 case OPC_OUB_SATA_ABORT_RSP
:
4104 PM8001_MSG_DBG(pm8001_ha
,
4105 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4106 pm8001_mpi_task_abort_resp(pm8001_ha
, piomb
);
4108 case OPC_OUB_SAS_DIAG_MODE_START_END
:
4109 PM8001_MSG_DBG(pm8001_ha
,
4110 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4112 case OPC_OUB_SAS_DIAG_EXECUTE
:
4113 PM8001_MSG_DBG(pm8001_ha
,
4114 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4116 case OPC_OUB_GET_TIME_STAMP
:
4117 PM8001_MSG_DBG(pm8001_ha
,
4118 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4120 case OPC_OUB_SAS_HW_EVENT_ACK
:
4121 PM8001_MSG_DBG(pm8001_ha
,
4122 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4124 case OPC_OUB_PORT_CONTROL
:
4125 PM8001_MSG_DBG(pm8001_ha
,
4126 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4128 case OPC_OUB_SMP_ABORT_RSP
:
4129 PM8001_MSG_DBG(pm8001_ha
,
4130 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4131 pm8001_mpi_task_abort_resp(pm8001_ha
, piomb
);
4133 case OPC_OUB_GET_NVMD_DATA
:
4134 PM8001_MSG_DBG(pm8001_ha
,
4135 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4136 pm8001_mpi_get_nvmd_resp(pm8001_ha
, piomb
);
4138 case OPC_OUB_SET_NVMD_DATA
:
4139 PM8001_MSG_DBG(pm8001_ha
,
4140 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4141 pm8001_mpi_set_nvmd_resp(pm8001_ha
, piomb
);
4143 case OPC_OUB_DEVICE_HANDLE_REMOVAL
:
4144 PM8001_MSG_DBG(pm8001_ha
,
4145 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4147 case OPC_OUB_SET_DEVICE_STATE
:
4148 PM8001_MSG_DBG(pm8001_ha
,
4149 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4150 pm8001_mpi_set_dev_state_resp(pm8001_ha
, piomb
);
4152 case OPC_OUB_GET_DEVICE_STATE
:
4153 PM8001_MSG_DBG(pm8001_ha
,
4154 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4156 case OPC_OUB_SET_DEV_INFO
:
4157 PM8001_MSG_DBG(pm8001_ha
,
4158 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4160 case OPC_OUB_SAS_RE_INITIALIZE
:
4161 PM8001_MSG_DBG(pm8001_ha
,
4162 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4165 PM8001_MSG_DBG(pm8001_ha
,
4166 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4172 static int process_oq(struct pm8001_hba_info
*pm8001_ha
, u8 vec
)
4174 struct outbound_queue_table
*circularQ
;
4176 u8
uninitialized_var(bc
);
4177 u32 ret
= MPI_IO_STATUS_FAIL
;
4178 unsigned long flags
;
4180 spin_lock_irqsave(&pm8001_ha
->lock
, flags
);
4181 circularQ
= &pm8001_ha
->outbnd_q_tbl
[vec
];
4183 ret
= pm8001_mpi_msg_consume(pm8001_ha
, circularQ
, &pMsg1
, &bc
);
4184 if (MPI_IO_STATUS_SUCCESS
== ret
) {
4185 /* process the outbound message */
4186 process_one_iomb(pm8001_ha
, (void *)(pMsg1
- 4));
4187 /* free the message from the outbound circular buffer */
4188 pm8001_mpi_msg_free_set(pm8001_ha
, pMsg1
,
4191 if (MPI_IO_STATUS_BUSY
== ret
) {
4192 /* Update the producer index from SPC */
4193 circularQ
->producer_index
=
4194 cpu_to_le32(pm8001_read_32(circularQ
->pi_virt
));
4195 if (le32_to_cpu(circularQ
->producer_index
) ==
4196 circularQ
->consumer_idx
)
4201 spin_unlock_irqrestore(&pm8001_ha
->lock
, flags
);
4205 /* PCI_DMA_... to our direction translation. */
4206 static const u8 data_dir_flags
[] = {
4207 [PCI_DMA_BIDIRECTIONAL
] = DATA_DIR_BYRECIPIENT
,/* UNSPECIFIED */
4208 [PCI_DMA_TODEVICE
] = DATA_DIR_OUT
,/* OUTBOUND */
4209 [PCI_DMA_FROMDEVICE
] = DATA_DIR_IN
,/* INBOUND */
4210 [PCI_DMA_NONE
] = DATA_DIR_NONE
,/* NO TRANSFER */
4213 pm8001_chip_make_sg(struct scatterlist
*scatter
, int nr
, void *prd
)
4216 struct scatterlist
*sg
;
4217 struct pm8001_prd
*buf_prd
= prd
;
4219 for_each_sg(scatter
, sg
, nr
, i
) {
4220 buf_prd
->addr
= cpu_to_le64(sg_dma_address(sg
));
4221 buf_prd
->im_len
.len
= cpu_to_le32(sg_dma_len(sg
));
4222 buf_prd
->im_len
.e
= 0;
4227 static void build_smp_cmd(u32 deviceID
, __le32 hTag
, struct smp_req
*psmp_cmd
)
4229 psmp_cmd
->tag
= hTag
;
4230 psmp_cmd
->device_id
= cpu_to_le32(deviceID
);
4231 psmp_cmd
->len_ip_ir
= cpu_to_le32(1|(1 << 1));
4235 * pm8001_chip_smp_req - send a SMP task to FW
4236 * @pm8001_ha: our hba card information.
4237 * @ccb: the ccb information this request used.
4239 static int pm8001_chip_smp_req(struct pm8001_hba_info
*pm8001_ha
,
4240 struct pm8001_ccb_info
*ccb
)
4243 struct sas_task
*task
= ccb
->task
;
4244 struct domain_device
*dev
= task
->dev
;
4245 struct pm8001_device
*pm8001_dev
= dev
->lldd_dev
;
4246 struct scatterlist
*sg_req
, *sg_resp
;
4247 u32 req_len
, resp_len
;
4248 struct smp_req smp_cmd
;
4250 struct inbound_queue_table
*circularQ
;
4252 memset(&smp_cmd
, 0, sizeof(smp_cmd
));
4254 * DMA-map SMP request, response buffers
4256 sg_req
= &task
->smp_task
.smp_req
;
4257 elem
= dma_map_sg(pm8001_ha
->dev
, sg_req
, 1, PCI_DMA_TODEVICE
);
4260 req_len
= sg_dma_len(sg_req
);
4262 sg_resp
= &task
->smp_task
.smp_resp
;
4263 elem
= dma_map_sg(pm8001_ha
->dev
, sg_resp
, 1, PCI_DMA_FROMDEVICE
);
4268 resp_len
= sg_dma_len(sg_resp
);
4269 /* must be in dwords */
4270 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
4275 opc
= OPC_INB_SMP_REQUEST
;
4276 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4277 smp_cmd
.tag
= cpu_to_le32(ccb
->ccb_tag
);
4278 smp_cmd
.long_smp_req
.long_req_addr
=
4279 cpu_to_le64((u64
)sg_dma_address(&task
->smp_task
.smp_req
));
4280 smp_cmd
.long_smp_req
.long_req_size
=
4281 cpu_to_le32((u32
)sg_dma_len(&task
->smp_task
.smp_req
)-4);
4282 smp_cmd
.long_smp_req
.long_resp_addr
=
4283 cpu_to_le64((u64
)sg_dma_address(&task
->smp_task
.smp_resp
));
4284 smp_cmd
.long_smp_req
.long_resp_size
=
4285 cpu_to_le32((u32
)sg_dma_len(&task
->smp_task
.smp_resp
)-4);
4286 build_smp_cmd(pm8001_dev
->device_id
, smp_cmd
.tag
, &smp_cmd
);
4287 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
,
4288 (u32
*)&smp_cmd
, 0);
4295 dma_unmap_sg(pm8001_ha
->dev
, &ccb
->task
->smp_task
.smp_resp
, 1,
4296 PCI_DMA_FROMDEVICE
);
4298 dma_unmap_sg(pm8001_ha
->dev
, &ccb
->task
->smp_task
.smp_req
, 1,
4304 * pm8001_chip_ssp_io_req - send a SSP task to FW
4305 * @pm8001_ha: our hba card information.
4306 * @ccb: the ccb information this request used.
4308 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info
*pm8001_ha
,
4309 struct pm8001_ccb_info
*ccb
)
4311 struct sas_task
*task
= ccb
->task
;
4312 struct domain_device
*dev
= task
->dev
;
4313 struct pm8001_device
*pm8001_dev
= dev
->lldd_dev
;
4314 struct ssp_ini_io_start_req ssp_cmd
;
4315 u32 tag
= ccb
->ccb_tag
;
4318 struct inbound_queue_table
*circularQ
;
4319 u32 opc
= OPC_INB_SSPINIIOSTART
;
4320 memset(&ssp_cmd
, 0, sizeof(ssp_cmd
));
4321 memcpy(ssp_cmd
.ssp_iu
.lun
, task
->ssp_task
.LUN
, 8);
4323 cpu_to_le32(data_dir_flags
[task
->data_dir
] << 8 | 0x0);/*0 for
4324 SAS 1.1 compatible TLR*/
4325 ssp_cmd
.data_len
= cpu_to_le32(task
->total_xfer_len
);
4326 ssp_cmd
.device_id
= cpu_to_le32(pm8001_dev
->device_id
);
4327 ssp_cmd
.tag
= cpu_to_le32(tag
);
4328 if (task
->ssp_task
.enable_first_burst
)
4329 ssp_cmd
.ssp_iu
.efb_prio_attr
|= 0x80;
4330 ssp_cmd
.ssp_iu
.efb_prio_attr
|= (task
->ssp_task
.task_prio
<< 3);
4331 ssp_cmd
.ssp_iu
.efb_prio_attr
|= (task
->ssp_task
.task_attr
& 7);
4332 memcpy(ssp_cmd
.ssp_iu
.cdb
, task
->ssp_task
.cmd
->cmnd
,
4333 task
->ssp_task
.cmd
->cmd_len
);
4334 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4336 /* fill in PRD (scatter/gather) table, if any */
4337 if (task
->num_scatter
> 1) {
4338 pm8001_chip_make_sg(task
->scatter
, ccb
->n_elem
, ccb
->buf_prd
);
4339 phys_addr
= ccb
->ccb_dma_handle
+
4340 offsetof(struct pm8001_ccb_info
, buf_prd
[0]);
4341 ssp_cmd
.addr_low
= cpu_to_le32(lower_32_bits(phys_addr
));
4342 ssp_cmd
.addr_high
= cpu_to_le32(upper_32_bits(phys_addr
));
4343 ssp_cmd
.esgl
= cpu_to_le32(1<<31);
4344 } else if (task
->num_scatter
== 1) {
4345 u64 dma_addr
= sg_dma_address(task
->scatter
);
4346 ssp_cmd
.addr_low
= cpu_to_le32(lower_32_bits(dma_addr
));
4347 ssp_cmd
.addr_high
= cpu_to_le32(upper_32_bits(dma_addr
));
4348 ssp_cmd
.len
= cpu_to_le32(task
->total_xfer_len
);
4350 } else if (task
->num_scatter
== 0) {
4351 ssp_cmd
.addr_low
= 0;
4352 ssp_cmd
.addr_high
= 0;
4353 ssp_cmd
.len
= cpu_to_le32(task
->total_xfer_len
);
4356 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &ssp_cmd
, 0);
4360 static int pm8001_chip_sata_req(struct pm8001_hba_info
*pm8001_ha
,
4361 struct pm8001_ccb_info
*ccb
)
4363 struct sas_task
*task
= ccb
->task
;
4364 struct domain_device
*dev
= task
->dev
;
4365 struct pm8001_device
*pm8001_ha_dev
= dev
->lldd_dev
;
4366 u32 tag
= ccb
->ccb_tag
;
4368 struct sata_start_req sata_cmd
;
4369 u32 hdr_tag
, ncg_tag
= 0;
4373 struct inbound_queue_table
*circularQ
;
4374 unsigned long flags
;
4375 u32 opc
= OPC_INB_SATA_HOST_OPSTART
;
4376 memset(&sata_cmd
, 0, sizeof(sata_cmd
));
4377 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4378 if (task
->data_dir
== PCI_DMA_NONE
) {
4379 ATAP
= 0x04; /* no data*/
4380 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("no data\n"));
4381 } else if (likely(!task
->ata_task
.device_control_reg_update
)) {
4382 if (task
->ata_task
.dma_xfer
) {
4383 ATAP
= 0x06; /* DMA */
4384 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("DMA\n"));
4386 ATAP
= 0x05; /* PIO*/
4387 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("PIO\n"));
4389 if (task
->ata_task
.use_ncq
&&
4390 dev
->sata_dev
.class != ATA_DEV_ATAPI
) {
4391 ATAP
= 0x07; /* FPDMA */
4392 PM8001_IO_DBG(pm8001_ha
, pm8001_printk("FPDMA\n"));
4395 if (task
->ata_task
.use_ncq
&& pm8001_get_ncq_tag(task
, &hdr_tag
)) {
4396 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
4399 dir
= data_dir_flags
[task
->data_dir
] << 8;
4400 sata_cmd
.tag
= cpu_to_le32(tag
);
4401 sata_cmd
.device_id
= cpu_to_le32(pm8001_ha_dev
->device_id
);
4402 sata_cmd
.data_len
= cpu_to_le32(task
->total_xfer_len
);
4403 sata_cmd
.ncqtag_atap_dir_m
=
4404 cpu_to_le32(((ncg_tag
& 0xff)<<16)|((ATAP
& 0x3f) << 10) | dir
);
4405 sata_cmd
.sata_fis
= task
->ata_task
.fis
;
4406 if (likely(!task
->ata_task
.device_control_reg_update
))
4407 sata_cmd
.sata_fis
.flags
|= 0x80;/* C=1: update ATA cmd reg */
4408 sata_cmd
.sata_fis
.flags
&= 0xF0;/* PM_PORT field shall be 0 */
4409 /* fill in PRD (scatter/gather) table, if any */
4410 if (task
->num_scatter
> 1) {
4411 pm8001_chip_make_sg(task
->scatter
, ccb
->n_elem
, ccb
->buf_prd
);
4412 phys_addr
= ccb
->ccb_dma_handle
+
4413 offsetof(struct pm8001_ccb_info
, buf_prd
[0]);
4414 sata_cmd
.addr_low
= lower_32_bits(phys_addr
);
4415 sata_cmd
.addr_high
= upper_32_bits(phys_addr
);
4416 sata_cmd
.esgl
= cpu_to_le32(1 << 31);
4417 } else if (task
->num_scatter
== 1) {
4418 u64 dma_addr
= sg_dma_address(task
->scatter
);
4419 sata_cmd
.addr_low
= lower_32_bits(dma_addr
);
4420 sata_cmd
.addr_high
= upper_32_bits(dma_addr
);
4421 sata_cmd
.len
= cpu_to_le32(task
->total_xfer_len
);
4423 } else if (task
->num_scatter
== 0) {
4424 sata_cmd
.addr_low
= 0;
4425 sata_cmd
.addr_high
= 0;
4426 sata_cmd
.len
= cpu_to_le32(task
->total_xfer_len
);
4430 /* Check for read log for failed drive and return */
4431 if (sata_cmd
.sata_fis
.command
== 0x2f) {
4432 if (((pm8001_ha_dev
->id
& NCQ_READ_LOG_FLAG
) ||
4433 (pm8001_ha_dev
->id
& NCQ_ABORT_ALL_FLAG
) ||
4434 (pm8001_ha_dev
->id
& NCQ_2ND_RLE_FLAG
))) {
4435 struct task_status_struct
*ts
;
4437 pm8001_ha_dev
->id
&= 0xDFFFFFFF;
4438 ts
= &task
->task_status
;
4440 spin_lock_irqsave(&task
->task_state_lock
, flags
);
4441 ts
->resp
= SAS_TASK_COMPLETE
;
4442 ts
->stat
= SAM_STAT_GOOD
;
4443 task
->task_state_flags
&= ~SAS_TASK_STATE_PENDING
;
4444 task
->task_state_flags
&= ~SAS_TASK_AT_INITIATOR
;
4445 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
4446 if (unlikely((task
->task_state_flags
&
4447 SAS_TASK_STATE_ABORTED
))) {
4448 spin_unlock_irqrestore(&task
->task_state_lock
,
4450 PM8001_FAIL_DBG(pm8001_ha
,
4451 pm8001_printk("task 0x%p resp 0x%x "
4452 " stat 0x%x but aborted by upper layer "
4453 "\n", task
, ts
->resp
, ts
->stat
));
4454 pm8001_ccb_task_free(pm8001_ha
, task
, ccb
, tag
);
4456 spin_unlock_irqrestore(&task
->task_state_lock
,
4458 pm8001_ccb_task_free_done(pm8001_ha
, task
,
4465 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &sata_cmd
, 0);
4470 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4471 * @pm8001_ha: our hba card information.
4472 * @num: the inbound queue number
4473 * @phy_id: the phy id which we wanted to start up.
4476 pm8001_chip_phy_start_req(struct pm8001_hba_info
*pm8001_ha
, u8 phy_id
)
4478 struct phy_start_req payload
;
4479 struct inbound_queue_table
*circularQ
;
4482 u32 opcode
= OPC_INB_PHYSTART
;
4483 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4484 memset(&payload
, 0, sizeof(payload
));
4485 payload
.tag
= cpu_to_le32(tag
);
4487 ** [0:7] PHY Identifier
4488 ** [8:11] link rate 1.5G, 3G, 6G
4489 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4490 ** [14] 0b disable spin up hold; 1b enable spin up hold
4492 payload
.ase_sh_lm_slr_phyid
= cpu_to_le32(SPINHOLD_DISABLE
|
4493 LINKMODE_AUTO
| LINKRATE_15
|
4494 LINKRATE_30
| LINKRATE_60
| phy_id
);
4495 payload
.sas_identify
.dev_type
= SAS_END_DEVICE
;
4496 payload
.sas_identify
.initiator_bits
= SAS_PROTOCOL_ALL
;
4497 memcpy(payload
.sas_identify
.sas_addr
,
4498 pm8001_ha
->sas_addr
, SAS_ADDR_SIZE
);
4499 payload
.sas_identify
.phy_id
= phy_id
;
4500 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opcode
, &payload
, 0);
4505 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4506 * @pm8001_ha: our hba card information.
4507 * @num: the inbound queue number
4508 * @phy_id: the phy id which we wanted to start up.
4510 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info
*pm8001_ha
,
4513 struct phy_stop_req payload
;
4514 struct inbound_queue_table
*circularQ
;
4517 u32 opcode
= OPC_INB_PHYSTOP
;
4518 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4519 memset(&payload
, 0, sizeof(payload
));
4520 payload
.tag
= cpu_to_le32(tag
);
4521 payload
.phy_id
= cpu_to_le32(phy_id
);
4522 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opcode
, &payload
, 0);
4527 * see comments on pm8001_mpi_reg_resp.
4529 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info
*pm8001_ha
,
4530 struct pm8001_device
*pm8001_dev
, u32 flag
)
4532 struct reg_dev_req payload
;
4534 u32 stp_sspsmp_sata
= 0x4;
4535 struct inbound_queue_table
*circularQ
;
4536 u32 linkrate
, phy_id
;
4537 int rc
, tag
= 0xdeadbeef;
4538 struct pm8001_ccb_info
*ccb
;
4540 u16 firstBurstSize
= 0;
4542 struct domain_device
*dev
= pm8001_dev
->sas_device
;
4543 struct domain_device
*parent_dev
= dev
->parent
;
4544 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4546 memset(&payload
, 0, sizeof(payload
));
4547 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
4550 ccb
= &pm8001_ha
->ccb_info
[tag
];
4551 ccb
->device
= pm8001_dev
;
4553 payload
.tag
= cpu_to_le32(tag
);
4555 stp_sspsmp_sata
= 0x02; /*direct attached sata */
4557 if (pm8001_dev
->dev_type
== SAS_SATA_DEV
)
4558 stp_sspsmp_sata
= 0x00; /* stp*/
4559 else if (pm8001_dev
->dev_type
== SAS_END_DEVICE
||
4560 pm8001_dev
->dev_type
== SAS_EDGE_EXPANDER_DEVICE
||
4561 pm8001_dev
->dev_type
== SAS_FANOUT_EXPANDER_DEVICE
)
4562 stp_sspsmp_sata
= 0x01; /*ssp or smp*/
4564 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
4565 phy_id
= parent_dev
->ex_dev
.ex_phy
->phy_id
;
4567 phy_id
= pm8001_dev
->attached_phy
;
4568 opc
= OPC_INB_REG_DEV
;
4569 linkrate
= (pm8001_dev
->sas_device
->linkrate
< dev
->port
->linkrate
) ?
4570 pm8001_dev
->sas_device
->linkrate
: dev
->port
->linkrate
;
4571 payload
.phyid_portid
=
4572 cpu_to_le32(((pm8001_dev
->sas_device
->port
->id
) & 0x0F) |
4573 ((phy_id
& 0x0F) << 4));
4574 payload
.dtype_dlr_retry
= cpu_to_le32((retryFlag
& 0x01) |
4575 ((linkrate
& 0x0F) * 0x1000000) |
4576 ((stp_sspsmp_sata
& 0x03) * 0x10000000));
4577 payload
.firstburstsize_ITNexustimeout
=
4578 cpu_to_le32(ITNT
| (firstBurstSize
* 0x10000));
4579 memcpy(payload
.sas_addr
, pm8001_dev
->sas_device
->sas_addr
,
4581 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
4586 * see comments on pm8001_mpi_reg_resp.
4588 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info
*pm8001_ha
,
4591 struct dereg_dev_req payload
;
4592 u32 opc
= OPC_INB_DEREG_DEV_HANDLE
;
4594 struct inbound_queue_table
*circularQ
;
4596 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4597 memset(&payload
, 0, sizeof(payload
));
4598 payload
.tag
= cpu_to_le32(1);
4599 payload
.device_id
= cpu_to_le32(device_id
);
4600 PM8001_MSG_DBG(pm8001_ha
,
4601 pm8001_printk("unregister device device_id = %d\n", device_id
));
4602 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
4607 * pm8001_chip_phy_ctl_req - support the local phy operation
4608 * @pm8001_ha: our hba card information.
4609 * @num: the inbound queue number
4610 * @phy_id: the phy id which we wanted to operate
4613 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info
*pm8001_ha
,
4614 u32 phyId
, u32 phy_op
)
4616 struct local_phy_ctl_req payload
;
4617 struct inbound_queue_table
*circularQ
;
4619 u32 opc
= OPC_INB_LOCAL_PHY_CONTROL
;
4620 memset(&payload
, 0, sizeof(payload
));
4621 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4622 payload
.tag
= cpu_to_le32(1);
4623 payload
.phyop_phyid
=
4624 cpu_to_le32(((phy_op
& 0xff) << 8) | (phyId
& 0x0F));
4625 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
4629 static u32
pm8001_chip_is_our_interupt(struct pm8001_hba_info
*pm8001_ha
)
4632 #ifdef PM8001_USE_MSIX
4635 value
= pm8001_cr32(pm8001_ha
, 0, MSGU_ODR
);
4643 * pm8001_chip_isr - PM8001 isr handler.
4644 * @pm8001_ha: our hba card information.
4649 pm8001_chip_isr(struct pm8001_hba_info
*pm8001_ha
, u8 vec
)
4651 pm8001_chip_interrupt_disable(pm8001_ha
, vec
);
4652 process_oq(pm8001_ha
, vec
);
4653 pm8001_chip_interrupt_enable(pm8001_ha
, vec
);
4657 static int send_task_abort(struct pm8001_hba_info
*pm8001_ha
, u32 opc
,
4658 u32 dev_id
, u8 flag
, u32 task_tag
, u32 cmd_tag
)
4660 struct task_abort_req task_abort
;
4661 struct inbound_queue_table
*circularQ
;
4663 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4664 memset(&task_abort
, 0, sizeof(task_abort
));
4665 if (ABORT_SINGLE
== (flag
& ABORT_MASK
)) {
4666 task_abort
.abort_all
= 0;
4667 task_abort
.device_id
= cpu_to_le32(dev_id
);
4668 task_abort
.tag_to_abort
= cpu_to_le32(task_tag
);
4669 task_abort
.tag
= cpu_to_le32(cmd_tag
);
4670 } else if (ABORT_ALL
== (flag
& ABORT_MASK
)) {
4671 task_abort
.abort_all
= cpu_to_le32(1);
4672 task_abort
.device_id
= cpu_to_le32(dev_id
);
4673 task_abort
.tag
= cpu_to_le32(cmd_tag
);
4675 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &task_abort
, 0);
4680 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4681 * @task: the task we wanted to aborted.
4682 * @flag: the abort flag.
4684 int pm8001_chip_abort_task(struct pm8001_hba_info
*pm8001_ha
,
4685 struct pm8001_device
*pm8001_dev
, u8 flag
, u32 task_tag
, u32 cmd_tag
)
4688 int rc
= TMF_RESP_FUNC_FAILED
;
4689 PM8001_EH_DBG(pm8001_ha
,
4690 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4691 cmd_tag
, task_tag
));
4692 if (pm8001_dev
->dev_type
== SAS_END_DEVICE
)
4693 opc
= OPC_INB_SSP_ABORT
;
4694 else if (pm8001_dev
->dev_type
== SAS_SATA_DEV
)
4695 opc
= OPC_INB_SATA_ABORT
;
4697 opc
= OPC_INB_SMP_ABORT
;/* SMP */
4698 device_id
= pm8001_dev
->device_id
;
4699 rc
= send_task_abort(pm8001_ha
, opc
, device_id
, flag
,
4701 if (rc
!= TMF_RESP_FUNC_COMPLETE
)
4702 PM8001_EH_DBG(pm8001_ha
, pm8001_printk("rc= %d\n", rc
));
4707 * pm8001_chip_ssp_tm_req - built the task management command.
4708 * @pm8001_ha: our hba card information.
4709 * @ccb: the ccb information.
4710 * @tmf: task management function.
4712 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info
*pm8001_ha
,
4713 struct pm8001_ccb_info
*ccb
, struct pm8001_tmf_task
*tmf
)
4715 struct sas_task
*task
= ccb
->task
;
4716 struct domain_device
*dev
= task
->dev
;
4717 struct pm8001_device
*pm8001_dev
= dev
->lldd_dev
;
4718 u32 opc
= OPC_INB_SSPINITMSTART
;
4719 struct inbound_queue_table
*circularQ
;
4720 struct ssp_ini_tm_start_req sspTMCmd
;
4723 memset(&sspTMCmd
, 0, sizeof(sspTMCmd
));
4724 sspTMCmd
.device_id
= cpu_to_le32(pm8001_dev
->device_id
);
4725 sspTMCmd
.relate_tag
= cpu_to_le32(tmf
->tag_of_task_to_be_managed
);
4726 sspTMCmd
.tmf
= cpu_to_le32(tmf
->tmf
);
4727 memcpy(sspTMCmd
.lun
, task
->ssp_task
.LUN
, 8);
4728 sspTMCmd
.tag
= cpu_to_le32(ccb
->ccb_tag
);
4729 if (pm8001_ha
->chip_id
!= chip_8001
)
4730 sspTMCmd
.ds_ads_m
= 0x08;
4731 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4732 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &sspTMCmd
, 0);
4736 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info
*pm8001_ha
,
4739 u32 opc
= OPC_INB_GET_NVMD_DATA
;
4743 struct pm8001_ccb_info
*ccb
;
4744 struct inbound_queue_table
*circularQ
;
4745 struct get_nvm_data_req nvmd_req
;
4746 struct fw_control_ex
*fw_control_context
;
4747 struct pm8001_ioctl_payload
*ioctl_payload
= payload
;
4749 nvmd_type
= ioctl_payload
->minor_function
;
4750 fw_control_context
= kzalloc(sizeof(struct fw_control_ex
), GFP_KERNEL
);
4751 if (!fw_control_context
)
4753 fw_control_context
->usrAddr
= (u8
*)ioctl_payload
->func_specific
;
4754 fw_control_context
->len
= ioctl_payload
->length
;
4755 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4756 memset(&nvmd_req
, 0, sizeof(nvmd_req
));
4757 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
4759 kfree(fw_control_context
);
4762 ccb
= &pm8001_ha
->ccb_info
[tag
];
4764 ccb
->fw_control_context
= fw_control_context
;
4765 nvmd_req
.tag
= cpu_to_le32(tag
);
4767 switch (nvmd_type
) {
4769 u32 twi_addr
, twi_page_size
;
4773 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| twi_addr
<< 16 |
4774 twi_page_size
<< 8 | TWI_DEVICE
);
4775 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4776 nvmd_req
.resp_addr_hi
=
4777 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4778 nvmd_req
.resp_addr_lo
=
4779 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4783 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| C_SEEPROM
);
4784 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4785 nvmd_req
.resp_addr_hi
=
4786 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4787 nvmd_req
.resp_addr_lo
=
4788 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4792 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| VPD_FLASH
);
4793 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4794 nvmd_req
.resp_addr_hi
=
4795 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4796 nvmd_req
.resp_addr_lo
=
4797 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4801 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| EXPAN_ROM
);
4802 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4803 nvmd_req
.resp_addr_hi
=
4804 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4805 nvmd_req
.resp_addr_lo
=
4806 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4810 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| IOP_RDUMP
);
4811 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4812 nvmd_req
.vpd_offset
= cpu_to_le32(ioctl_payload
->offset
);
4813 nvmd_req
.resp_addr_hi
=
4814 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4815 nvmd_req
.resp_addr_lo
=
4816 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4822 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &nvmd_req
, 0);
4824 kfree(fw_control_context
);
4825 pm8001_tag_free(pm8001_ha
, tag
);
4830 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info
*pm8001_ha
,
4833 u32 opc
= OPC_INB_SET_NVMD_DATA
;
4837 struct pm8001_ccb_info
*ccb
;
4838 struct inbound_queue_table
*circularQ
;
4839 struct set_nvm_data_req nvmd_req
;
4840 struct fw_control_ex
*fw_control_context
;
4841 struct pm8001_ioctl_payload
*ioctl_payload
= payload
;
4843 nvmd_type
= ioctl_payload
->minor_function
;
4844 fw_control_context
= kzalloc(sizeof(struct fw_control_ex
), GFP_KERNEL
);
4845 if (!fw_control_context
)
4847 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4848 memcpy(pm8001_ha
->memoryMap
.region
[NVMD
].virt_ptr
,
4849 &ioctl_payload
->func_specific
,
4850 ioctl_payload
->length
);
4851 memset(&nvmd_req
, 0, sizeof(nvmd_req
));
4852 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
4854 kfree(fw_control_context
);
4857 ccb
= &pm8001_ha
->ccb_info
[tag
];
4858 ccb
->fw_control_context
= fw_control_context
;
4860 nvmd_req
.tag
= cpu_to_le32(tag
);
4861 switch (nvmd_type
) {
4863 u32 twi_addr
, twi_page_size
;
4866 nvmd_req
.reserved
[0] = cpu_to_le32(0xFEDCBA98);
4867 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| twi_addr
<< 16 |
4868 twi_page_size
<< 8 | TWI_DEVICE
);
4869 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4870 nvmd_req
.resp_addr_hi
=
4871 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4872 nvmd_req
.resp_addr_lo
=
4873 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4877 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| C_SEEPROM
);
4878 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4879 nvmd_req
.reserved
[0] = cpu_to_le32(0xFEDCBA98);
4880 nvmd_req
.resp_addr_hi
=
4881 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4882 nvmd_req
.resp_addr_lo
=
4883 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4886 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| VPD_FLASH
);
4887 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4888 nvmd_req
.reserved
[0] = cpu_to_le32(0xFEDCBA98);
4889 nvmd_req
.resp_addr_hi
=
4890 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4891 nvmd_req
.resp_addr_lo
=
4892 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4895 nvmd_req
.len_ir_vpdd
= cpu_to_le32(IPMode
| EXPAN_ROM
);
4896 nvmd_req
.resp_len
= cpu_to_le32(ioctl_payload
->length
);
4897 nvmd_req
.reserved
[0] = cpu_to_le32(0xFEDCBA98);
4898 nvmd_req
.resp_addr_hi
=
4899 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_hi
);
4900 nvmd_req
.resp_addr_lo
=
4901 cpu_to_le32(pm8001_ha
->memoryMap
.region
[NVMD
].phys_addr_lo
);
4906 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &nvmd_req
, 0);
4908 kfree(fw_control_context
);
4909 pm8001_tag_free(pm8001_ha
, tag
);
4915 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4916 * @pm8001_ha: our hba card information.
4917 * @fw_flash_updata_info: firmware flash update param
4920 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info
*pm8001_ha
,
4921 void *fw_flash_updata_info
, u32 tag
)
4923 struct fw_flash_Update_req payload
;
4924 struct fw_flash_updata_info
*info
;
4925 struct inbound_queue_table
*circularQ
;
4927 u32 opc
= OPC_INB_FW_FLASH_UPDATE
;
4929 memset(&payload
, 0, sizeof(struct fw_flash_Update_req
));
4930 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
4931 info
= fw_flash_updata_info
;
4932 payload
.tag
= cpu_to_le32(tag
);
4933 payload
.cur_image_len
= cpu_to_le32(info
->cur_image_len
);
4934 payload
.cur_image_offset
= cpu_to_le32(info
->cur_image_offset
);
4935 payload
.total_image_len
= cpu_to_le32(info
->total_image_len
);
4936 payload
.len
= info
->sgl
.im_len
.len
;
4937 payload
.sgl_addr_lo
=
4938 cpu_to_le32(lower_32_bits(le64_to_cpu(info
->sgl
.addr
)));
4939 payload
.sgl_addr_hi
=
4940 cpu_to_le32(upper_32_bits(le64_to_cpu(info
->sgl
.addr
)));
4941 ret
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
4946 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info
*pm8001_ha
,
4949 struct fw_flash_updata_info flash_update_info
;
4950 struct fw_control_info
*fw_control
;
4951 struct fw_control_ex
*fw_control_context
;
4954 struct pm8001_ccb_info
*ccb
;
4955 void *buffer
= pm8001_ha
->memoryMap
.region
[FW_FLASH
].virt_ptr
;
4956 dma_addr_t phys_addr
= pm8001_ha
->memoryMap
.region
[FW_FLASH
].phys_addr
;
4957 struct pm8001_ioctl_payload
*ioctl_payload
= payload
;
4959 fw_control_context
= kzalloc(sizeof(struct fw_control_ex
), GFP_KERNEL
);
4960 if (!fw_control_context
)
4962 fw_control
= (struct fw_control_info
*)&ioctl_payload
->func_specific
;
4963 memcpy(buffer
, fw_control
->buffer
, fw_control
->len
);
4964 flash_update_info
.sgl
.addr
= cpu_to_le64(phys_addr
);
4965 flash_update_info
.sgl
.im_len
.len
= cpu_to_le32(fw_control
->len
);
4966 flash_update_info
.sgl
.im_len
.e
= 0;
4967 flash_update_info
.cur_image_offset
= fw_control
->offset
;
4968 flash_update_info
.cur_image_len
= fw_control
->len
;
4969 flash_update_info
.total_image_len
= fw_control
->size
;
4970 fw_control_context
->fw_control
= fw_control
;
4971 fw_control_context
->virtAddr
= buffer
;
4972 fw_control_context
->phys_addr
= phys_addr
;
4973 fw_control_context
->len
= fw_control
->len
;
4974 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
4976 kfree(fw_control_context
);
4979 ccb
= &pm8001_ha
->ccb_info
[tag
];
4980 ccb
->fw_control_context
= fw_control_context
;
4982 rc
= pm8001_chip_fw_flash_update_build(pm8001_ha
, &flash_update_info
,
4988 pm8001_get_gsm_dump(struct device
*cdev
, u32 length
, char *buf
)
4990 u32 value
, rem
, offset
= 0, bar
= 0;
4991 u32 index
, work_offset
, dw_length
;
4992 u32 shift_value
, gsm_base
, gsm_dump_offset
;
4994 struct Scsi_Host
*shost
= class_to_shost(cdev
);
4995 struct sas_ha_struct
*sha
= SHOST_TO_SAS_HA(shost
);
4996 struct pm8001_hba_info
*pm8001_ha
= sha
->lldd_ha
;
4999 gsm_dump_offset
= pm8001_ha
->fatal_forensic_shift_offset
;
5001 /* check max is 1 Mbytes */
5002 if ((length
> 0x100000) || (gsm_dump_offset
& 3) ||
5003 ((gsm_dump_offset
+ length
) > 0x1000000))
5006 if (pm8001_ha
->chip_id
== chip_8001
)
5011 work_offset
= gsm_dump_offset
& 0xFFFF0000;
5012 offset
= gsm_dump_offset
& 0x0000FFFF;
5013 gsm_dump_offset
= work_offset
;
5014 /* adjust length to dword boundary */
5016 dw_length
= length
>> 2;
5018 for (index
= 0; index
< dw_length
; index
++) {
5019 if ((work_offset
+ offset
) & 0xFFFF0000) {
5020 if (pm8001_ha
->chip_id
== chip_8001
)
5021 shift_value
= ((gsm_dump_offset
+ offset
) &
5022 SHIFT_REG_64K_MASK
);
5024 shift_value
= (((gsm_dump_offset
+ offset
) &
5025 SHIFT_REG_64K_MASK
) >>
5026 SHIFT_REG_BIT_SHIFT
);
5028 if (pm8001_ha
->chip_id
== chip_8001
) {
5029 gsm_base
= GSM_BASE
;
5030 if (-1 == pm8001_bar4_shift(pm8001_ha
,
5031 (gsm_base
+ shift_value
)))
5035 if (-1 == pm80xx_bar4_shift(pm8001_ha
,
5036 (gsm_base
+ shift_value
)))
5039 gsm_dump_offset
= (gsm_dump_offset
+ offset
) &
5042 offset
= offset
& 0x0000FFFF;
5044 value
= pm8001_cr32(pm8001_ha
, bar
, (work_offset
+ offset
) &
5046 direct_data
+= sprintf(direct_data
, "%08x ", value
);
5050 value
= pm8001_cr32(pm8001_ha
, bar
, (work_offset
+ offset
) &
5052 /* xfr for non_dw */
5053 direct_data
+= sprintf(direct_data
, "%08x ", value
);
5055 /* Shift back to BAR4 original address */
5056 if (-1 == pm8001_bar4_shift(pm8001_ha
, 0))
5058 pm8001_ha
->fatal_forensic_shift_offset
+= 1024;
5060 if (pm8001_ha
->fatal_forensic_shift_offset
>= 0x100000)
5061 pm8001_ha
->fatal_forensic_shift_offset
= 0;
5062 return direct_data
- buf
;
5066 pm8001_chip_set_dev_state_req(struct pm8001_hba_info
*pm8001_ha
,
5067 struct pm8001_device
*pm8001_dev
, u32 state
)
5069 struct set_dev_state_req payload
;
5070 struct inbound_queue_table
*circularQ
;
5071 struct pm8001_ccb_info
*ccb
;
5074 u32 opc
= OPC_INB_SET_DEVICE_STATE
;
5075 memset(&payload
, 0, sizeof(payload
));
5076 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
5079 ccb
= &pm8001_ha
->ccb_info
[tag
];
5081 ccb
->device
= pm8001_dev
;
5082 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
5083 payload
.tag
= cpu_to_le32(tag
);
5084 payload
.device_id
= cpu_to_le32(pm8001_dev
->device_id
);
5085 payload
.nds
= cpu_to_le32(state
);
5086 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
5092 pm8001_chip_sas_re_initialization(struct pm8001_hba_info
*pm8001_ha
)
5094 struct sas_re_initialization_req payload
;
5095 struct inbound_queue_table
*circularQ
;
5096 struct pm8001_ccb_info
*ccb
;
5099 u32 opc
= OPC_INB_SAS_RE_INITIALIZE
;
5100 memset(&payload
, 0, sizeof(payload
));
5101 rc
= pm8001_tag_alloc(pm8001_ha
, &tag
);
5104 ccb
= &pm8001_ha
->ccb_info
[tag
];
5106 circularQ
= &pm8001_ha
->inbnd_q_tbl
[0];
5107 payload
.tag
= cpu_to_le32(tag
);
5108 payload
.SSAHOLT
= cpu_to_le32(0xd << 25);
5109 payload
.sata_hol_tmo
= cpu_to_le32(80);
5110 payload
.open_reject_cmdretries_data_retries
= cpu_to_le32(0xff00ff);
5111 rc
= pm8001_mpi_build_cmd(pm8001_ha
, circularQ
, opc
, &payload
, 0);
5113 pm8001_tag_free(pm8001_ha
, tag
);
5118 const struct pm8001_dispatch pm8001_8001_dispatch
= {
5120 .chip_init
= pm8001_chip_init
,
5121 .chip_soft_rst
= pm8001_chip_soft_rst
,
5122 .chip_rst
= pm8001_hw_chip_rst
,
5123 .chip_iounmap
= pm8001_chip_iounmap
,
5124 .isr
= pm8001_chip_isr
,
5125 .is_our_interupt
= pm8001_chip_is_our_interupt
,
5126 .isr_process_oq
= process_oq
,
5127 .interrupt_enable
= pm8001_chip_interrupt_enable
,
5128 .interrupt_disable
= pm8001_chip_interrupt_disable
,
5129 .make_prd
= pm8001_chip_make_sg
,
5130 .smp_req
= pm8001_chip_smp_req
,
5131 .ssp_io_req
= pm8001_chip_ssp_io_req
,
5132 .sata_req
= pm8001_chip_sata_req
,
5133 .phy_start_req
= pm8001_chip_phy_start_req
,
5134 .phy_stop_req
= pm8001_chip_phy_stop_req
,
5135 .reg_dev_req
= pm8001_chip_reg_dev_req
,
5136 .dereg_dev_req
= pm8001_chip_dereg_dev_req
,
5137 .phy_ctl_req
= pm8001_chip_phy_ctl_req
,
5138 .task_abort
= pm8001_chip_abort_task
,
5139 .ssp_tm_req
= pm8001_chip_ssp_tm_req
,
5140 .get_nvmd_req
= pm8001_chip_get_nvmd_req
,
5141 .set_nvmd_req
= pm8001_chip_set_nvmd_req
,
5142 .fw_flash_update_req
= pm8001_chip_fw_flash_update_req
,
5143 .set_dev_state_req
= pm8001_chip_set_dev_state_req
,
5144 .sas_re_init_req
= pm8001_chip_sas_re_initialization
,