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Linux 4.19.133
[linux/fpc-iii.git] / drivers / soc / tegra / pmc.c
blobf17a678154047ed2fc935d8e96ce7ef9e31a6dac
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
21
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/iopoll.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_clk.h>
35 #include <linux/of_platform.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_domain.h>
38 #include <linux/reboot.h>
39 #include <linux/reset.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43
44 #include <soc/tegra/common.h>
45 #include <soc/tegra/fuse.h>
46 #include <soc/tegra/pmc.h>
47
48 #define PMC_CNTRL 0x0
49 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
50 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
51 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
52 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
53 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
54 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
55 #define PMC_CNTRL_MAIN_RST BIT(4)
56
57 #define DPD_SAMPLE 0x020
58 #define DPD_SAMPLE_ENABLE BIT(0)
59 #define DPD_SAMPLE_DISABLE (0 << 0)
60
61 #define PWRGATE_TOGGLE 0x30
62 #define PWRGATE_TOGGLE_START BIT(8)
63
64 #define REMOVE_CLAMPING 0x34
65
66 #define PWRGATE_STATUS 0x38
67
68 #define PMC_IMPL_E_33V_PWR 0x40
69
70 #define PMC_PWR_DET 0x48
71
72 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
73 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
74 #define PMC_SCRATCH0_MODE_RCM BIT(1)
75 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
76 PMC_SCRATCH0_MODE_BOOTLOADER | \
77 PMC_SCRATCH0_MODE_RCM)
78
79 #define PMC_CPUPWRGOOD_TIMER 0xc8
80 #define PMC_CPUPWROFF_TIMER 0xcc
81
82 #define PMC_PWR_DET_VALUE 0xe4
83
84 #define PMC_SCRATCH41 0x140
85
86 #define PMC_SENSOR_CTRL 0x1b0
87 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
88 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
89
90 #define PMC_RST_STATUS 0x1b4
91 #define PMC_RST_STATUS_POR 0
92 #define PMC_RST_STATUS_WATCHDOG 1
93 #define PMC_RST_STATUS_SENSOR 2
94 #define PMC_RST_STATUS_SW_MAIN 3
95 #define PMC_RST_STATUS_LP0 4
96 #define PMC_RST_STATUS_AOTAG 5
97
98 #define IO_DPD_REQ 0x1b8
99 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
100 #define IO_DPD_REQ_CODE_OFF (1U << 30)
101 #define IO_DPD_REQ_CODE_ON (2U << 30)
102 #define IO_DPD_REQ_CODE_MASK (3U << 30)
103
104 #define IO_DPD_STATUS 0x1bc
105 #define IO_DPD2_REQ 0x1c0
106 #define IO_DPD2_STATUS 0x1c4
107 #define SEL_DPD_TIM 0x1c8
108
109 #define PMC_SCRATCH54 0x258
110 #define PMC_SCRATCH54_DATA_SHIFT 8
111 #define PMC_SCRATCH54_ADDR_SHIFT 0
112
113 #define PMC_SCRATCH55 0x25c
114 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
115 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
116 #define PMC_SCRATCH55_PINMUX_SHIFT 24
117 #define PMC_SCRATCH55_16BITOP BIT(15)
118 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
119 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
120
121 #define GPU_RG_CNTRL 0x2d4
122
123 /* Tegra186 and later */
124 #define WAKE_AOWAKE_CTRL 0x4f4
125 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
126
127 struct tegra_powergate {
128 struct generic_pm_domain genpd;
129 struct tegra_pmc *pmc;
130 unsigned int id;
131 struct clk **clks;
132 unsigned int num_clks;
133 struct reset_control *reset;
134 };
135
136 struct tegra_io_pad_soc {
137 enum tegra_io_pad id;
138 unsigned int dpd;
139 unsigned int voltage;
140 };
141
142 struct tegra_pmc_regs {
143 unsigned int scratch0;
144 unsigned int dpd_req;
145 unsigned int dpd_status;
146 unsigned int dpd2_req;
147 unsigned int dpd2_status;
148 };
149
150 struct tegra_pmc_soc {
151 unsigned int num_powergates;
152 const char *const *powergates;
153 unsigned int num_cpu_powergates;
154 const u8 *cpu_powergates;
155
156 bool has_tsense_reset;
157 bool has_gpu_clamps;
158 bool needs_mbist_war;
159 bool has_impl_33v_pwr;
160
161 const struct tegra_io_pad_soc *io_pads;
162 unsigned int num_io_pads;
163
164 const struct tegra_pmc_regs *regs;
165 void (*init)(struct tegra_pmc *pmc);
166 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
167 struct device_node *np,
168 bool invert);
169 };
170
171 /**
172 * struct tegra_pmc - NVIDIA Tegra PMC
173 * @dev: pointer to PMC device structure
174 * @base: pointer to I/O remapped register region
175 * @clk: pointer to pclk clock
176 * @soc: pointer to SoC data structure
177 * @debugfs: pointer to debugfs entry
178 * @rate: currently configured rate of pclk
179 * @suspend_mode: lowest suspend mode available
180 * @cpu_good_time: CPU power good time (in microseconds)
181 * @cpu_off_time: CPU power off time (in microsecends)
182 * @core_osc_time: core power good OSC time (in microseconds)
183 * @core_pmu_time: core power good PMU time (in microseconds)
184 * @core_off_time: core power off time (in microseconds)
185 * @corereq_high: core power request is active-high
186 * @sysclkreq_high: system clock request is active-high
187 * @combined_req: combined power request for CPU & core
188 * @cpu_pwr_good_en: CPU power good signal is enabled
189 * @lp0_vec_phys: physical base address of the LP0 warm boot code
190 * @lp0_vec_size: size of the LP0 warm boot code
191 * @powergates_available: Bitmap of available power gates
192 * @powergates_lock: mutex for power gate register access
193 */
194 struct tegra_pmc {
195 struct device *dev;
196 void __iomem *base;
197 void __iomem *wake;
198 void __iomem *aotag;
199 void __iomem *scratch;
200 struct clk *clk;
201 struct dentry *debugfs;
202
203 const struct tegra_pmc_soc *soc;
204
205 unsigned long rate;
206
207 enum tegra_suspend_mode suspend_mode;
208 u32 cpu_good_time;
209 u32 cpu_off_time;
210 u32 core_osc_time;
211 u32 core_pmu_time;
212 u32 core_off_time;
213 bool corereq_high;
214 bool sysclkreq_high;
215 bool combined_req;
216 bool cpu_pwr_good_en;
217 u32 lp0_vec_phys;
218 u32 lp0_vec_size;
219 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
220
221 struct mutex powergates_lock;
222 };
223
224 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
225 .base = NULL,
226 .suspend_mode = TEGRA_SUSPEND_NONE,
227 };
228
229 static inline struct tegra_powergate *
230 to_powergate(struct generic_pm_domain *domain)
231 {
232 return container_of(domain, struct tegra_powergate, genpd);
233 }
234
235 static u32 tegra_pmc_readl(unsigned long offset)
236 {
237 return readl(pmc->base + offset);
238 }
239
240 static void tegra_pmc_writel(u32 value, unsigned long offset)
241 {
242 writel(value, pmc->base + offset);
243 }
244
245 static inline bool tegra_powergate_state(int id)
246 {
247 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
248 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
249 else
250 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
251 }
252
253 static inline bool tegra_powergate_is_valid(int id)
254 {
255 return (pmc->soc && pmc->soc->powergates[id]);
256 }
257
258 static inline bool tegra_powergate_is_available(int id)
259 {
260 return test_bit(id, pmc->powergates_available);
261 }
262
263 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
264 {
265 unsigned int i;
266
267 if (!pmc || !pmc->soc || !name)
268 return -EINVAL;
269
270 for (i = 0; i < pmc->soc->num_powergates; i++) {
271 if (!tegra_powergate_is_valid(i))
272 continue;
273
274 if (!strcmp(name, pmc->soc->powergates[i]))
275 return i;
276 }
277
278 return -ENODEV;
279 }
280
281 /**
282 * tegra_powergate_set() - set the state of a partition
283 * @id: partition ID
284 * @new_state: new state of the partition
285 */
286 static int tegra_powergate_set(unsigned int id, bool new_state)
287 {
288 bool status;
289 int err;
290
291 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
292 return -EINVAL;
293
294 mutex_lock(&pmc->powergates_lock);
295
296 if (tegra_powergate_state(id) == new_state) {
297 mutex_unlock(&pmc->powergates_lock);
298 return 0;
299 }
300
301 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
302
303 err = readx_poll_timeout(tegra_powergate_state, id, status,
304 status == new_state, 10, 100000);
305
306 mutex_unlock(&pmc->powergates_lock);
307
308 return err;
309 }
310
311 static int __tegra_powergate_remove_clamping(unsigned int id)
312 {
313 u32 mask;
314
315 mutex_lock(&pmc->powergates_lock);
316
317 /*
318 * On Tegra124 and later, the clamps for the GPU are controlled by a
319 * separate register (with different semantics).
320 */
321 if (id == TEGRA_POWERGATE_3D) {
322 if (pmc->soc->has_gpu_clamps) {
323 tegra_pmc_writel(0, GPU_RG_CNTRL);
324 goto out;
325 }
326 }
327
328 /*
329 * Tegra 2 has a bug where PCIE and VDE clamping masks are
330 * swapped relatively to the partition ids
331 */
332 if (id == TEGRA_POWERGATE_VDEC)
333 mask = (1 << TEGRA_POWERGATE_PCIE);
334 else if (id == TEGRA_POWERGATE_PCIE)
335 mask = (1 << TEGRA_POWERGATE_VDEC);
336 else
337 mask = (1 << id);
338
339 tegra_pmc_writel(mask, REMOVE_CLAMPING);
340
341 out:
342 mutex_unlock(&pmc->powergates_lock);
343
344 return 0;
345 }
346
347 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
348 {
349 unsigned int i;
350
351 for (i = 0; i < pg->num_clks; i++)
352 clk_disable_unprepare(pg->clks[i]);
353 }
354
355 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
356 {
357 unsigned int i;
358 int err;
359
360 for (i = 0; i < pg->num_clks; i++) {
361 err = clk_prepare_enable(pg->clks[i]);
362 if (err)
363 goto out;
364 }
365
366 return 0;
367
368 out:
369 while (i--)
370 clk_disable_unprepare(pg->clks[i]);
371
372 return err;
373 }
374
375 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
376 {
377 return 0;
378 }
379
380 static int tegra_powergate_power_up(struct tegra_powergate *pg,
381 bool disable_clocks)
382 {
383 int err;
384
385 err = reset_control_assert(pg->reset);
386 if (err)
387 return err;
388
389 usleep_range(10, 20);
390
391 err = tegra_powergate_set(pg->id, true);
392 if (err < 0)
393 return err;
394
395 usleep_range(10, 20);
396
397 err = tegra_powergate_enable_clocks(pg);
398 if (err)
399 goto disable_clks;
400
401 usleep_range(10, 20);
402
403 err = __tegra_powergate_remove_clamping(pg->id);
404 if (err)
405 goto disable_clks;
406
407 usleep_range(10, 20);
408
409 err = reset_control_deassert(pg->reset);
410 if (err)
411 goto powergate_off;
412
413 usleep_range(10, 20);
414
415 if (pg->pmc->soc->needs_mbist_war)
416 err = tegra210_clk_handle_mbist_war(pg->id);
417 if (err)
418 goto disable_clks;
419
420 if (disable_clocks)
421 tegra_powergate_disable_clocks(pg);
422
423 return 0;
424
425 disable_clks:
426 tegra_powergate_disable_clocks(pg);
427 usleep_range(10, 20);
428
429 powergate_off:
430 tegra_powergate_set(pg->id, false);
431
432 return err;
433 }
434
435 static int tegra_powergate_power_down(struct tegra_powergate *pg)
436 {
437 int err;
438
439 err = tegra_powergate_enable_clocks(pg);
440 if (err)
441 return err;
442
443 usleep_range(10, 20);
444
445 err = reset_control_assert(pg->reset);
446 if (err)
447 goto disable_clks;
448
449 usleep_range(10, 20);
450
451 tegra_powergate_disable_clocks(pg);
452
453 usleep_range(10, 20);
454
455 err = tegra_powergate_set(pg->id, false);
456 if (err)
457 goto assert_resets;
458
459 return 0;
460
461 assert_resets:
462 tegra_powergate_enable_clocks(pg);
463 usleep_range(10, 20);
464 reset_control_deassert(pg->reset);
465 usleep_range(10, 20);
466
467 disable_clks:
468 tegra_powergate_disable_clocks(pg);
469
470 return err;
471 }
472
473 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
474 {
475 struct tegra_powergate *pg = to_powergate(domain);
476 int err;
477
478 err = tegra_powergate_power_up(pg, true);
479 if (err)
480 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
481 err);
482
483 return err;
484 }
485
486 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
487 {
488 struct tegra_powergate *pg = to_powergate(domain);
489 int err;
490
491 err = tegra_powergate_power_down(pg);
492 if (err)
493 pr_err("failed to turn off PM domain %s: %d\n",
494 pg->genpd.name, err);
495
496 return err;
497 }
498
499 /**
500 * tegra_powergate_power_on() - power on partition
501 * @id: partition ID
502 */
503 int tegra_powergate_power_on(unsigned int id)
504 {
505 if (!tegra_powergate_is_available(id))
506 return -EINVAL;
507
508 return tegra_powergate_set(id, true);
509 }
510
511 /**
512 * tegra_powergate_power_off() - power off partition
513 * @id: partition ID
514 */
515 int tegra_powergate_power_off(unsigned int id)
516 {
517 if (!tegra_powergate_is_available(id))
518 return -EINVAL;
519
520 return tegra_powergate_set(id, false);
521 }
522 EXPORT_SYMBOL(tegra_powergate_power_off);
523
524 /**
525 * tegra_powergate_is_powered() - check if partition is powered
526 * @id: partition ID
527 */
528 int tegra_powergate_is_powered(unsigned int id)
529 {
530 if (!tegra_powergate_is_valid(id))
531 return -EINVAL;
532
533 return tegra_powergate_state(id);
534 }
535
536 /**
537 * tegra_powergate_remove_clamping() - remove power clamps for partition
538 * @id: partition ID
539 */
540 int tegra_powergate_remove_clamping(unsigned int id)
541 {
542 if (!tegra_powergate_is_available(id))
543 return -EINVAL;
544
545 return __tegra_powergate_remove_clamping(id);
546 }
547 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
548
549 /**
550 * tegra_powergate_sequence_power_up() - power up partition
551 * @id: partition ID
552 * @clk: clock for partition
553 * @rst: reset for partition
554 *
555 * Must be called with clk disabled, and returns with clk enabled.
556 */
557 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
558 struct reset_control *rst)
559 {
560 struct tegra_powergate *pg;
561 int err;
562
563 if (!tegra_powergate_is_available(id))
564 return -EINVAL;
565
566 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
567 if (!pg)
568 return -ENOMEM;
569
570 pg->id = id;
571 pg->clks = &clk;
572 pg->num_clks = 1;
573 pg->reset = rst;
574 pg->pmc = pmc;
575
576 err = tegra_powergate_power_up(pg, false);
577 if (err)
578 pr_err("failed to turn on partition %d: %d\n", id, err);
579
580 kfree(pg);
581
582 return err;
583 }
584 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
585
586 #ifdef CONFIG_SMP
587 /**
588 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
589 * @cpuid: CPU partition ID
590 *
591 * Returns the partition ID corresponding to the CPU partition ID or a
592 * negative error code on failure.
593 */
594 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
595 {
596 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
597 return pmc->soc->cpu_powergates[cpuid];
598
599 return -EINVAL;
600 }
601
602 /**
603 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
604 * @cpuid: CPU partition ID
605 */
606 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
607 {
608 int id;
609
610 id = tegra_get_cpu_powergate_id(cpuid);
611 if (id < 0)
612 return false;
613
614 return tegra_powergate_is_powered(id);
615 }
616
617 /**
618 * tegra_pmc_cpu_power_on() - power on CPU partition
619 * @cpuid: CPU partition ID
620 */
621 int tegra_pmc_cpu_power_on(unsigned int cpuid)
622 {
623 int id;
624
625 id = tegra_get_cpu_powergate_id(cpuid);
626 if (id < 0)
627 return id;
628
629 return tegra_powergate_set(id, true);
630 }
631
632 /**
633 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
634 * @cpuid: CPU partition ID
635 */
636 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
637 {
638 int id;
639
640 id = tegra_get_cpu_powergate_id(cpuid);
641 if (id < 0)
642 return id;
643
644 return tegra_powergate_remove_clamping(id);
645 }
646 #endif /* CONFIG_SMP */
647
648 static int tegra_pmc_restart_notify(struct notifier_block *this,
649 unsigned long action, void *data)
650 {
651 const char *cmd = data;
652 u32 value;
653
654 value = readl(pmc->scratch + pmc->soc->regs->scratch0);
655 value &= ~PMC_SCRATCH0_MODE_MASK;
656
657 if (cmd) {
658 if (strcmp(cmd, "recovery") == 0)
659 value |= PMC_SCRATCH0_MODE_RECOVERY;
660
661 if (strcmp(cmd, "bootloader") == 0)
662 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
663
664 if (strcmp(cmd, "forced-recovery") == 0)
665 value |= PMC_SCRATCH0_MODE_RCM;
666 }
667
668 writel(value, pmc->scratch + pmc->soc->regs->scratch0);
669
670 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
671 value = tegra_pmc_readl(PMC_CNTRL);
672 value |= PMC_CNTRL_MAIN_RST;
673 tegra_pmc_writel(value, PMC_CNTRL);
674
675 return NOTIFY_DONE;
676 }
677
678 static struct notifier_block tegra_pmc_restart_handler = {
679 .notifier_call = tegra_pmc_restart_notify,
680 .priority = 128,
681 };
682
683 static int powergate_show(struct seq_file *s, void *data)
684 {
685 unsigned int i;
686 int status;
687
688 seq_printf(s, " powergate powered\n");
689 seq_printf(s, "------------------\n");
690
691 for (i = 0; i < pmc->soc->num_powergates; i++) {
692 status = tegra_powergate_is_powered(i);
693 if (status < 0)
694 continue;
695
696 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
697 status ? "yes" : "no");
698 }
699
700 return 0;
701 }
702
703 static int powergate_open(struct inode *inode, struct file *file)
704 {
705 return single_open(file, powergate_show, inode->i_private);
706 }
707
708 static const struct file_operations powergate_fops = {
709 .open = powergate_open,
710 .read = seq_read,
711 .llseek = seq_lseek,
712 .release = single_release,
713 };
714
715 static int tegra_powergate_debugfs_init(void)
716 {
717 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
718 &powergate_fops);
719 if (!pmc->debugfs)
720 return -ENOMEM;
721
722 return 0;
723 }
724
725 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
726 struct device_node *np)
727 {
728 struct clk *clk;
729 unsigned int i, count;
730 int err;
731
732 count = of_clk_get_parent_count(np);
733 if (count == 0)
734 return -ENODEV;
735
736 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
737 if (!pg->clks)
738 return -ENOMEM;
739
740 for (i = 0; i < count; i++) {
741 pg->clks[i] = of_clk_get(np, i);
742 if (IS_ERR(pg->clks[i])) {
743 err = PTR_ERR(pg->clks[i]);
744 goto err;
745 }
746 }
747
748 pg->num_clks = count;
749
750 return 0;
751
752 err:
753 while (i--)
754 clk_put(pg->clks[i]);
755
756 kfree(pg->clks);
757
758 return err;
759 }
760
761 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
762 struct device_node *np, bool off)
763 {
764 int err;
765
766 pg->reset = of_reset_control_array_get_exclusive(np);
767 if (IS_ERR(pg->reset)) {
768 err = PTR_ERR(pg->reset);
769 pr_err("failed to get device resets: %d\n", err);
770 return err;
771 }
772
773 if (off)
774 err = reset_control_assert(pg->reset);
775 else
776 err = reset_control_deassert(pg->reset);
777
778 if (err)
779 reset_control_put(pg->reset);
780
781 return err;
782 }
783
784 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
785 {
786 struct tegra_powergate *pg;
787 int id, err;
788 bool off;
789
790 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
791 if (!pg)
792 return;
793
794 id = tegra_powergate_lookup(pmc, np->name);
795 if (id < 0) {
796 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
797 goto free_mem;
798 }
799
800 /*
801 * Clear the bit for this powergate so it cannot be managed
802 * directly via the legacy APIs for controlling powergates.
803 */
804 clear_bit(id, pmc->powergates_available);
805
806 pg->id = id;
807 pg->genpd.name = np->name;
808 pg->genpd.power_off = tegra_genpd_power_off;
809 pg->genpd.power_on = tegra_genpd_power_on;
810 pg->pmc = pmc;
811
812 off = !tegra_powergate_is_powered(pg->id);
813
814 err = tegra_powergate_of_get_clks(pg, np);
815 if (err < 0) {
816 pr_err("failed to get clocks for %s: %d\n", np->name, err);
817 goto set_available;
818 }
819
820 err = tegra_powergate_of_get_resets(pg, np, off);
821 if (err < 0) {
822 pr_err("failed to get resets for %s: %d\n", np->name, err);
823 goto remove_clks;
824 }
825
826 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
827 if (off)
828 WARN_ON(tegra_powergate_power_up(pg, true));
829
830 goto remove_resets;
831 }
832
833 /*
834 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
835 * host and super-speed partitions. Once the XHCI driver
836 * manages the partitions itself this code can be removed. Note
837 * that we don't register these partitions with the genpd core
838 * to avoid it from powering down the partitions as they appear
839 * to be unused.
840 */
841 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
842 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
843 if (off)
844 WARN_ON(tegra_powergate_power_up(pg, true));
845
846 goto remove_resets;
847 }
848
849 err = pm_genpd_init(&pg->genpd, NULL, off);
850 if (err < 0) {
851 pr_err("failed to initialise PM domain %s: %d\n", np->name,
852 err);
853 goto remove_resets;
854 }
855
856 err = of_genpd_add_provider_simple(np, &pg->genpd);
857 if (err < 0) {
858 pr_err("failed to add PM domain provider for %s: %d\n",
859 np->name, err);
860 goto remove_genpd;
861 }
862
863 pr_debug("added PM domain %s\n", pg->genpd.name);
864
865 return;
866
867 remove_genpd:
868 pm_genpd_remove(&pg->genpd);
869
870 remove_resets:
871 reset_control_put(pg->reset);
872
873 remove_clks:
874 while (pg->num_clks--)
875 clk_put(pg->clks[pg->num_clks]);
876
877 kfree(pg->clks);
878
879 set_available:
880 set_bit(id, pmc->powergates_available);
881
882 free_mem:
883 kfree(pg);
884 }
885
886 static void tegra_powergate_init(struct tegra_pmc *pmc,
887 struct device_node *parent)
888 {
889 struct device_node *np, *child;
890 unsigned int i;
891
892 /* Create a bitmap of the available and valid partitions */
893 for (i = 0; i < pmc->soc->num_powergates; i++)
894 if (pmc->soc->powergates[i])
895 set_bit(i, pmc->powergates_available);
896
897 np = of_get_child_by_name(parent, "powergates");
898 if (!np)
899 return;
900
901 for_each_child_of_node(np, child)
902 tegra_powergate_add(pmc, child);
903
904 of_node_put(np);
905 }
906
907 static const struct tegra_io_pad_soc *
908 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
909 {
910 unsigned int i;
911
912 for (i = 0; i < pmc->soc->num_io_pads; i++)
913 if (pmc->soc->io_pads[i].id == id)
914 return &pmc->soc->io_pads[i];
915
916 return NULL;
917 }
918
919 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
920 unsigned long *status, u32 *mask)
921 {
922 const struct tegra_io_pad_soc *pad;
923 unsigned long rate, value;
924
925 pad = tegra_io_pad_find(pmc, id);
926 if (!pad) {
927 pr_err("invalid I/O pad ID %u\n", id);
928 return -ENOENT;
929 }
930
931 if (pad->dpd == UINT_MAX)
932 return -ENOTSUPP;
933
934 *mask = BIT(pad->dpd % 32);
935
936 if (pad->dpd < 32) {
937 *status = pmc->soc->regs->dpd_status;
938 *request = pmc->soc->regs->dpd_req;
939 } else {
940 *status = pmc->soc->regs->dpd2_status;
941 *request = pmc->soc->regs->dpd2_req;
942 }
943
944 if (pmc->clk) {
945 rate = clk_get_rate(pmc->clk);
946 if (!rate) {
947 pr_err("failed to get clock rate\n");
948 return -ENODEV;
949 }
950
951 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
952
953 /* must be at least 200 ns, in APB (PCLK) clock cycles */
954 value = DIV_ROUND_UP(1000000000, rate);
955 value = DIV_ROUND_UP(200, value);
956 tegra_pmc_writel(value, SEL_DPD_TIM);
957 }
958
959 return 0;
960 }
961
962 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
963 u32 val, unsigned long timeout)
964 {
965 u32 value;
966
967 timeout = jiffies + msecs_to_jiffies(timeout);
968
969 while (time_after(timeout, jiffies)) {
970 value = tegra_pmc_readl(offset);
971 if ((value & mask) == val)
972 return 0;
973
974 usleep_range(250, 1000);
975 }
976
977 return -ETIMEDOUT;
978 }
979
980 static void tegra_io_pad_unprepare(void)
981 {
982 if (pmc->clk)
983 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
984 }
985
986 /**
987 * tegra_io_pad_power_enable() - enable power to I/O pad
988 * @id: Tegra I/O pad ID for which to enable power
989 *
990 * Returns: 0 on success or a negative error code on failure.
991 */
992 int tegra_io_pad_power_enable(enum tegra_io_pad id)
993 {
994 unsigned long request, status;
995 u32 mask;
996 int err;
997
998 mutex_lock(&pmc->powergates_lock);
999
1000 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1001 if (err < 0) {
1002 pr_err("failed to prepare I/O pad: %d\n", err);
1003 goto unlock;
1004 }
1005
1006 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1007
1008 err = tegra_io_pad_poll(status, mask, 0, 250);
1009 if (err < 0) {
1010 pr_err("failed to enable I/O pad: %d\n", err);
1011 goto unlock;
1012 }
1013
1014 tegra_io_pad_unprepare();
1015
1016 unlock:
1017 mutex_unlock(&pmc->powergates_lock);
1018 return err;
1019 }
1020 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1021
1022 /**
1023 * tegra_io_pad_power_disable() - disable power to I/O pad
1024 * @id: Tegra I/O pad ID for which to disable power
1025 *
1026 * Returns: 0 on success or a negative error code on failure.
1027 */
1028 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1029 {
1030 unsigned long request, status;
1031 u32 mask;
1032 int err;
1033
1034 mutex_lock(&pmc->powergates_lock);
1035
1036 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1037 if (err < 0) {
1038 pr_err("failed to prepare I/O pad: %d\n", err);
1039 goto unlock;
1040 }
1041
1042 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1043
1044 err = tegra_io_pad_poll(status, mask, mask, 250);
1045 if (err < 0) {
1046 pr_err("failed to disable I/O pad: %d\n", err);
1047 goto unlock;
1048 }
1049
1050 tegra_io_pad_unprepare();
1051
1052 unlock:
1053 mutex_unlock(&pmc->powergates_lock);
1054 return err;
1055 }
1056 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1057
1058 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1059 enum tegra_io_pad_voltage voltage)
1060 {
1061 const struct tegra_io_pad_soc *pad;
1062 u32 value;
1063
1064 pad = tegra_io_pad_find(pmc, id);
1065 if (!pad)
1066 return -ENOENT;
1067
1068 if (pad->voltage == UINT_MAX)
1069 return -ENOTSUPP;
1070
1071 mutex_lock(&pmc->powergates_lock);
1072
1073 if (pmc->soc->has_impl_33v_pwr) {
1074 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR);
1075
1076 if (voltage == TEGRA_IO_PAD_1800000UV)
1077 value &= ~BIT(pad->voltage);
1078 else
1079 value |= BIT(pad->voltage);
1080
1081 tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR);
1082 } else {
1083 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1084 value = tegra_pmc_readl(PMC_PWR_DET);
1085 value |= BIT(pad->voltage);
1086 tegra_pmc_writel(value, PMC_PWR_DET);
1087
1088 /* update I/O voltage */
1089 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1090
1091 if (voltage == TEGRA_IO_PAD_1800000UV)
1092 value &= ~BIT(pad->voltage);
1093 else
1094 value |= BIT(pad->voltage);
1095
1096 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1097 }
1098
1099 mutex_unlock(&pmc->powergates_lock);
1100
1101 usleep_range(100, 250);
1102
1103 return 0;
1104 }
1105 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1106
1107 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1108 {
1109 const struct tegra_io_pad_soc *pad;
1110 u32 value;
1111
1112 pad = tegra_io_pad_find(pmc, id);
1113 if (!pad)
1114 return -ENOENT;
1115
1116 if (pad->voltage == UINT_MAX)
1117 return -ENOTSUPP;
1118
1119 if (pmc->soc->has_impl_33v_pwr)
1120 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR);
1121 else
1122 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1123
1124 if ((value & BIT(pad->voltage)) == 0)
1125 return TEGRA_IO_PAD_1800000UV;
1126
1127 return TEGRA_IO_PAD_3300000UV;
1128 }
1129 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1130
1131 /**
1132 * tegra_io_rail_power_on() - enable power to I/O rail
1133 * @id: Tegra I/O pad ID for which to enable power
1134 *
1135 * See also: tegra_io_pad_power_enable()
1136 */
1137 int tegra_io_rail_power_on(unsigned int id)
1138 {
1139 return tegra_io_pad_power_enable(id);
1140 }
1141 EXPORT_SYMBOL(tegra_io_rail_power_on);
1142
1143 /**
1144 * tegra_io_rail_power_off() - disable power to I/O rail
1145 * @id: Tegra I/O pad ID for which to disable power
1146 *
1147 * See also: tegra_io_pad_power_disable()
1148 */
1149 int tegra_io_rail_power_off(unsigned int id)
1150 {
1151 return tegra_io_pad_power_disable(id);
1152 }
1153 EXPORT_SYMBOL(tegra_io_rail_power_off);
1154
1155 #ifdef CONFIG_PM_SLEEP
1156 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1157 {
1158 return pmc->suspend_mode;
1159 }
1160
1161 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1162 {
1163 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1164 return;
1165
1166 pmc->suspend_mode = mode;
1167 }
1168
1169 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1170 {
1171 unsigned long long rate = 0;
1172 u32 value;
1173
1174 switch (mode) {
1175 case TEGRA_SUSPEND_LP1:
1176 rate = 32768;
1177 break;
1178
1179 case TEGRA_SUSPEND_LP2:
1180 rate = clk_get_rate(pmc->clk);
1181 break;
1182
1183 default:
1184 break;
1185 }
1186
1187 if (WARN_ON_ONCE(rate == 0))
1188 rate = 100000000;
1189
1190 if (rate != pmc->rate) {
1191 u64 ticks;
1192
1193 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1194 do_div(ticks, USEC_PER_SEC);
1195 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1196
1197 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1198 do_div(ticks, USEC_PER_SEC);
1199 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1200
1201 wmb();
1202
1203 pmc->rate = rate;
1204 }
1205
1206 value = tegra_pmc_readl(PMC_CNTRL);
1207 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1208 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1209 tegra_pmc_writel(value, PMC_CNTRL);
1210 }
1211 #endif
1212
1213 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1214 {
1215 u32 value, values[2];
1216
1217 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1218 } else {
1219 switch (value) {
1220 case 0:
1221 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1222 break;
1223
1224 case 1:
1225 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1226 break;
1227
1228 case 2:
1229 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1230 break;
1231
1232 default:
1233 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1234 break;
1235 }
1236 }
1237
1238 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1239
1240 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1241 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1242
1243 pmc->cpu_good_time = value;
1244
1245 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1246 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1247
1248 pmc->cpu_off_time = value;
1249
1250 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1251 values, ARRAY_SIZE(values)))
1252 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1253
1254 pmc->core_osc_time = values[0];
1255 pmc->core_pmu_time = values[1];
1256
1257 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1258 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1259
1260 pmc->core_off_time = value;
1261
1262 pmc->corereq_high = of_property_read_bool(np,
1263 "nvidia,core-power-req-active-high");
1264
1265 pmc->sysclkreq_high = of_property_read_bool(np,
1266 "nvidia,sys-clock-req-active-high");
1267
1268 pmc->combined_req = of_property_read_bool(np,
1269 "nvidia,combined-power-req");
1270
1271 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1272 "nvidia,cpu-pwr-good-en");
1273
1274 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1275 ARRAY_SIZE(values)))
1276 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1277 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1278
1279 pmc->lp0_vec_phys = values[0];
1280 pmc->lp0_vec_size = values[1];
1281
1282 return 0;
1283 }
1284
1285 static void tegra_pmc_init(struct tegra_pmc *pmc)
1286 {
1287 if (pmc->soc->init)
1288 pmc->soc->init(pmc);
1289 }
1290
1291 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1292 {
1293 static const char disabled[] = "emergency thermal reset disabled";
1294 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1295 struct device *dev = pmc->dev;
1296 struct device_node *np;
1297 u32 value, checksum;
1298
1299 if (!pmc->soc->has_tsense_reset)
1300 return;
1301
1302 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1303 if (!np) {
1304 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1305 return;
1306 }
1307
1308 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1309 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1310 goto out;
1311 }
1312
1313 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1314 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1315 goto out;
1316 }
1317
1318 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1319 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1320 goto out;
1321 }
1322
1323 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1324 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1325 goto out;
1326 }
1327
1328 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1329 pinmux = 0;
1330
1331 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1332 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1333 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1334
1335 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1336 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1337 tegra_pmc_writel(value, PMC_SCRATCH54);
1338
1339 value = PMC_SCRATCH55_RESET_TEGRA;
1340 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1341 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1342 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1343
1344 /*
1345 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1346 * contain the checksum and are currently zero, so they are not added.
1347 */
1348 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1349 + ((value >> 24) & 0xff);
1350 checksum &= 0xff;
1351 checksum = 0x100 - checksum;
1352
1353 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1354
1355 tegra_pmc_writel(value, PMC_SCRATCH55);
1356
1357 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1358 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1359 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1360
1361 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1362
1363 out:
1364 of_node_put(np);
1365 }
1366
1367 static int tegra_pmc_probe(struct platform_device *pdev)
1368 {
1369 void __iomem *base;
1370 struct resource *res;
1371 int err;
1372
1373 /*
1374 * Early initialisation should have configured an initial
1375 * register mapping and setup the soc data pointer. If these
1376 * are not valid then something went badly wrong!
1377 */
1378 if (WARN_ON(!pmc->base || !pmc->soc))
1379 return -ENODEV;
1380
1381 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1382 if (err < 0)
1383 return err;
1384
1385 /* take over the memory region from the early initialization */
1386 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1387 base = devm_ioremap_resource(&pdev->dev, res);
1388 if (IS_ERR(base))
1389 return PTR_ERR(base);
1390
1391 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
1392 if (res) {
1393 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
1394 if (IS_ERR(pmc->wake))
1395 return PTR_ERR(pmc->wake);
1396 } else {
1397 pmc->wake = base;
1398 }
1399
1400 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
1401 if (res) {
1402 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
1403 if (IS_ERR(pmc->aotag))
1404 return PTR_ERR(pmc->aotag);
1405 } else {
1406 pmc->aotag = base;
1407 }
1408
1409 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
1410 if (res) {
1411 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
1412 if (IS_ERR(pmc->scratch))
1413 return PTR_ERR(pmc->scratch);
1414 } else {
1415 pmc->scratch = base;
1416 }
1417
1418 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1419 if (IS_ERR(pmc->clk)) {
1420 err = PTR_ERR(pmc->clk);
1421
1422 if (err != -ENOENT) {
1423 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1424 return err;
1425 }
1426
1427 pmc->clk = NULL;
1428 }
1429
1430 pmc->dev = &pdev->dev;
1431
1432 tegra_pmc_init(pmc);
1433
1434 tegra_pmc_init_tsense_reset(pmc);
1435
1436 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1437 err = tegra_powergate_debugfs_init();
1438 if (err < 0)
1439 return err;
1440 }
1441
1442 err = register_restart_handler(&tegra_pmc_restart_handler);
1443 if (err) {
1444 debugfs_remove(pmc->debugfs);
1445 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1446 err);
1447 return err;
1448 }
1449
1450 mutex_lock(&pmc->powergates_lock);
1451 iounmap(pmc->base);
1452 pmc->base = base;
1453 mutex_unlock(&pmc->powergates_lock);
1454
1455 return 0;
1456 }
1457
1458 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1459 static int tegra_pmc_suspend(struct device *dev)
1460 {
1461 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1462
1463 return 0;
1464 }
1465
1466 static int tegra_pmc_resume(struct device *dev)
1467 {
1468 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1469
1470 return 0;
1471 }
1472
1473 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1474
1475 #endif
1476
1477 static const char * const tegra20_powergates[] = {
1478 [TEGRA_POWERGATE_CPU] = "cpu",
1479 [TEGRA_POWERGATE_3D] = "3d",
1480 [TEGRA_POWERGATE_VENC] = "venc",
1481 [TEGRA_POWERGATE_VDEC] = "vdec",
1482 [TEGRA_POWERGATE_PCIE] = "pcie",
1483 [TEGRA_POWERGATE_L2] = "l2",
1484 [TEGRA_POWERGATE_MPE] = "mpe",
1485 };
1486
1487 static const struct tegra_pmc_regs tegra20_pmc_regs = {
1488 .scratch0 = 0x50,
1489 .dpd_req = 0x1b8,
1490 .dpd_status = 0x1bc,
1491 .dpd2_req = 0x1c0,
1492 .dpd2_status = 0x1c4,
1493 };
1494
1495 static void tegra20_pmc_init(struct tegra_pmc *pmc)
1496 {
1497 u32 value;
1498
1499 /* Always enable CPU power request */
1500 value = tegra_pmc_readl(PMC_CNTRL);
1501 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1502 tegra_pmc_writel(value, PMC_CNTRL);
1503
1504 value = tegra_pmc_readl(PMC_CNTRL);
1505
1506 if (pmc->sysclkreq_high)
1507 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1508 else
1509 value |= PMC_CNTRL_SYSCLK_POLARITY;
1510
1511 /* configure the output polarity while the request is tristated */
1512 tegra_pmc_writel(value, PMC_CNTRL);
1513
1514 /* now enable the request */
1515 value = tegra_pmc_readl(PMC_CNTRL);
1516 value |= PMC_CNTRL_SYSCLK_OE;
1517 tegra_pmc_writel(value, PMC_CNTRL);
1518 }
1519
1520 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1521 struct device_node *np,
1522 bool invert)
1523 {
1524 u32 value;
1525
1526 value = tegra_pmc_readl(PMC_CNTRL);
1527
1528 if (invert)
1529 value |= PMC_CNTRL_INTR_POLARITY;
1530 else
1531 value &= ~PMC_CNTRL_INTR_POLARITY;
1532
1533 tegra_pmc_writel(value, PMC_CNTRL);
1534 }
1535
1536 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1537 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1538 .powergates = tegra20_powergates,
1539 .num_cpu_powergates = 0,
1540 .cpu_powergates = NULL,
1541 .has_tsense_reset = false,
1542 .has_gpu_clamps = false,
1543 .num_io_pads = 0,
1544 .io_pads = NULL,
1545 .regs = &tegra20_pmc_regs,
1546 .init = tegra20_pmc_init,
1547 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1548 };
1549
1550 static const char * const tegra30_powergates[] = {
1551 [TEGRA_POWERGATE_CPU] = "cpu0",
1552 [TEGRA_POWERGATE_3D] = "3d0",
1553 [TEGRA_POWERGATE_VENC] = "venc",
1554 [TEGRA_POWERGATE_VDEC] = "vdec",
1555 [TEGRA_POWERGATE_PCIE] = "pcie",
1556 [TEGRA_POWERGATE_L2] = "l2",
1557 [TEGRA_POWERGATE_MPE] = "mpe",
1558 [TEGRA_POWERGATE_HEG] = "heg",
1559 [TEGRA_POWERGATE_SATA] = "sata",
1560 [TEGRA_POWERGATE_CPU1] = "cpu1",
1561 [TEGRA_POWERGATE_CPU2] = "cpu2",
1562 [TEGRA_POWERGATE_CPU3] = "cpu3",
1563 [TEGRA_POWERGATE_CELP] = "celp",
1564 [TEGRA_POWERGATE_3D1] = "3d1",
1565 };
1566
1567 static const u8 tegra30_cpu_powergates[] = {
1568 TEGRA_POWERGATE_CPU,
1569 TEGRA_POWERGATE_CPU1,
1570 TEGRA_POWERGATE_CPU2,
1571 TEGRA_POWERGATE_CPU3,
1572 };
1573
1574 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1575 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1576 .powergates = tegra30_powergates,
1577 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1578 .cpu_powergates = tegra30_cpu_powergates,
1579 .has_tsense_reset = true,
1580 .has_gpu_clamps = false,
1581 .has_impl_33v_pwr = false,
1582 .num_io_pads = 0,
1583 .io_pads = NULL,
1584 .regs = &tegra20_pmc_regs,
1585 .init = tegra20_pmc_init,
1586 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1587 };
1588
1589 static const char * const tegra114_powergates[] = {
1590 [TEGRA_POWERGATE_CPU] = "crail",
1591 [TEGRA_POWERGATE_3D] = "3d",
1592 [TEGRA_POWERGATE_VENC] = "venc",
1593 [TEGRA_POWERGATE_VDEC] = "vdec",
1594 [TEGRA_POWERGATE_MPE] = "mpe",
1595 [TEGRA_POWERGATE_HEG] = "heg",
1596 [TEGRA_POWERGATE_CPU1] = "cpu1",
1597 [TEGRA_POWERGATE_CPU2] = "cpu2",
1598 [TEGRA_POWERGATE_CPU3] = "cpu3",
1599 [TEGRA_POWERGATE_CELP] = "celp",
1600 [TEGRA_POWERGATE_CPU0] = "cpu0",
1601 [TEGRA_POWERGATE_C0NC] = "c0nc",
1602 [TEGRA_POWERGATE_C1NC] = "c1nc",
1603 [TEGRA_POWERGATE_DIS] = "dis",
1604 [TEGRA_POWERGATE_DISB] = "disb",
1605 [TEGRA_POWERGATE_XUSBA] = "xusba",
1606 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1607 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1608 };
1609
1610 static const u8 tegra114_cpu_powergates[] = {
1611 TEGRA_POWERGATE_CPU0,
1612 TEGRA_POWERGATE_CPU1,
1613 TEGRA_POWERGATE_CPU2,
1614 TEGRA_POWERGATE_CPU3,
1615 };
1616
1617 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1618 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1619 .powergates = tegra114_powergates,
1620 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1621 .cpu_powergates = tegra114_cpu_powergates,
1622 .has_tsense_reset = true,
1623 .has_gpu_clamps = false,
1624 .has_impl_33v_pwr = false,
1625 .num_io_pads = 0,
1626 .io_pads = NULL,
1627 .regs = &tegra20_pmc_regs,
1628 .init = tegra20_pmc_init,
1629 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1630 };
1631
1632 static const char * const tegra124_powergates[] = {
1633 [TEGRA_POWERGATE_CPU] = "crail",
1634 [TEGRA_POWERGATE_3D] = "3d",
1635 [TEGRA_POWERGATE_VENC] = "venc",
1636 [TEGRA_POWERGATE_PCIE] = "pcie",
1637 [TEGRA_POWERGATE_VDEC] = "vdec",
1638 [TEGRA_POWERGATE_MPE] = "mpe",
1639 [TEGRA_POWERGATE_HEG] = "heg",
1640 [TEGRA_POWERGATE_SATA] = "sata",
1641 [TEGRA_POWERGATE_CPU1] = "cpu1",
1642 [TEGRA_POWERGATE_CPU2] = "cpu2",
1643 [TEGRA_POWERGATE_CPU3] = "cpu3",
1644 [TEGRA_POWERGATE_CELP] = "celp",
1645 [TEGRA_POWERGATE_CPU0] = "cpu0",
1646 [TEGRA_POWERGATE_C0NC] = "c0nc",
1647 [TEGRA_POWERGATE_C1NC] = "c1nc",
1648 [TEGRA_POWERGATE_SOR] = "sor",
1649 [TEGRA_POWERGATE_DIS] = "dis",
1650 [TEGRA_POWERGATE_DISB] = "disb",
1651 [TEGRA_POWERGATE_XUSBA] = "xusba",
1652 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1653 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1654 [TEGRA_POWERGATE_VIC] = "vic",
1655 [TEGRA_POWERGATE_IRAM] = "iram",
1656 };
1657
1658 static const u8 tegra124_cpu_powergates[] = {
1659 TEGRA_POWERGATE_CPU0,
1660 TEGRA_POWERGATE_CPU1,
1661 TEGRA_POWERGATE_CPU2,
1662 TEGRA_POWERGATE_CPU3,
1663 };
1664
1665 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1666 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1669 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1671 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1672 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1674 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1677 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1678 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1679 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1680 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1682 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1684 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1686 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1687 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1688 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1689 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1690 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1691 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1692 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1693 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1694 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1695 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1696 };
1697
1698 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1699 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1700 .powergates = tegra124_powergates,
1701 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1702 .cpu_powergates = tegra124_cpu_powergates,
1703 .has_tsense_reset = true,
1704 .has_gpu_clamps = true,
1705 .has_impl_33v_pwr = false,
1706 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1707 .io_pads = tegra124_io_pads,
1708 .regs = &tegra20_pmc_regs,
1709 .init = tegra20_pmc_init,
1710 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1711 };
1712
1713 static const char * const tegra210_powergates[] = {
1714 [TEGRA_POWERGATE_CPU] = "crail",
1715 [TEGRA_POWERGATE_3D] = "3d",
1716 [TEGRA_POWERGATE_VENC] = "venc",
1717 [TEGRA_POWERGATE_PCIE] = "pcie",
1718 [TEGRA_POWERGATE_MPE] = "mpe",
1719 [TEGRA_POWERGATE_SATA] = "sata",
1720 [TEGRA_POWERGATE_CPU1] = "cpu1",
1721 [TEGRA_POWERGATE_CPU2] = "cpu2",
1722 [TEGRA_POWERGATE_CPU3] = "cpu3",
1723 [TEGRA_POWERGATE_CPU0] = "cpu0",
1724 [TEGRA_POWERGATE_C0NC] = "c0nc",
1725 [TEGRA_POWERGATE_SOR] = "sor",
1726 [TEGRA_POWERGATE_DIS] = "dis",
1727 [TEGRA_POWERGATE_DISB] = "disb",
1728 [TEGRA_POWERGATE_XUSBA] = "xusba",
1729 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1730 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1731 [TEGRA_POWERGATE_VIC] = "vic",
1732 [TEGRA_POWERGATE_IRAM] = "iram",
1733 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1734 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1735 [TEGRA_POWERGATE_AUD] = "aud",
1736 [TEGRA_POWERGATE_DFD] = "dfd",
1737 [TEGRA_POWERGATE_VE2] = "ve2",
1738 };
1739
1740 static const u8 tegra210_cpu_powergates[] = {
1741 TEGRA_POWERGATE_CPU0,
1742 TEGRA_POWERGATE_CPU1,
1743 TEGRA_POWERGATE_CPU2,
1744 TEGRA_POWERGATE_CPU3,
1745 };
1746
1747 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1748 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1749 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1750 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1751 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1752 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1753 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1754 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1755 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1756 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1757 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1758 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1759 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1760 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1761 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1762 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1763 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1764 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1765 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1766 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1767 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1768 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1769 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1770 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1771 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1772 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1773 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1774 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1775 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1776 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1777 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1778 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1779 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1780 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1781 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1782 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1783 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1784 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1785 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1786 };
1787
1788 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1789 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1790 .powergates = tegra210_powergates,
1791 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1792 .cpu_powergates = tegra210_cpu_powergates,
1793 .has_tsense_reset = true,
1794 .has_gpu_clamps = true,
1795 .has_impl_33v_pwr = false,
1796 .needs_mbist_war = true,
1797 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1798 .io_pads = tegra210_io_pads,
1799 .regs = &tegra20_pmc_regs,
1800 .init = tegra20_pmc_init,
1801 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1802 };
1803
1804 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
1805 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1806 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1807 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1808 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1809 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
1810 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
1811 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1812 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
1813 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1814 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1815 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1816 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1817 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1818 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1819 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1820 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
1821 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
1822 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
1823 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1824 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = 5 },
1825 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
1826 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX },
1827 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX },
1828 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX },
1829 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX },
1830 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
1831 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
1832 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
1833 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
1834 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
1835 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
1836 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = 2 },
1837 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
1838 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = 4 },
1839 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = 6 },
1840 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
1841 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 1 },
1842 { .id = TEGRA_IO_PAD_AO_HV, .dpd = UINT_MAX, .voltage = 0 },
1843 };
1844
1845 static const struct tegra_pmc_regs tegra186_pmc_regs = {
1846 .scratch0 = 0x2000,
1847 .dpd_req = 0x74,
1848 .dpd_status = 0x78,
1849 .dpd2_req = 0x7c,
1850 .dpd2_status = 0x80,
1851 };
1852
1853 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1854 struct device_node *np,
1855 bool invert)
1856 {
1857 struct resource regs;
1858 void __iomem *wake;
1859 u32 value;
1860 int index;
1861
1862 index = of_property_match_string(np, "reg-names", "wake");
1863 if (index < 0) {
1864 pr_err("failed to find PMC wake registers\n");
1865 return;
1866 }
1867
1868 of_address_to_resource(np, index, &regs);
1869
1870 wake = ioremap_nocache(regs.start, resource_size(&regs));
1871 if (!wake) {
1872 pr_err("failed to map PMC wake registers\n");
1873 return;
1874 }
1875
1876 value = readl(wake + WAKE_AOWAKE_CTRL);
1877
1878 if (invert)
1879 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
1880 else
1881 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
1882
1883 writel(value, wake + WAKE_AOWAKE_CTRL);
1884
1885 iounmap(wake);
1886 }
1887
1888 static const struct tegra_pmc_soc tegra186_pmc_soc = {
1889 .num_powergates = 0,
1890 .powergates = NULL,
1891 .num_cpu_powergates = 0,
1892 .cpu_powergates = NULL,
1893 .has_tsense_reset = false,
1894 .has_gpu_clamps = false,
1895 .has_impl_33v_pwr = true,
1896 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
1897 .io_pads = tegra186_io_pads,
1898 .regs = &tegra186_pmc_regs,
1899 .init = NULL,
1900 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
1901 };
1902
1903 static const struct of_device_id tegra_pmc_match[] = {
1904 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
1905 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
1906 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1907 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1908 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1909 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1910 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1911 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1912 { }
1913 };
1914
1915 static struct platform_driver tegra_pmc_driver = {
1916 .driver = {
1917 .name = "tegra-pmc",
1918 .suppress_bind_attrs = true,
1919 .of_match_table = tegra_pmc_match,
1920 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1921 .pm = &tegra_pmc_pm_ops,
1922 #endif
1923 },
1924 .probe = tegra_pmc_probe,
1925 };
1926 builtin_platform_driver(tegra_pmc_driver);
1927
1928 /*
1929 * Early initialization to allow access to registers in the very early boot
1930 * process.
1931 */
1932 static int __init tegra_pmc_early_init(void)
1933 {
1934 const struct of_device_id *match;
1935 struct device_node *np;
1936 struct resource regs;
1937 bool invert;
1938
1939 mutex_init(&pmc->powergates_lock);
1940
1941 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1942 if (!np) {
1943 /*
1944 * Fall back to legacy initialization for 32-bit ARM only. All
1945 * 64-bit ARM device tree files for Tegra are required to have
1946 * a PMC node.
1947 *
1948 * This is for backwards-compatibility with old device trees
1949 * that didn't contain a PMC node. Note that in this case the
1950 * SoC data can't be matched and therefore powergating is
1951 * disabled.
1952 */
1953 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1954 pr_warn("DT node not found, powergating disabled\n");
1955
1956 regs.start = 0x7000e400;
1957 regs.end = 0x7000e7ff;
1958 regs.flags = IORESOURCE_MEM;
1959
1960 pr_warn("Using memory region %pR\n", &regs);
1961 } else {
1962 /*
1963 * At this point we're not running on Tegra, so play
1964 * nice with multi-platform kernels.
1965 */
1966 return 0;
1967 }
1968 } else {
1969 /*
1970 * Extract information from the device tree if we've found a
1971 * matching node.
1972 */
1973 if (of_address_to_resource(np, 0, &regs) < 0) {
1974 pr_err("failed to get PMC registers\n");
1975 of_node_put(np);
1976 return -ENXIO;
1977 }
1978 }
1979
1980 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
1981 if (!pmc->base) {
1982 pr_err("failed to map PMC registers\n");
1983 of_node_put(np);
1984 return -ENXIO;
1985 }
1986
1987 if (np) {
1988 pmc->soc = match->data;
1989
1990 tegra_powergate_init(pmc, np);
1991
1992 /*
1993 * Invert the interrupt polarity if a PMC device tree node
1994 * exists and contains the nvidia,invert-interrupt property.
1995 */
1996 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1997
1998 pmc->soc->setup_irq_polarity(pmc, np, invert);
1999
2000 of_node_put(np);
2001 }
2002
2003 return 0;
2004 }
2005 early_initcall(tegra_pmc_early_init);
Linux with added FPC-III support