drivers/spi/spi-dw-mmio.c

   1 /*
   2  * Memory-mapped interface driver for DW SPI Core
   3  *
   4  * Copyright (c) 2010, Octasic semiconductor.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/scatterlist.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/property.h>
  24 #include <linux/regmap.h>
  25
  26 #include "spi-dw.h"
  27
  28 #define DRIVER_NAME "dw_spi_mmio"
  29
  30 struct dw_spi_mmio {
  31         struct dw_spi  dws;
  32         struct clk     *clk;
  33         void           *priv;
  34 };
  35
  36 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL       0x24
  37 #define OCELOT_IF_SI_OWNER_MASK                 GENMASK(5, 4)
  38 #define OCELOT_IF_SI_OWNER_OFFSET               4
  39 #define MSCC_IF_SI_OWNER_SISL                   0
  40 #define MSCC_IF_SI_OWNER_SIBM                   1
  41 #define MSCC_IF_SI_OWNER_SIMC                   2
  42
  43 #define MSCC_SPI_MST_SW_MODE                    0x14
  44 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE   BIT(13)
  45 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)       (x << 5)
  46
  47 struct dw_spi_mscc {
  48         struct regmap       *syscon;
  49         void __iomem        *spi_mst;
  50 };
  51
  52 /*
  53  * The Designware SPI controller (referred to as master in the documentation)
  54  * automatically deasserts chip select when the tx fifo is empty. The chip
  55  * selects then needs to be either driven as GPIOs or, for the first 4 using the
  56  * the SPI boot controller registers. the final chip select is an OR gate
  57  * between the Designware SPI controller and the SPI boot controller.
  58  */
  59 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
  60 {
  61         struct dw_spi *dws = spi_master_get_devdata(spi->master);
  62         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  63         struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  64         u32 cs = spi->chip_select;
  65
  66         if (cs < 4) {
  67                 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
  68
  69                 if (!enable)
  70                         sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
  71
  72                 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  73         }
  74
  75         dw_spi_set_cs(spi, enable);
  76 }
  77
  78 static int dw_spi_mscc_init(struct platform_device *pdev,
  79                             struct dw_spi_mmio *dwsmmio)
  80 {
  81         struct dw_spi_mscc *dwsmscc;
  82         struct resource *res;
  83
  84         dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
  85         if (!dwsmscc)
  86                 return -ENOMEM;
  87
  88         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  89         dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
  90         if (IS_ERR(dwsmscc->spi_mst)) {
  91                 dev_err(&pdev->dev, "SPI_MST region map failed\n");
  92                 return PTR_ERR(dwsmscc->spi_mst);
  93         }
  94
  95         dwsmscc->syscon = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
  96         if (IS_ERR(dwsmscc->syscon))
  97                 return PTR_ERR(dwsmscc->syscon);
  98
  99         /* Deassert all CS */
 100         writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
 101
 102         /* Select the owner of the SI interface */
 103         regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
 104                            OCELOT_IF_SI_OWNER_MASK,
 105                            MSCC_IF_SI_OWNER_SIMC << OCELOT_IF_SI_OWNER_OFFSET);
 106
 107         dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
 108         dwsmmio->priv = dwsmscc;
 109
 110         return 0;
 111 }
 112
 113 static int dw_spi_mmio_probe(struct platform_device *pdev)
 114 {
 115         int (*init_func)(struct platform_device *pdev,
 116                          struct dw_spi_mmio *dwsmmio);
 117         struct dw_spi_mmio *dwsmmio;
 118         struct dw_spi *dws;
 119         struct resource *mem;
 120         int ret;
 121         int num_cs;
 122
 123         dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
 124                         GFP_KERNEL);
 125         if (!dwsmmio)
 126                 return -ENOMEM;
 127
 128         dws = &dwsmmio->dws;
 129
 130         /* Get basic io resource and map it */
 131         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 132         dws->regs = devm_ioremap_resource(&pdev->dev, mem);
 133         if (IS_ERR(dws->regs)) {
 134                 dev_err(&pdev->dev, "SPI region map failed\n");
 135                 return PTR_ERR(dws->regs);
 136         }
 137
 138         dws->irq = platform_get_irq(pdev, 0);
 139         if (dws->irq < 0) {
 140                 dev_err(&pdev->dev, "no irq resource?\n");
 141                 return dws->irq; /* -ENXIO */
 142         }
 143
 144         dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
 145         if (IS_ERR(dwsmmio->clk))
 146                 return PTR_ERR(dwsmmio->clk);
 147         ret = clk_prepare_enable(dwsmmio->clk);
 148         if (ret)
 149                 return ret;
 150
 151         dws->bus_num = pdev->id;
 152
 153         dws->max_freq = clk_get_rate(dwsmmio->clk);
 154
 155         device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
 156
 157         num_cs = 4;
 158
 159         device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
 160
 161         dws->num_cs = num_cs;
 162
 163         if (pdev->dev.of_node) {
 164                 int i;
 165
 166                 for (i = 0; i < dws->num_cs; i++) {
 167                         int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
 168                                         "cs-gpios", i);
 169
 170                         if (cs_gpio == -EPROBE_DEFER) {
 171                                 ret = cs_gpio;
 172                                 goto out;
 173                         }
 174
 175                         if (gpio_is_valid(cs_gpio)) {
 176                                 ret = devm_gpio_request(&pdev->dev, cs_gpio,
 177                                                 dev_name(&pdev->dev));
 178                                 if (ret)
 179                                         goto out;
 180                         }
 181                 }
 182         }
 183
 184         init_func = device_get_match_data(&pdev->dev);
 185         if (init_func) {
 186                 ret = init_func(pdev, dwsmmio);
 187                 if (ret)
 188                         goto out;
 189         }
 190
 191         ret = dw_spi_add_host(&pdev->dev, dws);
 192         if (ret)
 193                 goto out;
 194
 195         platform_set_drvdata(pdev, dwsmmio);
 196         return 0;
 197
 198 out:
 199         clk_disable_unprepare(dwsmmio->clk);
 200         return ret;
 201 }
 202
 203 static int dw_spi_mmio_remove(struct platform_device *pdev)
 204 {
 205         struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
 206
 207         dw_spi_remove_host(&dwsmmio->dws);
 208         clk_disable_unprepare(dwsmmio->clk);
 209
 210         return 0;
 211 }
 212
 213 static const struct of_device_id dw_spi_mmio_of_match[] = {
 214         { .compatible = "snps,dw-apb-ssi", },
 215         { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_init},
 216         { /* end of table */}
 217 };
 218 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
 219
 220 static struct platform_driver dw_spi_mmio_driver = {
 221         .probe          = dw_spi_mmio_probe,
 222         .remove         = dw_spi_mmio_remove,
 223         .driver         = {
 224                 .name   = DRIVER_NAME,
 225                 .of_match_table = dw_spi_mmio_of_match,
 226         },
 227 };
 228 module_platform_driver(dw_spi_mmio_driver);
 229
 230 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
 231 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
 232 MODULE_LICENSE("GPL v2");