drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/scatterlist.h>
  25
  26 #define DRIVER_NAME "rockchip-spi"
  27
  28 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  29                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  30 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  31                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 #define RXBUSY                                          (1 << 0)
 146 #define TXBUSY                                          (1 << 1)
 147
 148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 149 #define MAX_SCLK_OUT            50000000
 150
 151 /*
 152  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 153  * the controller seems to hang when given 0x10000, so stick with this for now.
 154  */
 155 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 156
 157 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 158
 159 enum rockchip_ssi_type {
 160         SSI_MOTO_SPI = 0,
 161         SSI_TI_SSP,
 162         SSI_NS_MICROWIRE,
 163 };
 164
 165 struct rockchip_spi_dma_data {
 166         struct dma_chan *ch;
 167         enum dma_transfer_direction direction;
 168         dma_addr_t addr;
 169 };
 170
 171 struct rockchip_spi {
 172         struct device *dev;
 173         struct spi_master *master;
 174
 175         struct clk *spiclk;
 176         struct clk *apb_pclk;
 177
 178         void __iomem *regs;
 179         /*depth of the FIFO buffer */
 180         u32 fifo_len;
 181         /* max bus freq supported */
 182         u32 max_freq;
 183         /* supported slave numbers */
 184         enum rockchip_ssi_type type;
 185
 186         u16 mode;
 187         u8 tmode;
 188         u8 bpw;
 189         u8 n_bytes;
 190         u32 rsd_nsecs;
 191         unsigned len;
 192         u32 speed;
 193
 194         const void *tx;
 195         const void *tx_end;
 196         void *rx;
 197         void *rx_end;
 198
 199         u32 state;
 200         /* protect state */
 201         spinlock_t lock;
 202
 203         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 204
 205         u32 use_dma;
 206         struct sg_table tx_sg;
 207         struct sg_table rx_sg;
 208         struct rockchip_spi_dma_data dma_rx;
 209         struct rockchip_spi_dma_data dma_tx;
 210         struct dma_slave_caps dma_caps;
 211 };
 212
 213 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
 214 {
 215         writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
 216 }
 217
 218 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 219 {
 220         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 221 }
 222
 223 static inline void flush_fifo(struct rockchip_spi *rs)
 224 {
 225         while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
 226                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 227 }
 228
 229 static inline void wait_for_idle(struct rockchip_spi *rs)
 230 {
 231         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 232
 233         do {
 234                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 235                         return;
 236         } while (!time_after(jiffies, timeout));
 237
 238         dev_warn(rs->dev, "spi controller is in busy state!\n");
 239 }
 240
 241 static u32 get_fifo_len(struct rockchip_spi *rs)
 242 {
 243         u32 fifo;
 244
 245         for (fifo = 2; fifo < 32; fifo++) {
 246                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 247                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 248                         break;
 249         }
 250
 251         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 252
 253         return (fifo == 31) ? 0 : fifo;
 254 }
 255
 256 static inline u32 tx_max(struct rockchip_spi *rs)
 257 {
 258         u32 tx_left, tx_room;
 259
 260         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 261         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 262
 263         return min(tx_left, tx_room);
 264 }
 265
 266 static inline u32 rx_max(struct rockchip_spi *rs)
 267 {
 268         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 269         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 270
 271         return min(rx_left, rx_room);
 272 }
 273
 274 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 275 {
 276         struct spi_master *master = spi->master;
 277         struct rockchip_spi *rs = spi_master_get_devdata(master);
 278         bool cs_asserted = !enable;
 279
 280         /* Return immediately for no-op */
 281         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 282                 return;
 283
 284         if (cs_asserted) {
 285                 /* Keep things powered as long as CS is asserted */
 286                 pm_runtime_get_sync(rs->dev);
 287
 288                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 289                                       BIT(spi->chip_select));
 290         } else {
 291                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 292                                       BIT(spi->chip_select));
 293
 294                 /* Drop reference from when we first asserted CS */
 295                 pm_runtime_put(rs->dev);
 296         }
 297
 298         rs->cs_asserted[spi->chip_select] = cs_asserted;
 299 }
 300
 301 static int rockchip_spi_prepare_message(struct spi_master *master,
 302                                         struct spi_message *msg)
 303 {
 304         struct rockchip_spi *rs = spi_master_get_devdata(master);
 305         struct spi_device *spi = msg->spi;
 306
 307         rs->mode = spi->mode;
 308
 309         return 0;
 310 }
 311
 312 static void rockchip_spi_handle_err(struct spi_master *master,
 313                                     struct spi_message *msg)
 314 {
 315         unsigned long flags;
 316         struct rockchip_spi *rs = spi_master_get_devdata(master);
 317
 318         spin_lock_irqsave(&rs->lock, flags);
 319
 320         /*
 321          * For DMA mode, we need terminate DMA channel and flush
 322          * fifo for the next transfer if DMA thansfer timeout.
 323          * handle_err() was called by core if transfer failed.
 324          * Maybe it is reasonable for error handling here.
 325          */
 326         if (rs->use_dma) {
 327                 if (rs->state & RXBUSY) {
 328                         dmaengine_terminate_async(rs->dma_rx.ch);
 329                         flush_fifo(rs);
 330                 }
 331
 332                 if (rs->state & TXBUSY)
 333                         dmaengine_terminate_async(rs->dma_tx.ch);
 334         }
 335
 336         spin_unlock_irqrestore(&rs->lock, flags);
 337 }
 338
 339 static int rockchip_spi_unprepare_message(struct spi_master *master,
 340                                           struct spi_message *msg)
 341 {
 342         struct rockchip_spi *rs = spi_master_get_devdata(master);
 343
 344         spi_enable_chip(rs, 0);
 345
 346         return 0;
 347 }
 348
 349 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 350 {
 351         u32 max = tx_max(rs);
 352         u32 txw = 0;
 353
 354         while (max--) {
 355                 if (rs->n_bytes == 1)
 356                         txw = *(u8 *)(rs->tx);
 357                 else
 358                         txw = *(u16 *)(rs->tx);
 359
 360                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 361                 rs->tx += rs->n_bytes;
 362         }
 363 }
 364
 365 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 366 {
 367         u32 max = rx_max(rs);
 368         u32 rxw;
 369
 370         while (max--) {
 371                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 372                 if (rs->n_bytes == 1)
 373                         *(u8 *)(rs->rx) = (u8)rxw;
 374                 else
 375                         *(u16 *)(rs->rx) = (u16)rxw;
 376                 rs->rx += rs->n_bytes;
 377         }
 378 }
 379
 380 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 381 {
 382         int remain = 0;
 383
 384         do {
 385                 if (rs->tx) {
 386                         remain = rs->tx_end - rs->tx;
 387                         rockchip_spi_pio_writer(rs);
 388                 }
 389
 390                 if (rs->rx) {
 391                         remain = rs->rx_end - rs->rx;
 392                         rockchip_spi_pio_reader(rs);
 393                 }
 394
 395                 cpu_relax();
 396         } while (remain);
 397
 398         /* If tx, wait until the FIFO data completely. */
 399         if (rs->tx)
 400                 wait_for_idle(rs);
 401
 402         spi_enable_chip(rs, 0);
 403
 404         return 0;
 405 }
 406
 407 static void rockchip_spi_dma_rxcb(void *data)
 408 {
 409         unsigned long flags;
 410         struct rockchip_spi *rs = data;
 411
 412         spin_lock_irqsave(&rs->lock, flags);
 413
 414         rs->state &= ~RXBUSY;
 415         if (!(rs->state & TXBUSY)) {
 416                 spi_enable_chip(rs, 0);
 417                 spi_finalize_current_transfer(rs->master);
 418         }
 419
 420         spin_unlock_irqrestore(&rs->lock, flags);
 421 }
 422
 423 static void rockchip_spi_dma_txcb(void *data)
 424 {
 425         unsigned long flags;
 426         struct rockchip_spi *rs = data;
 427
 428         /* Wait until the FIFO data completely. */
 429         wait_for_idle(rs);
 430
 431         spin_lock_irqsave(&rs->lock, flags);
 432
 433         rs->state &= ~TXBUSY;
 434         if (!(rs->state & RXBUSY)) {
 435                 spi_enable_chip(rs, 0);
 436                 spi_finalize_current_transfer(rs->master);
 437         }
 438
 439         spin_unlock_irqrestore(&rs->lock, flags);
 440 }
 441
 442 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
 443 {
 444         unsigned long flags;
 445         struct dma_slave_config rxconf, txconf;
 446         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 447
 448         memset(&rxconf, 0, sizeof(rxconf));
 449         memset(&txconf, 0, sizeof(txconf));
 450
 451         spin_lock_irqsave(&rs->lock, flags);
 452         rs->state &= ~RXBUSY;
 453         rs->state &= ~TXBUSY;
 454         spin_unlock_irqrestore(&rs->lock, flags);
 455
 456         rxdesc = NULL;
 457         if (rs->rx) {
 458                 rxconf.direction = rs->dma_rx.direction;
 459                 rxconf.src_addr = rs->dma_rx.addr;
 460                 rxconf.src_addr_width = rs->n_bytes;
 461                 if (rs->dma_caps.max_burst > 4)
 462                         rxconf.src_maxburst = 4;
 463                 else
 464                         rxconf.src_maxburst = 1;
 465                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 466
 467                 rxdesc = dmaengine_prep_slave_sg(
 468                                 rs->dma_rx.ch,
 469                                 rs->rx_sg.sgl, rs->rx_sg.nents,
 470                                 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
 471                 if (!rxdesc)
 472                         return -EINVAL;
 473
 474                 rxdesc->callback = rockchip_spi_dma_rxcb;
 475                 rxdesc->callback_param = rs;
 476         }
 477
 478         txdesc = NULL;
 479         if (rs->tx) {
 480                 txconf.direction = rs->dma_tx.direction;
 481                 txconf.dst_addr = rs->dma_tx.addr;
 482                 txconf.dst_addr_width = rs->n_bytes;
 483                 if (rs->dma_caps.max_burst > 4)
 484                         txconf.dst_maxburst = 4;
 485                 else
 486                         txconf.dst_maxburst = 1;
 487                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 488
 489                 txdesc = dmaengine_prep_slave_sg(
 490                                 rs->dma_tx.ch,
 491                                 rs->tx_sg.sgl, rs->tx_sg.nents,
 492                                 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
 493                 if (!txdesc) {
 494                         if (rxdesc)
 495                                 dmaengine_terminate_sync(rs->dma_rx.ch);
 496                         return -EINVAL;
 497                 }
 498
 499                 txdesc->callback = rockchip_spi_dma_txcb;
 500                 txdesc->callback_param = rs;
 501         }
 502
 503         /* rx must be started before tx due to spi instinct */
 504         if (rxdesc) {
 505                 spin_lock_irqsave(&rs->lock, flags);
 506                 rs->state |= RXBUSY;
 507                 spin_unlock_irqrestore(&rs->lock, flags);
 508                 dmaengine_submit(rxdesc);
 509                 dma_async_issue_pending(rs->dma_rx.ch);
 510         }
 511
 512         if (txdesc) {
 513                 spin_lock_irqsave(&rs->lock, flags);
 514                 rs->state |= TXBUSY;
 515                 spin_unlock_irqrestore(&rs->lock, flags);
 516                 dmaengine_submit(txdesc);
 517                 dma_async_issue_pending(rs->dma_tx.ch);
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void rockchip_spi_config(struct rockchip_spi *rs)
 524 {
 525         u32 div = 0;
 526         u32 dmacr = 0;
 527         int rsd = 0;
 528
 529         u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
 530                 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
 531                 | (CR0_EM_BIG << CR0_EM_OFFSET);
 532
 533         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 534         cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
 535         cr0 |= (rs->tmode << CR0_XFM_OFFSET);
 536         cr0 |= (rs->type << CR0_FRF_OFFSET);
 537
 538         if (rs->use_dma) {
 539                 if (rs->tx)
 540                         dmacr |= TF_DMA_EN;
 541                 if (rs->rx)
 542                         dmacr |= RF_DMA_EN;
 543         }
 544
 545         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 546                 rs->speed = MAX_SCLK_OUT;
 547
 548         /* the minimum divisor is 2 */
 549         if (rs->max_freq < 2 * rs->speed) {
 550                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 551                 rs->max_freq = clk_get_rate(rs->spiclk);
 552         }
 553
 554         /* div doesn't support odd number */
 555         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 556         div = (div + 1) & 0xfffe;
 557
 558         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 559         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 560                                 1000000000 >> 8);
 561         if (!rsd && rs->rsd_nsecs) {
 562                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 563                              rs->max_freq, rs->rsd_nsecs);
 564         } else if (rsd > 3) {
 565                 rsd = 3;
 566                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 567                              rs->max_freq, rs->rsd_nsecs,
 568                              rsd * 1000000000U / rs->max_freq);
 569         }
 570         cr0 |= rsd << CR0_RSD_OFFSET;
 571
 572         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 573
 574         if (rs->n_bytes == 1)
 575                 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 576         else if (rs->n_bytes == 2)
 577                 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 578         else
 579                 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 580
 581         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 582         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 583
 584         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
 585         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 586         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 587
 588         spi_set_clk(rs, div);
 589
 590         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 591 }
 592
 593 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 594 {
 595         return ROCKCHIP_SPI_MAX_TRANLEN;
 596 }
 597
 598 static int rockchip_spi_transfer_one(
 599                 struct spi_master *master,
 600                 struct spi_device *spi,
 601                 struct spi_transfer *xfer)
 602 {
 603         int ret = 0;
 604         struct rockchip_spi *rs = spi_master_get_devdata(master);
 605
 606         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 607                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 608
 609         if (!xfer->tx_buf && !xfer->rx_buf) {
 610                 dev_err(rs->dev, "No buffer for transfer\n");
 611                 return -EINVAL;
 612         }
 613
 614         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 615                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 616                 return -EINVAL;
 617         }
 618
 619         rs->speed = xfer->speed_hz;
 620         rs->bpw = xfer->bits_per_word;
 621         rs->n_bytes = rs->bpw >> 3;
 622
 623         rs->tx = xfer->tx_buf;
 624         rs->tx_end = rs->tx + xfer->len;
 625         rs->rx = xfer->rx_buf;
 626         rs->rx_end = rs->rx + xfer->len;
 627         rs->len = xfer->len;
 628
 629         rs->tx_sg = xfer->tx_sg;
 630         rs->rx_sg = xfer->rx_sg;
 631
 632         if (rs->tx && rs->rx)
 633                 rs->tmode = CR0_XFM_TR;
 634         else if (rs->tx)
 635                 rs->tmode = CR0_XFM_TO;
 636         else if (rs->rx)
 637                 rs->tmode = CR0_XFM_RO;
 638
 639         /* we need prepare dma before spi was enabled */
 640         if (master->can_dma && master->can_dma(master, spi, xfer))
 641                 rs->use_dma = 1;
 642         else
 643                 rs->use_dma = 0;
 644
 645         rockchip_spi_config(rs);
 646
 647         if (rs->use_dma) {
 648                 if (rs->tmode == CR0_XFM_RO) {
 649                         /* rx: dma must be prepared first */
 650                         ret = rockchip_spi_prepare_dma(rs);
 651                         spi_enable_chip(rs, 1);
 652                 } else {
 653                         /* tx or tr: spi must be enabled first */
 654                         spi_enable_chip(rs, 1);
 655                         ret = rockchip_spi_prepare_dma(rs);
 656                 }
 657                 /* successful DMA prepare means the transfer is in progress */
 658                 ret = ret ? ret : 1;
 659         } else {
 660                 spi_enable_chip(rs, 1);
 661                 ret = rockchip_spi_pio_transfer(rs);
 662         }
 663
 664         return ret;
 665 }
 666
 667 static bool rockchip_spi_can_dma(struct spi_master *master,
 668                                  struct spi_device *spi,
 669                                  struct spi_transfer *xfer)
 670 {
 671         struct rockchip_spi *rs = spi_master_get_devdata(master);
 672
 673         return (xfer->len > rs->fifo_len);
 674 }
 675
 676 static int rockchip_spi_probe(struct platform_device *pdev)
 677 {
 678         int ret;
 679         struct rockchip_spi *rs;
 680         struct spi_master *master;
 681         struct resource *mem;
 682         u32 rsd_nsecs;
 683
 684         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 685         if (!master)
 686                 return -ENOMEM;
 687
 688         platform_set_drvdata(pdev, master);
 689
 690         rs = spi_master_get_devdata(master);
 691
 692         /* Get basic io resource and map it */
 693         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 694         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 695         if (IS_ERR(rs->regs)) {
 696                 ret =  PTR_ERR(rs->regs);
 697                 goto err_put_master;
 698         }
 699
 700         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 701         if (IS_ERR(rs->apb_pclk)) {
 702                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 703                 ret = PTR_ERR(rs->apb_pclk);
 704                 goto err_put_master;
 705         }
 706
 707         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 708         if (IS_ERR(rs->spiclk)) {
 709                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 710                 ret = PTR_ERR(rs->spiclk);
 711                 goto err_put_master;
 712         }
 713
 714         ret = clk_prepare_enable(rs->apb_pclk);
 715         if (ret < 0) {
 716                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 717                 goto err_put_master;
 718         }
 719
 720         ret = clk_prepare_enable(rs->spiclk);
 721         if (ret < 0) {
 722                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 723                 goto err_disable_apbclk;
 724         }
 725
 726         spi_enable_chip(rs, 0);
 727
 728         rs->type = SSI_MOTO_SPI;
 729         rs->master = master;
 730         rs->dev = &pdev->dev;
 731         rs->max_freq = clk_get_rate(rs->spiclk);
 732
 733         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 734                                   &rsd_nsecs))
 735                 rs->rsd_nsecs = rsd_nsecs;
 736
 737         rs->fifo_len = get_fifo_len(rs);
 738         if (!rs->fifo_len) {
 739                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 740                 ret = -EINVAL;
 741                 goto err_disable_spiclk;
 742         }
 743
 744         spin_lock_init(&rs->lock);
 745
 746         pm_runtime_set_active(&pdev->dev);
 747         pm_runtime_enable(&pdev->dev);
 748
 749         master->auto_runtime_pm = true;
 750         master->bus_num = pdev->id;
 751         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 752         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 753         master->dev.of_node = pdev->dev.of_node;
 754         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 755
 756         master->set_cs = rockchip_spi_set_cs;
 757         master->prepare_message = rockchip_spi_prepare_message;
 758         master->unprepare_message = rockchip_spi_unprepare_message;
 759         master->transfer_one = rockchip_spi_transfer_one;
 760         master->max_transfer_size = rockchip_spi_max_transfer_size;
 761         master->handle_err = rockchip_spi_handle_err;
 762         master->flags = SPI_MASTER_GPIO_SS;
 763
 764         rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
 765         if (IS_ERR(rs->dma_tx.ch)) {
 766                 /* Check tx to see if we need defer probing driver */
 767                 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
 768                         ret = -EPROBE_DEFER;
 769                         goto err_disable_pm_runtime;
 770                 }
 771                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 772                 rs->dma_tx.ch = NULL;
 773         }
 774
 775         rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
 776         if (IS_ERR(rs->dma_rx.ch)) {
 777                 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
 778                         ret = -EPROBE_DEFER;
 779                         goto err_free_dma_tx;
 780                 }
 781                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 782                 rs->dma_rx.ch = NULL;
 783         }
 784
 785         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 786                 dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps));
 787                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 788                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 789                 rs->dma_tx.direction = DMA_MEM_TO_DEV;
 790                 rs->dma_rx.direction = DMA_DEV_TO_MEM;
 791
 792                 master->can_dma = rockchip_spi_can_dma;
 793                 master->dma_tx = rs->dma_tx.ch;
 794                 master->dma_rx = rs->dma_rx.ch;
 795         }
 796
 797         ret = devm_spi_register_master(&pdev->dev, master);
 798         if (ret < 0) {
 799                 dev_err(&pdev->dev, "Failed to register master\n");
 800                 goto err_free_dma_rx;
 801         }
 802
 803         return 0;
 804
 805 err_free_dma_rx:
 806         if (rs->dma_rx.ch)
 807                 dma_release_channel(rs->dma_rx.ch);
 808 err_free_dma_tx:
 809         if (rs->dma_tx.ch)
 810                 dma_release_channel(rs->dma_tx.ch);
 811 err_disable_pm_runtime:
 812         pm_runtime_disable(&pdev->dev);
 813 err_disable_spiclk:
 814         clk_disable_unprepare(rs->spiclk);
 815 err_disable_apbclk:
 816         clk_disable_unprepare(rs->apb_pclk);
 817 err_put_master:
 818         spi_master_put(master);
 819
 820         return ret;
 821 }
 822
 823 static int rockchip_spi_remove(struct platform_device *pdev)
 824 {
 825         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 826         struct rockchip_spi *rs = spi_master_get_devdata(master);
 827
 828         pm_runtime_get_sync(&pdev->dev);
 829
 830         clk_disable_unprepare(rs->spiclk);
 831         clk_disable_unprepare(rs->apb_pclk);
 832
 833         pm_runtime_put_noidle(&pdev->dev);
 834         pm_runtime_disable(&pdev->dev);
 835         pm_runtime_set_suspended(&pdev->dev);
 836
 837         if (rs->dma_tx.ch)
 838                 dma_release_channel(rs->dma_tx.ch);
 839         if (rs->dma_rx.ch)
 840                 dma_release_channel(rs->dma_rx.ch);
 841
 842         spi_master_put(master);
 843
 844         return 0;
 845 }
 846
 847 #ifdef CONFIG_PM_SLEEP
 848 static int rockchip_spi_suspend(struct device *dev)
 849 {
 850         int ret;
 851         struct spi_master *master = dev_get_drvdata(dev);
 852         struct rockchip_spi *rs = spi_master_get_devdata(master);
 853
 854         ret = spi_master_suspend(rs->master);
 855         if (ret < 0)
 856                 return ret;
 857
 858         ret = pm_runtime_force_suspend(dev);
 859         if (ret < 0)
 860                 return ret;
 861
 862         pinctrl_pm_select_sleep_state(dev);
 863
 864         return 0;
 865 }
 866
 867 static int rockchip_spi_resume(struct device *dev)
 868 {
 869         int ret;
 870         struct spi_master *master = dev_get_drvdata(dev);
 871         struct rockchip_spi *rs = spi_master_get_devdata(master);
 872
 873         pinctrl_pm_select_default_state(dev);
 874
 875         ret = pm_runtime_force_resume(dev);
 876         if (ret < 0)
 877                 return ret;
 878
 879         ret = spi_master_resume(rs->master);
 880         if (ret < 0) {
 881                 clk_disable_unprepare(rs->spiclk);
 882                 clk_disable_unprepare(rs->apb_pclk);
 883         }
 884
 885         return 0;
 886 }
 887 #endif /* CONFIG_PM_SLEEP */
 888
 889 #ifdef CONFIG_PM
 890 static int rockchip_spi_runtime_suspend(struct device *dev)
 891 {
 892         struct spi_master *master = dev_get_drvdata(dev);
 893         struct rockchip_spi *rs = spi_master_get_devdata(master);
 894
 895         clk_disable_unprepare(rs->spiclk);
 896         clk_disable_unprepare(rs->apb_pclk);
 897
 898         return 0;
 899 }
 900
 901 static int rockchip_spi_runtime_resume(struct device *dev)
 902 {
 903         int ret;
 904         struct spi_master *master = dev_get_drvdata(dev);
 905         struct rockchip_spi *rs = spi_master_get_devdata(master);
 906
 907         ret = clk_prepare_enable(rs->apb_pclk);
 908         if (ret < 0)
 909                 return ret;
 910
 911         ret = clk_prepare_enable(rs->spiclk);
 912         if (ret < 0)
 913                 clk_disable_unprepare(rs->apb_pclk);
 914
 915         return 0;
 916 }
 917 #endif /* CONFIG_PM */
 918
 919 static const struct dev_pm_ops rockchip_spi_pm = {
 920         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 921         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 922                            rockchip_spi_runtime_resume, NULL)
 923 };
 924
 925 static const struct of_device_id rockchip_spi_dt_match[] = {
 926         { .compatible = "rockchip,rv1108-spi", },
 927         { .compatible = "rockchip,rk3036-spi", },
 928         { .compatible = "rockchip,rk3066-spi", },
 929         { .compatible = "rockchip,rk3188-spi", },
 930         { .compatible = "rockchip,rk3228-spi", },
 931         { .compatible = "rockchip,rk3288-spi", },
 932         { .compatible = "rockchip,rk3368-spi", },
 933         { .compatible = "rockchip,rk3399-spi", },
 934         { },
 935 };
 936 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 937
 938 static struct platform_driver rockchip_spi_driver = {
 939         .driver = {
 940                 .name   = DRIVER_NAME,
 941                 .pm = &rockchip_spi_pm,
 942                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 943         },
 944         .probe = rockchip_spi_probe,
 945         .remove = rockchip_spi_remove,
 946 };
 947
 948 module_platform_driver(rockchip_spi_driver);
 949
 950 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 951 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 952 MODULE_LICENSE("GPL v2");