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Linux 4.19.133
[linux/fpc-iii.git] / drivers / spi / spi-rspi.c
blobd61120822f026308269bd2a89bedd7b55bf8b7d5
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sh_dma.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/rspi.h>
35
36 #define RSPI_SPCR 0x00 /* Control Register */
37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
38 #define RSPI_SPPCR 0x02 /* Pin Control Register */
39 #define RSPI_SPSR 0x03 /* Status Register */
40 #define RSPI_SPDR 0x04 /* Data Register */
41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
43 #define RSPI_SPBR 0x0a /* Bit Rate Register */
44 #define RSPI_SPDCR 0x0b /* Data Control Register */
45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
58 #define RSPI_NUM_SPCMD 8
59 #define RSPI_RZ_NUM_SPCMD 4
60 #define QSPI_NUM_SPCMD 4
61
62 /* RSPI on RZ only */
63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
65
66 /* QSPI only */
67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
74
75 /* SPCR - Control Register */
76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
77 #define SPCR_SPE 0x40 /* Function Enable */
78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
82 /* RSPI on SH only */
83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
85 /* QSPI on R-Car Gen2 only */
86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88
89 /* SSLP - Slave Select Polarity Register */
90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
92
93 /* SPPCR - Pin Control Register */
94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
96 #define SPPCR_SPOM 0x04
97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
99
100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
102
103 /* SPSR - Status Register */
104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
105 #define SPSR_TEND 0x40 /* Transmit End */
106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
107 #define SPSR_PERF 0x08 /* Parity Error Flag */
108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
111
112 /* SPSCR - Sequence Control Register */
113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
114
115 /* SPSSR - Sequence Status Register */
116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
118
119 /* SPDCR - Data Control Register */
120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
124 #define SPDCR_SPLWORD SPDCR_SPLW1
125 #define SPDCR_SPLBYTE SPDCR_SPLW0
126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
128 #define SPDCR_SLSEL1 0x08
129 #define SPDCR_SLSEL0 0x04
130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
131 #define SPDCR_SPFC1 0x02
132 #define SPDCR_SPFC0 0x01
133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
134
135 /* SPCKD - Clock Delay Register */
136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
137
138 /* SSLND - Slave Select Negation Delay Register */
139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
140
141 /* SPND - Next-Access Delay Register */
142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
143
144 /* SPCR2 - Control Register 2 */
145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
148 #define SPCR2_SPPE 0x01 /* Parity Enable */
149
150 /* SPCMDn - Command Registers */
151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
154 #define SPCMD_LSBF 0x1000 /* LSB First */
155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
158 #define SPCMD_SPB_16BIT 0x0100
159 #define SPCMD_SPB_20BIT 0x0000
160 #define SPCMD_SPB_24BIT 0x0100
161 #define SPCMD_SPB_32BIT 0x0200
162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
164 #define SPCMD_SPIMOD1 0x0040
165 #define SPCMD_SPIMOD0 0x0020
166 #define SPCMD_SPIMOD_SINGLE 0
167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174
175 /* SPBFCR - Buffer Control Register */
176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180 /* QSPI on R-Car Gen2 */
181 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186 #define QSPI_BUFFER_SIZE 32u
187
188 struct rspi_data {
189 void __iomem *addr;
190 u32 max_speed_hz;
191 struct spi_master *master;
192 wait_queue_head_t wait;
193 struct clk *clk;
194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
198 const struct spi_ops *ops;
199
200 unsigned dma_callbacked:1;
201 unsigned byte_access:1;
202 };
203
204 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
205 {
206 iowrite8(data, rspi->addr + offset);
207 }
208
209 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
210 {
211 iowrite16(data, rspi->addr + offset);
212 }
213
214 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
215 {
216 iowrite32(data, rspi->addr + offset);
217 }
218
219 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
220 {
221 return ioread8(rspi->addr + offset);
222 }
223
224 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
225 {
226 return ioread16(rspi->addr + offset);
227 }
228
229 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
230 {
231 if (rspi->byte_access)
232 rspi_write8(rspi, data, RSPI_SPDR);
233 else /* 16 bit */
234 rspi_write16(rspi, data, RSPI_SPDR);
235 }
236
237 static u16 rspi_read_data(const struct rspi_data *rspi)
238 {
239 if (rspi->byte_access)
240 return rspi_read8(rspi, RSPI_SPDR);
241 else /* 16 bit */
242 return rspi_read16(rspi, RSPI_SPDR);
243 }
244
245 /* optional functions */
246 struct spi_ops {
247 int (*set_config_register)(struct rspi_data *rspi, int access_size);
248 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
249 struct spi_transfer *xfer);
250 u16 mode_bits;
251 u16 flags;
252 u16 fifo_size;
253 };
254
255 /*
256 * functions for RSPI on legacy SH
257 */
258 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259 {
260 int spbr;
261
262 /* Sets output mode, MOSI signal, and (optionally) loopback */
263 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264
265 /* Sets transfer bit rate */
266 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267 2 * rspi->max_speed_hz) - 1;
268 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
269
270 /* Disable dummy transmission, set 16-bit word access, 1 frame */
271 rspi_write8(rspi, 0, RSPI_SPDCR);
272 rspi->byte_access = 0;
273
274 /* Sets RSPCK, SSL, next-access delay value */
275 rspi_write8(rspi, 0x00, RSPI_SPCKD);
276 rspi_write8(rspi, 0x00, RSPI_SSLND);
277 rspi_write8(rspi, 0x00, RSPI_SPND);
278
279 /* Sets parity, interrupt mask */
280 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281
282 /* Resets sequencer */
283 rspi_write8(rspi, 0, RSPI_SPSCR);
284 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
285 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
286
287 /* Sets RSPI mode */
288 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
289
290 return 0;
291 }
292
293 /*
294 * functions for RSPI on RZ
295 */
296 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
297 {
298 int spbr;
299 int div = 0;
300 unsigned long clksrc;
301
302 /* Sets output mode, MOSI signal, and (optionally) loopback */
303 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
304
305 clksrc = clk_get_rate(rspi->clk);
306 while (div < 3) {
307 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
308 break;
309 div++;
310 clksrc /= 2;
311 }
312
313 /* Sets transfer bit rate */
314 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
315 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
316 rspi->spcmd |= div << 2;
317
318 /* Disable dummy transmission, set byte access */
319 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
320 rspi->byte_access = 1;
321
322 /* Sets RSPCK, SSL, next-access delay value */
323 rspi_write8(rspi, 0x00, RSPI_SPCKD);
324 rspi_write8(rspi, 0x00, RSPI_SSLND);
325 rspi_write8(rspi, 0x00, RSPI_SPND);
326
327 /* Resets sequencer */
328 rspi_write8(rspi, 0, RSPI_SPSCR);
329 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
330 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
331
332 /* Sets RSPI mode */
333 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
334
335 return 0;
336 }
337
338 /*
339 * functions for QSPI
340 */
341 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
342 {
343 int spbr;
344
345 /* Sets output mode, MOSI signal, and (optionally) loopback */
346 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
347
348 /* Sets transfer bit rate */
349 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
350 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
351
352 /* Disable dummy transmission, set byte access */
353 rspi_write8(rspi, 0, RSPI_SPDCR);
354 rspi->byte_access = 1;
355
356 /* Sets RSPCK, SSL, next-access delay value */
357 rspi_write8(rspi, 0x00, RSPI_SPCKD);
358 rspi_write8(rspi, 0x00, RSPI_SSLND);
359 rspi_write8(rspi, 0x00, RSPI_SPND);
360
361 /* Data Length Setting */
362 if (access_size == 8)
363 rspi->spcmd |= SPCMD_SPB_8BIT;
364 else if (access_size == 16)
365 rspi->spcmd |= SPCMD_SPB_16BIT;
366 else
367 rspi->spcmd |= SPCMD_SPB_32BIT;
368
369 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
370
371 /* Resets transfer data length */
372 rspi_write32(rspi, 0, QSPI_SPBMUL0);
373
374 /* Resets transmit and receive buffer */
375 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
376 /* Sets buffer to allow normal operation */
377 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
378
379 /* Resets sequencer */
380 rspi_write8(rspi, 0, RSPI_SPSCR);
381 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
382
383 /* Sets RSPI mode */
384 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
385
386 return 0;
387 }
388
389 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
390 {
391 u8 data;
392
393 data = rspi_read8(rspi, reg);
394 data &= ~mask;
395 data |= (val & mask);
396 rspi_write8(rspi, data, reg);
397 }
398
399 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
400 unsigned int len)
401 {
402 unsigned int n;
403
404 n = min(len, QSPI_BUFFER_SIZE);
405
406 if (len >= QSPI_BUFFER_SIZE) {
407 /* sets triggering number to 32 bytes */
408 qspi_update(rspi, SPBFCR_TXTRG_MASK,
409 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
410 } else {
411 /* sets triggering number to 1 byte */
412 qspi_update(rspi, SPBFCR_TXTRG_MASK,
413 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
414 }
415
416 return n;
417 }
418
419 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
420 {
421 unsigned int n;
422
423 n = min(len, QSPI_BUFFER_SIZE);
424
425 if (len >= QSPI_BUFFER_SIZE) {
426 /* sets triggering number to 32 bytes */
427 qspi_update(rspi, SPBFCR_RXTRG_MASK,
428 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
429 } else {
430 /* sets triggering number to 1 byte */
431 qspi_update(rspi, SPBFCR_RXTRG_MASK,
432 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
433 }
434 return n;
435 }
436
437 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
438
439 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
440 {
441 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
442 }
443
444 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
445 {
446 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
447 }
448
449 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
450 u8 enable_bit)
451 {
452 int ret;
453
454 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
455 if (rspi->spsr & wait_mask)
456 return 0;
457
458 rspi_enable_irq(rspi, enable_bit);
459 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
460 if (ret == 0 && !(rspi->spsr & wait_mask))
461 return -ETIMEDOUT;
462
463 return 0;
464 }
465
466 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
467 {
468 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
469 }
470
471 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
472 {
473 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
474 }
475
476 static int rspi_data_out(struct rspi_data *rspi, u8 data)
477 {
478 int error = rspi_wait_for_tx_empty(rspi);
479 if (error < 0) {
480 dev_err(&rspi->master->dev, "transmit timeout\n");
481 return error;
482 }
483 rspi_write_data(rspi, data);
484 return 0;
485 }
486
487 static int rspi_data_in(struct rspi_data *rspi)
488 {
489 int error;
490 u8 data;
491
492 error = rspi_wait_for_rx_full(rspi);
493 if (error < 0) {
494 dev_err(&rspi->master->dev, "receive timeout\n");
495 return error;
496 }
497 data = rspi_read_data(rspi);
498 return data;
499 }
500
501 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
502 unsigned int n)
503 {
504 while (n-- > 0) {
505 if (tx) {
506 int ret = rspi_data_out(rspi, *tx++);
507 if (ret < 0)
508 return ret;
509 }
510 if (rx) {
511 int ret = rspi_data_in(rspi);
512 if (ret < 0)
513 return ret;
514 *rx++ = ret;
515 }
516 }
517
518 return 0;
519 }
520
521 static void rspi_dma_complete(void *arg)
522 {
523 struct rspi_data *rspi = arg;
524
525 rspi->dma_callbacked = 1;
526 wake_up_interruptible(&rspi->wait);
527 }
528
529 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
530 struct sg_table *rx)
531 {
532 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
533 u8 irq_mask = 0;
534 unsigned int other_irq = 0;
535 dma_cookie_t cookie;
536 int ret;
537
538 /* First prepare and submit the DMA request(s), as this may fail */
539 if (rx) {
540 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
541 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
542 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
543 if (!desc_rx) {
544 ret = -EAGAIN;
545 goto no_dma_rx;
546 }
547
548 desc_rx->callback = rspi_dma_complete;
549 desc_rx->callback_param = rspi;
550 cookie = dmaengine_submit(desc_rx);
551 if (dma_submit_error(cookie)) {
552 ret = cookie;
553 goto no_dma_rx;
554 }
555
556 irq_mask |= SPCR_SPRIE;
557 }
558
559 if (tx) {
560 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
561 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
562 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
563 if (!desc_tx) {
564 ret = -EAGAIN;
565 goto no_dma_tx;
566 }
567
568 if (rx) {
569 /* No callback */
570 desc_tx->callback = NULL;
571 } else {
572 desc_tx->callback = rspi_dma_complete;
573 desc_tx->callback_param = rspi;
574 }
575 cookie = dmaengine_submit(desc_tx);
576 if (dma_submit_error(cookie)) {
577 ret = cookie;
578 goto no_dma_tx;
579 }
580
581 irq_mask |= SPCR_SPTIE;
582 }
583
584 /*
585 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
586 * called. So, this driver disables the IRQ while DMA transfer.
587 */
588 if (tx)
589 disable_irq(other_irq = rspi->tx_irq);
590 if (rx && rspi->rx_irq != other_irq)
591 disable_irq(rspi->rx_irq);
592
593 rspi_enable_irq(rspi, irq_mask);
594 rspi->dma_callbacked = 0;
595
596 /* Now start DMA */
597 if (rx)
598 dma_async_issue_pending(rspi->master->dma_rx);
599 if (tx)
600 dma_async_issue_pending(rspi->master->dma_tx);
601
602 ret = wait_event_interruptible_timeout(rspi->wait,
603 rspi->dma_callbacked, HZ);
604 if (ret > 0 && rspi->dma_callbacked) {
605 ret = 0;
606 } else {
607 if (!ret) {
608 dev_err(&rspi->master->dev, "DMA timeout\n");
609 ret = -ETIMEDOUT;
610 }
611 if (tx)
612 dmaengine_terminate_all(rspi->master->dma_tx);
613 if (rx)
614 dmaengine_terminate_all(rspi->master->dma_rx);
615 }
616
617 rspi_disable_irq(rspi, irq_mask);
618
619 if (tx)
620 enable_irq(rspi->tx_irq);
621 if (rx && rspi->rx_irq != other_irq)
622 enable_irq(rspi->rx_irq);
623
624 return ret;
625
626 no_dma_tx:
627 if (rx)
628 dmaengine_terminate_all(rspi->master->dma_rx);
629 no_dma_rx:
630 if (ret == -EAGAIN) {
631 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
632 dev_driver_string(&rspi->master->dev),
633 dev_name(&rspi->master->dev));
634 }
635 return ret;
636 }
637
638 static void rspi_receive_init(const struct rspi_data *rspi)
639 {
640 u8 spsr;
641
642 spsr = rspi_read8(rspi, RSPI_SPSR);
643 if (spsr & SPSR_SPRF)
644 rspi_read_data(rspi); /* dummy read */
645 if (spsr & SPSR_OVRF)
646 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
647 RSPI_SPSR);
648 }
649
650 static void rspi_rz_receive_init(const struct rspi_data *rspi)
651 {
652 rspi_receive_init(rspi);
653 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
654 rspi_write8(rspi, 0, RSPI_SPBFCR);
655 }
656
657 static void qspi_receive_init(const struct rspi_data *rspi)
658 {
659 u8 spsr;
660
661 spsr = rspi_read8(rspi, RSPI_SPSR);
662 if (spsr & SPSR_SPRF)
663 rspi_read_data(rspi); /* dummy read */
664 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
665 rspi_write8(rspi, 0, QSPI_SPBFCR);
666 }
667
668 static bool __rspi_can_dma(const struct rspi_data *rspi,
669 const struct spi_transfer *xfer)
670 {
671 return xfer->len > rspi->ops->fifo_size;
672 }
673
674 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
675 struct spi_transfer *xfer)
676 {
677 struct rspi_data *rspi = spi_master_get_devdata(master);
678
679 return __rspi_can_dma(rspi, xfer);
680 }
681
682 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
683 struct spi_transfer *xfer)
684 {
685 if (!rspi->master->can_dma || !__rspi_can_dma(rspi, xfer))
686 return -EAGAIN;
687
688 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
689 return rspi_dma_transfer(rspi, &xfer->tx_sg,
690 xfer->rx_buf ? &xfer->rx_sg : NULL);
691 }
692
693 static int rspi_common_transfer(struct rspi_data *rspi,
694 struct spi_transfer *xfer)
695 {
696 int ret;
697
698 ret = rspi_dma_check_then_transfer(rspi, xfer);
699 if (ret != -EAGAIN)
700 return ret;
701
702 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
703 if (ret < 0)
704 return ret;
705
706 /* Wait for the last transmission */
707 rspi_wait_for_tx_empty(rspi);
708
709 return 0;
710 }
711
712 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
713 struct spi_transfer *xfer)
714 {
715 struct rspi_data *rspi = spi_master_get_devdata(master);
716 u8 spcr;
717
718 spcr = rspi_read8(rspi, RSPI_SPCR);
719 if (xfer->rx_buf) {
720 rspi_receive_init(rspi);
721 spcr &= ~SPCR_TXMD;
722 } else {
723 spcr |= SPCR_TXMD;
724 }
725 rspi_write8(rspi, spcr, RSPI_SPCR);
726
727 return rspi_common_transfer(rspi, xfer);
728 }
729
730 static int rspi_rz_transfer_one(struct spi_master *master,
731 struct spi_device *spi,
732 struct spi_transfer *xfer)
733 {
734 struct rspi_data *rspi = spi_master_get_devdata(master);
735
736 rspi_rz_receive_init(rspi);
737
738 return rspi_common_transfer(rspi, xfer);
739 }
740
741 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
742 u8 *rx, unsigned int len)
743 {
744 unsigned int i, n;
745 int ret;
746
747 while (len > 0) {
748 n = qspi_set_send_trigger(rspi, len);
749 qspi_set_receive_trigger(rspi, len);
750 if (n == QSPI_BUFFER_SIZE) {
751 ret = rspi_wait_for_tx_empty(rspi);
752 if (ret < 0) {
753 dev_err(&rspi->master->dev, "transmit timeout\n");
754 return ret;
755 }
756 for (i = 0; i < n; i++)
757 rspi_write_data(rspi, *tx++);
758
759 ret = rspi_wait_for_rx_full(rspi);
760 if (ret < 0) {
761 dev_err(&rspi->master->dev, "receive timeout\n");
762 return ret;
763 }
764 for (i = 0; i < n; i++)
765 *rx++ = rspi_read_data(rspi);
766 } else {
767 ret = rspi_pio_transfer(rspi, tx, rx, n);
768 if (ret < 0)
769 return ret;
770 }
771 len -= n;
772 }
773
774 return 0;
775 }
776
777 static int qspi_transfer_out_in(struct rspi_data *rspi,
778 struct spi_transfer *xfer)
779 {
780 int ret;
781
782 qspi_receive_init(rspi);
783
784 ret = rspi_dma_check_then_transfer(rspi, xfer);
785 if (ret != -EAGAIN)
786 return ret;
787
788 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
789 xfer->rx_buf, xfer->len);
790 }
791
792 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
793 {
794 const u8 *tx = xfer->tx_buf;
795 unsigned int n = xfer->len;
796 unsigned int i, len;
797 int ret;
798
799 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
800 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
801 if (ret != -EAGAIN)
802 return ret;
803 }
804
805 while (n > 0) {
806 len = qspi_set_send_trigger(rspi, n);
807 if (len == QSPI_BUFFER_SIZE) {
808 ret = rspi_wait_for_tx_empty(rspi);
809 if (ret < 0) {
810 dev_err(&rspi->master->dev, "transmit timeout\n");
811 return ret;
812 }
813 for (i = 0; i < len; i++)
814 rspi_write_data(rspi, *tx++);
815 } else {
816 ret = rspi_pio_transfer(rspi, tx, NULL, len);
817 if (ret < 0)
818 return ret;
819 }
820 n -= len;
821 }
822
823 /* Wait for the last transmission */
824 rspi_wait_for_tx_empty(rspi);
825
826 return 0;
827 }
828
829 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
830 {
831 u8 *rx = xfer->rx_buf;
832 unsigned int n = xfer->len;
833 unsigned int i, len;
834 int ret;
835
836 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
837 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
838 if (ret != -EAGAIN)
839 return ret;
840 }
841
842 while (n > 0) {
843 len = qspi_set_receive_trigger(rspi, n);
844 if (len == QSPI_BUFFER_SIZE) {
845 ret = rspi_wait_for_rx_full(rspi);
846 if (ret < 0) {
847 dev_err(&rspi->master->dev, "receive timeout\n");
848 return ret;
849 }
850 for (i = 0; i < len; i++)
851 *rx++ = rspi_read_data(rspi);
852 } else {
853 ret = rspi_pio_transfer(rspi, NULL, rx, len);
854 if (ret < 0)
855 return ret;
856 }
857 n -= len;
858 }
859
860 return 0;
861 }
862
863 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
864 struct spi_transfer *xfer)
865 {
866 struct rspi_data *rspi = spi_master_get_devdata(master);
867
868 if (spi->mode & SPI_LOOP) {
869 return qspi_transfer_out_in(rspi, xfer);
870 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
871 /* Quad or Dual SPI Write */
872 return qspi_transfer_out(rspi, xfer);
873 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
874 /* Quad or Dual SPI Read */
875 return qspi_transfer_in(rspi, xfer);
876 } else {
877 /* Single SPI Transfer */
878 return qspi_transfer_out_in(rspi, xfer);
879 }
880 }
881
882 static int rspi_setup(struct spi_device *spi)
883 {
884 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
885
886 rspi->max_speed_hz = spi->max_speed_hz;
887
888 rspi->spcmd = SPCMD_SSLKP;
889 if (spi->mode & SPI_CPOL)
890 rspi->spcmd |= SPCMD_CPOL;
891 if (spi->mode & SPI_CPHA)
892 rspi->spcmd |= SPCMD_CPHA;
893
894 /* CMOS output mode and MOSI signal from previous transfer */
895 rspi->sppcr = 0;
896 if (spi->mode & SPI_LOOP)
897 rspi->sppcr |= SPPCR_SPLP;
898
899 set_config_register(rspi, 8);
900
901 return 0;
902 }
903
904 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
905 {
906 if (xfer->tx_buf)
907 switch (xfer->tx_nbits) {
908 case SPI_NBITS_QUAD:
909 return SPCMD_SPIMOD_QUAD;
910 case SPI_NBITS_DUAL:
911 return SPCMD_SPIMOD_DUAL;
912 default:
913 return 0;
914 }
915 if (xfer->rx_buf)
916 switch (xfer->rx_nbits) {
917 case SPI_NBITS_QUAD:
918 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
919 case SPI_NBITS_DUAL:
920 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
921 default:
922 return 0;
923 }
924
925 return 0;
926 }
927
928 static int qspi_setup_sequencer(struct rspi_data *rspi,
929 const struct spi_message *msg)
930 {
931 const struct spi_transfer *xfer;
932 unsigned int i = 0, len = 0;
933 u16 current_mode = 0xffff, mode;
934
935 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
936 mode = qspi_transfer_mode(xfer);
937 if (mode == current_mode) {
938 len += xfer->len;
939 continue;
940 }
941
942 /* Transfer mode change */
943 if (i) {
944 /* Set transfer data length of previous transfer */
945 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
946 }
947
948 if (i >= QSPI_NUM_SPCMD) {
949 dev_err(&msg->spi->dev,
950 "Too many different transfer modes");
951 return -EINVAL;
952 }
953
954 /* Program transfer mode for this transfer */
955 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
956 current_mode = mode;
957 len = xfer->len;
958 i++;
959 }
960 if (i) {
961 /* Set final transfer data length and sequence length */
962 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
963 rspi_write8(rspi, i - 1, RSPI_SPSCR);
964 }
965
966 return 0;
967 }
968
969 static int rspi_prepare_message(struct spi_master *master,
970 struct spi_message *msg)
971 {
972 struct rspi_data *rspi = spi_master_get_devdata(master);
973 int ret;
974
975 if (msg->spi->mode &
976 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
977 /* Setup sequencer for messages with multiple transfer modes */
978 ret = qspi_setup_sequencer(rspi, msg);
979 if (ret < 0)
980 return ret;
981 }
982
983 /* Enable SPI function in master mode */
984 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
985 return 0;
986 }
987
988 static int rspi_unprepare_message(struct spi_master *master,
989 struct spi_message *msg)
990 {
991 struct rspi_data *rspi = spi_master_get_devdata(master);
992
993 /* Disable SPI function */
994 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
995
996 /* Reset sequencer for Single SPI Transfers */
997 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
998 rspi_write8(rspi, 0, RSPI_SPSCR);
999 return 0;
1000 }
1001
1002 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1003 {
1004 struct rspi_data *rspi = _sr;
1005 u8 spsr;
1006 irqreturn_t ret = IRQ_NONE;
1007 u8 disable_irq = 0;
1008
1009 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1010 if (spsr & SPSR_SPRF)
1011 disable_irq |= SPCR_SPRIE;
1012 if (spsr & SPSR_SPTEF)
1013 disable_irq |= SPCR_SPTIE;
1014
1015 if (disable_irq) {
1016 ret = IRQ_HANDLED;
1017 rspi_disable_irq(rspi, disable_irq);
1018 wake_up(&rspi->wait);
1019 }
1020
1021 return ret;
1022 }
1023
1024 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1025 {
1026 struct rspi_data *rspi = _sr;
1027 u8 spsr;
1028
1029 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1030 if (spsr & SPSR_SPRF) {
1031 rspi_disable_irq(rspi, SPCR_SPRIE);
1032 wake_up(&rspi->wait);
1033 return IRQ_HANDLED;
1034 }
1035
1036 return 0;
1037 }
1038
1039 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1040 {
1041 struct rspi_data *rspi = _sr;
1042 u8 spsr;
1043
1044 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1045 if (spsr & SPSR_SPTEF) {
1046 rspi_disable_irq(rspi, SPCR_SPTIE);
1047 wake_up(&rspi->wait);
1048 return IRQ_HANDLED;
1049 }
1050
1051 return 0;
1052 }
1053
1054 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1055 enum dma_transfer_direction dir,
1056 unsigned int id,
1057 dma_addr_t port_addr)
1058 {
1059 dma_cap_mask_t mask;
1060 struct dma_chan *chan;
1061 struct dma_slave_config cfg;
1062 int ret;
1063
1064 dma_cap_zero(mask);
1065 dma_cap_set(DMA_SLAVE, mask);
1066
1067 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1068 (void *)(unsigned long)id, dev,
1069 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1070 if (!chan) {
1071 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1072 return NULL;
1073 }
1074
1075 memset(&cfg, 0, sizeof(cfg));
1076 cfg.direction = dir;
1077 if (dir == DMA_MEM_TO_DEV) {
1078 cfg.dst_addr = port_addr;
1079 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1080 } else {
1081 cfg.src_addr = port_addr;
1082 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1083 }
1084
1085 ret = dmaengine_slave_config(chan, &cfg);
1086 if (ret) {
1087 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1088 dma_release_channel(chan);
1089 return NULL;
1090 }
1091
1092 return chan;
1093 }
1094
1095 static int rspi_request_dma(struct device *dev, struct spi_master *master,
1096 const struct resource *res)
1097 {
1098 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1099 unsigned int dma_tx_id, dma_rx_id;
1100
1101 if (dev->of_node) {
1102 /* In the OF case we will get the slave IDs from the DT */
1103 dma_tx_id = 0;
1104 dma_rx_id = 0;
1105 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1106 dma_tx_id = rspi_pd->dma_tx_id;
1107 dma_rx_id = rspi_pd->dma_rx_id;
1108 } else {
1109 /* The driver assumes no error. */
1110 return 0;
1111 }
1112
1113 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1114 res->start + RSPI_SPDR);
1115 if (!master->dma_tx)
1116 return -ENODEV;
1117
1118 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1119 res->start + RSPI_SPDR);
1120 if (!master->dma_rx) {
1121 dma_release_channel(master->dma_tx);
1122 master->dma_tx = NULL;
1123 return -ENODEV;
1124 }
1125
1126 master->can_dma = rspi_can_dma;
1127 dev_info(dev, "DMA available");
1128 return 0;
1129 }
1130
1131 static void rspi_release_dma(struct spi_master *master)
1132 {
1133 if (master->dma_tx)
1134 dma_release_channel(master->dma_tx);
1135 if (master->dma_rx)
1136 dma_release_channel(master->dma_rx);
1137 }
1138
1139 static int rspi_remove(struct platform_device *pdev)
1140 {
1141 struct rspi_data *rspi = platform_get_drvdata(pdev);
1142
1143 rspi_release_dma(rspi->master);
1144 pm_runtime_disable(&pdev->dev);
1145
1146 return 0;
1147 }
1148
1149 static const struct spi_ops rspi_ops = {
1150 .set_config_register = rspi_set_config_register,
1151 .transfer_one = rspi_transfer_one,
1152 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1153 .flags = SPI_MASTER_MUST_TX,
1154 .fifo_size = 8,
1155 };
1156
1157 static const struct spi_ops rspi_rz_ops = {
1158 .set_config_register = rspi_rz_set_config_register,
1159 .transfer_one = rspi_rz_transfer_one,
1160 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1161 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1162 .fifo_size = 8, /* 8 for TX, 32 for RX */
1163 };
1164
1165 static const struct spi_ops qspi_ops = {
1166 .set_config_register = qspi_set_config_register,
1167 .transfer_one = qspi_transfer_one,
1168 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1169 SPI_TX_DUAL | SPI_TX_QUAD |
1170 SPI_RX_DUAL | SPI_RX_QUAD,
1171 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1172 .fifo_size = 32,
1173 };
1174
1175 #ifdef CONFIG_OF
1176 static const struct of_device_id rspi_of_match[] = {
1177 /* RSPI on legacy SH */
1178 { .compatible = "renesas,rspi", .data = &rspi_ops },
1179 /* RSPI on RZ/A1H */
1180 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1181 /* QSPI on R-Car Gen2 */
1182 { .compatible = "renesas,qspi", .data = &qspi_ops },
1183 { /* sentinel */ }
1184 };
1185
1186 MODULE_DEVICE_TABLE(of, rspi_of_match);
1187
1188 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1189 {
1190 u32 num_cs;
1191 int error;
1192
1193 /* Parse DT properties */
1194 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1195 if (error) {
1196 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1197 return error;
1198 }
1199
1200 master->num_chipselect = num_cs;
1201 return 0;
1202 }
1203 #else
1204 #define rspi_of_match NULL
1205 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1206 {
1207 return -EINVAL;
1208 }
1209 #endif /* CONFIG_OF */
1210
1211 static int rspi_request_irq(struct device *dev, unsigned int irq,
1212 irq_handler_t handler, const char *suffix,
1213 void *dev_id)
1214 {
1215 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1216 dev_name(dev), suffix);
1217 if (!name)
1218 return -ENOMEM;
1219
1220 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1221 }
1222
1223 static int rspi_probe(struct platform_device *pdev)
1224 {
1225 struct resource *res;
1226 struct spi_master *master;
1227 struct rspi_data *rspi;
1228 int ret;
1229 const struct rspi_plat_data *rspi_pd;
1230 const struct spi_ops *ops;
1231
1232 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1233 if (master == NULL)
1234 return -ENOMEM;
1235
1236 ops = of_device_get_match_data(&pdev->dev);
1237 if (ops) {
1238 ret = rspi_parse_dt(&pdev->dev, master);
1239 if (ret)
1240 goto error1;
1241 } else {
1242 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1243 rspi_pd = dev_get_platdata(&pdev->dev);
1244 if (rspi_pd && rspi_pd->num_chipselect)
1245 master->num_chipselect = rspi_pd->num_chipselect;
1246 else
1247 master->num_chipselect = 2; /* default */
1248 }
1249
1250 /* ops parameter check */
1251 if (!ops->set_config_register) {
1252 dev_err(&pdev->dev, "there is no set_config_register\n");
1253 ret = -ENODEV;
1254 goto error1;
1255 }
1256
1257 rspi = spi_master_get_devdata(master);
1258 platform_set_drvdata(pdev, rspi);
1259 rspi->ops = ops;
1260 rspi->master = master;
1261
1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1264 if (IS_ERR(rspi->addr)) {
1265 ret = PTR_ERR(rspi->addr);
1266 goto error1;
1267 }
1268
1269 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1270 if (IS_ERR(rspi->clk)) {
1271 dev_err(&pdev->dev, "cannot get clock\n");
1272 ret = PTR_ERR(rspi->clk);
1273 goto error1;
1274 }
1275
1276 pm_runtime_enable(&pdev->dev);
1277
1278 init_waitqueue_head(&rspi->wait);
1279
1280 master->bus_num = pdev->id;
1281 master->setup = rspi_setup;
1282 master->auto_runtime_pm = true;
1283 master->transfer_one = ops->transfer_one;
1284 master->prepare_message = rspi_prepare_message;
1285 master->unprepare_message = rspi_unprepare_message;
1286 master->mode_bits = ops->mode_bits;
1287 master->flags = ops->flags;
1288 master->dev.of_node = pdev->dev.of_node;
1289
1290 ret = platform_get_irq_byname(pdev, "rx");
1291 if (ret < 0) {
1292 ret = platform_get_irq_byname(pdev, "mux");
1293 if (ret < 0)
1294 ret = platform_get_irq(pdev, 0);
1295 if (ret >= 0)
1296 rspi->rx_irq = rspi->tx_irq = ret;
1297 } else {
1298 rspi->rx_irq = ret;
1299 ret = platform_get_irq_byname(pdev, "tx");
1300 if (ret >= 0)
1301 rspi->tx_irq = ret;
1302 }
1303 if (ret < 0) {
1304 dev_err(&pdev->dev, "platform_get_irq error\n");
1305 goto error2;
1306 }
1307
1308 if (rspi->rx_irq == rspi->tx_irq) {
1309 /* Single multiplexed interrupt */
1310 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1311 "mux", rspi);
1312 } else {
1313 /* Multi-interrupt mode, only SPRI and SPTI are used */
1314 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1315 "rx", rspi);
1316 if (!ret)
1317 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1318 rspi_irq_tx, "tx", rspi);
1319 }
1320 if (ret < 0) {
1321 dev_err(&pdev->dev, "request_irq error\n");
1322 goto error2;
1323 }
1324
1325 ret = rspi_request_dma(&pdev->dev, master, res);
1326 if (ret < 0)
1327 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1328
1329 ret = devm_spi_register_master(&pdev->dev, master);
1330 if (ret < 0) {
1331 dev_err(&pdev->dev, "spi_register_master error.\n");
1332 goto error3;
1333 }
1334
1335 dev_info(&pdev->dev, "probed\n");
1336
1337 return 0;
1338
1339 error3:
1340 rspi_release_dma(master);
1341 error2:
1342 pm_runtime_disable(&pdev->dev);
1343 error1:
1344 spi_master_put(master);
1345
1346 return ret;
1347 }
1348
1349 static const struct platform_device_id spi_driver_ids[] = {
1350 { "rspi", (kernel_ulong_t)&rspi_ops },
1351 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1352 { "qspi", (kernel_ulong_t)&qspi_ops },
1353 {},
1354 };
1355
1356 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1357
1358 #ifdef CONFIG_PM_SLEEP
1359 static int rspi_suspend(struct device *dev)
1360 {
1361 struct platform_device *pdev = to_platform_device(dev);
1362 struct rspi_data *rspi = platform_get_drvdata(pdev);
1363
1364 return spi_master_suspend(rspi->master);
1365 }
1366
1367 static int rspi_resume(struct device *dev)
1368 {
1369 struct platform_device *pdev = to_platform_device(dev);
1370 struct rspi_data *rspi = platform_get_drvdata(pdev);
1371
1372 return spi_master_resume(rspi->master);
1373 }
1374
1375 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1376 #define DEV_PM_OPS &rspi_pm_ops
1377 #else
1378 #define DEV_PM_OPS NULL
1379 #endif /* CONFIG_PM_SLEEP */
1380
1381 static struct platform_driver rspi_driver = {
1382 .probe = rspi_probe,
1383 .remove = rspi_remove,
1384 .id_table = spi_driver_ids,
1385 .driver = {
1386 .name = "renesas_spi",
1387 .pm = DEV_PM_OPS,
1388 .of_match_table = of_match_ptr(rspi_of_match),
1389 },
1390 };
1391 module_platform_driver(rspi_driver);
1392
1393 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1394 MODULE_LICENSE("GPL v2");
1395 MODULE_AUTHOR("Yoshihiro Shimoda");
1396 MODULE_ALIAS("platform:rspi");
Linux with added FPC-III support