drivers/staging/rtlwifi/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2009-2012  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 #ifndef __RTL_PCI_H__
  16 #define __RTL_PCI_H__
  17
  18 #include <linux/pci.h>
  19 /* 1: MSDU packet queue,
  20  * 2: Rx Command Queue
  21  */
  22 #define RTL_PCI_RX_MPDU_QUEUE                   0
  23 #define RTL_PCI_RX_CMD_QUEUE                    1
  24 #define RTL_PCI_MAX_RX_QUEUE                    2
  25
  26 #define RTL_PCI_MAX_RX_COUNT                    512/*64*/
  27 #define RTL_PCI_MAX_TX_QUEUE_COUNT              9
  28
  29 #define RT_TXDESC_NUM                           128
  30 #define TX_DESC_NUM_92E                         512
  31 #define TX_DESC_NUM_8822B                       512
  32 #define RT_TXDESC_NUM_BE_QUEUE                  256
  33
  34 #define BK_QUEUE                                0
  35 #define BE_QUEUE                                1
  36 #define VI_QUEUE                                2
  37 #define VO_QUEUE                                3
  38 #define BEACON_QUEUE                            4
  39 #define TXCMD_QUEUE                             5
  40 #define MGNT_QUEUE                              6
  41 #define HIGH_QUEUE                              7
  42 #define HCCA_QUEUE                              8
  43 #define H2C_QUEUE                               TXCMD_QUEUE     /* In 8822B */
  44
  45 #define RTL_PCI_DEVICE(vend, dev, cfg)  \
  46         .vendor = (vend), \
  47         .device = (dev), \
  48         .subvendor = PCI_ANY_ID, \
  49         .subdevice = PCI_ANY_ID,\
  50         .driver_data = (kernel_ulong_t)&(cfg)
  51
  52 #define INTEL_VENDOR_ID                         0x8086
  53 #define SIS_VENDOR_ID                           0x1039
  54 #define ATI_VENDOR_ID                           0x1002
  55 #define ATI_DEVICE_ID                           0x7914
  56 #define AMD_VENDOR_ID                           0x1022
  57
  58 #define PCI_MAX_BRIDGE_NUMBER                   255
  59 #define PCI_MAX_DEVICES                         32
  60 #define PCI_MAX_FUNCTION                        8
  61
  62 #define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
  63 #define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
  64
  65 #define PCI_CLASS_BRIDGE_DEV            0x06
  66 #define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  67 #define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  68 #define PCI_CAP_ID_EXP                  0x10
  69
  70 #define U1DONTCARE                      0xFF
  71 #define U2DONTCARE                      0xFFFF
  72 #define U4DONTCARE                      0xFFFFFFFF
  73
  74 #define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
  75 #define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
  76 #define RTL_PCI_8174_DID        0x8174  /*8192 SE */
  77 #define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
  78 #define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
  79 #define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
  80 #define RTL_PCI_8723AE_DID      0x8723  /*8723AE */
  81 #define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
  82 #define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
  83 #define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
  84 #define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
  85 #define RTL_PCI_700F_DID        0x700F
  86 #define RTL_PCI_701F_DID        0x701F
  87 #define RTL_PCI_DLINK_DID       0x3304
  88 #define RTL_PCI_8723AE_DID      0x8723  /*8723e */
  89 #define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
  90 #define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
  91 #define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
  92 #define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
  93 #define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
  94 #define RTL_PCI_8192DE_DID      0x8193  /*8192de */
  95 #define RTL_PCI_8192DE_DID2     0x002B  /*92DE*/
  96 #define RTL_PCI_8188EE_DID      0x8179  /*8188ee*/
  97 #define RTL_PCI_8723BE_DID      0xB723  /*8723be*/
  98 #define RTL_PCI_8192EE_DID      0x818B  /*8192ee*/
  99 #define RTL_PCI_8821AE_DID      0x8821  /*8821ae*/
 100 #define RTL_PCI_8812AE_DID      0x8812  /*8812ae*/
 101 #define RTL_PCI_8822BE_DID      0xB822  /*8822be*/
 102
 103 /*8192 support 16 pages of IO registers*/
 104 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
 105 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
 106 #define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
 107 #define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
 108 #define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
 109
 110 #define RTL_PCI_REVISION_ID_8190PCI             0x00
 111 #define RTL_PCI_REVISION_ID_8192PCIE            0x01
 112 #define RTL_PCI_REVISION_ID_8192SE              0x10
 113 #define RTL_PCI_REVISION_ID_8192CE              0x1
 114 #define RTL_PCI_REVISION_ID_8192DE              0x0
 115
 116 #define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
 117
 118 enum pci_bridge_vendor {
 119         PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
 120         PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
 121         PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
 122         PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
 123         PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
 124         PCI_BRIDGE_VENDOR_MAX,
 125 };
 126
 127 struct rtl_pci_capabilities_header {
 128         u8 capability_id;
 129         u8 next;
 130 };
 131
 132 /* In new TRX flow, Buffer_desc is new concept
 133  * But TX wifi info == TX descriptor in old flow
 134  * RX wifi info == RX descriptor in old flow
 135  */
 136 struct rtl_tx_buffer_desc {
 137         u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
 138 } __packed;
 139
 140 struct rtl_tx_desc {
 141         u32 dword[16];
 142 } __packed;
 143
 144 struct rtl_rx_buffer_desc { /*rx buffer desc*/
 145         u32 dword[4];
 146 } __packed;
 147
 148 struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
 149         u32 dword[8];
 150 } __packed;
 151
 152 struct rtl_tx_cmd_desc {
 153         u32 dword[16];
 154 } __packed;
 155
 156 struct rtl8192_tx_ring {
 157         struct rtl_tx_desc *desc;
 158         dma_addr_t dma;
 159         unsigned int idx;
 160         unsigned int entries;
 161         struct sk_buff_head queue;
 162         /*add for new trx flow*/
 163         struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
 164         dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
 165         u16 cur_tx_wp; /* current_tx_write_point */
 166         u16 cur_tx_rp; /* current_tx_read_point */
 167 };
 168
 169 struct rtl8192_rx_ring {
 170         struct rtl_rx_desc *desc;
 171         dma_addr_t dma;
 172         unsigned int idx;
 173         struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
 174         /*add for new trx flow*/
 175         struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
 176         u16 next_rx_rp; /* next_rx_read_point */
 177 };
 178
 179 struct rtl_pci {
 180         struct pci_dev *pdev;
 181         bool irq_enabled;
 182
 183         bool driver_is_goingto_unload;
 184         bool up_first_time;
 185         bool first_init;
 186         bool being_init_adapter;
 187         bool init_ready;
 188
 189         /*Tx */
 190         struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
 191         int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
 192         u32 transmit_config;
 193
 194         /*Rx */
 195         struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
 196         int rxringcount;
 197         u16 rxbuffersize;
 198         u32 receive_config;
 199
 200         /*irq */
 201         u8 irq_alloc;
 202         u32 irq_mask[4];        /* 0-1: normal, 2: unused, 3: h2c */
 203         u32 sys_irq_mask;
 204
 205         /*Bcn control register setting */
 206         u32 reg_bcn_ctrl_val;
 207
 208          /*ASPM*/ u8 const_pci_aspm;
 209         u8 const_amdpci_aspm;
 210         u8 const_hwsw_rfoff_d3;
 211         u8 const_support_pciaspm;
 212         /*pci-e bridge */
 213         u8 const_hostpci_aspm_setting;
 214         /*pci-e device */
 215         u8 const_devicepci_aspm_setting;
 216         /* If it supports ASPM, Offset[560h] = 0x40,
 217          * otherwise Offset[560h] = 0x00.
 218          */
 219         bool support_aspm;
 220         bool support_backdoor;
 221
 222         /*QOS & EDCA */
 223         enum acm_method acm_method;
 224
 225         u16 shortretry_limit;
 226         u16 longretry_limit;
 227
 228         /* MSI support */
 229         bool msi_support;
 230         bool using_msi;
 231         /* interrupt clear before set */
 232         bool int_clear;
 233 };
 234
 235 struct mp_adapter {
 236         u8 linkctrl_reg;
 237
 238         u8 busnumber;
 239         u8 devnumber;
 240         u8 funcnumber;
 241
 242         u8 pcibridge_busnum;
 243         u8 pcibridge_devnum;
 244         u8 pcibridge_funcnum;
 245
 246         u8 pcibridge_vendor;
 247         u16 pcibridge_vendorid;
 248         u16 pcibridge_deviceid;
 249
 250         u8 num4bytes;
 251
 252         u8 pcibridge_pciehdr_offset;
 253         u8 pcibridge_linkctrlreg;
 254
 255         bool amd_l1_patch;
 256 };
 257
 258 struct rtl_pci_priv {
 259         struct bt_coexist_info bt_coexist;
 260         struct rtl_led_ctl ledctl;
 261         struct rtl_pci dev;
 262         struct mp_adapter ndis_adapter;
 263 };
 264
 265 #define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
 266 #define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
 267
 268 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
 269
 270 extern const struct rtl_intf_ops rtl_pci_ops;
 271
 272 int rtl_pci_probe(struct pci_dev *pdev,
 273                   const struct pci_device_id *id);
 274 void rtl_pci_disconnect(struct pci_dev *pdev);
 275 #ifdef CONFIG_PM_SLEEP
 276 int rtl_pci_suspend(struct device *dev);
 277 int rtl_pci_resume(struct device *dev);
 278 #endif /* CONFIG_PM_SLEEP */
 279 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
 280 {
 281         return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 282 }
 283
 284 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
 285 {
 286         return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 287 }
 288
 289 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
 290 {
 291         return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 292 }
 293
 294 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
 295 {
 296         writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 297 }
 298
 299 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
 300                                      u32 addr, u16 val)
 301 {
 302         writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 303 }
 304
 305 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
 306                                      u32 addr, u32 val)
 307 {
 308         writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
 309 }
 310
 311 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
 312 {
 313         if (rp <= wp)
 314                 return size - 1 + rp - wp;
 315         return rp - wp - 1;
 316 }
 317
 318 #endif