?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / staging / rts5208 / ms.c
blob3a71dbb6d24a8d1133d0f2cdcd0f418ad7f59ccc
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27
28 #include "rtsx.h"
29 #include "ms.h"
30
31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
32 {
33 struct ms_info *ms_card = &chip->ms_card;
34
35 ms_card->err_code = err_code;
36 }
37
38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
39 {
40 struct ms_info *ms_card = &chip->ms_card;
41
42 return (ms_card->err_code == err_code);
43 }
44
45 static int ms_parse_err_code(struct rtsx_chip *chip)
46 {
47 return STATUS_FAIL;
48 }
49
50 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
51 u8 tpc, u8 cnt, u8 cfg)
52 {
53 struct ms_info *ms_card = &chip->ms_card;
54 int retval;
55 u8 *ptr;
56
57 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc);
58
59 rtsx_init_cmd(chip);
60
61 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
64 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
65 0x01, PINGPONG_BUFFER);
66
67 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
68 0xFF, MS_TRANSFER_START | trans_mode);
69 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
70 MS_TRANSFER_END, MS_TRANSFER_END);
71
72 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
73
74 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
75 if (retval < 0) {
76 rtsx_clear_ms_error(chip);
77 ms_set_err_code(chip, MS_TO_ERROR);
78 return ms_parse_err_code(chip);
79 }
80
81 ptr = rtsx_get_cmd_data(chip) + 1;
82
83 if (!(tpc & 0x08)) { /* Read Packet */
84 if (*ptr & MS_CRC16_ERR) {
85 ms_set_err_code(chip, MS_CRC16_ERROR);
86 return ms_parse_err_code(chip);
87 }
88 } else { /* Write Packet */
89 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
90 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
91 ms_set_err_code(chip, MS_CMD_NK);
92 return ms_parse_err_code(chip);
93 }
94 }
95 }
96
97 if (*ptr & MS_RDY_TIMEOUT) {
98 rtsx_clear_ms_error(chip);
99 ms_set_err_code(chip, MS_TO_ERROR);
100 return ms_parse_err_code(chip);
101 }
102
103 return STATUS_SUCCESS;
104 }
105
106 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
107 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k,
108 int use_sg, void *buf, int buf_len)
109 {
110 int retval;
111 u8 val, err_code = 0;
112 enum dma_data_direction dir;
113
114 if (!buf || !buf_len) {
115 return STATUS_FAIL;
116 }
117
118 if (trans_mode == MS_TM_AUTO_READ) {
119 dir = DMA_FROM_DEVICE;
120 err_code = MS_FLASH_READ_ERROR;
121 } else if (trans_mode == MS_TM_AUTO_WRITE) {
122 dir = DMA_TO_DEVICE;
123 err_code = MS_FLASH_WRITE_ERROR;
124 } else {
125 return STATUS_FAIL;
126 }
127
128 rtsx_init_cmd(chip);
129
130 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
131 rtsx_add_cmd(chip, WRITE_REG_CMD,
132 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
133 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
134 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
135
136 if (mode_2k) {
137 rtsx_add_cmd(chip, WRITE_REG_CMD,
138 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
139 } else {
140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
141 }
142
143 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
144
145 rtsx_add_cmd(chip, WRITE_REG_CMD,
146 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
147 rtsx_add_cmd(chip, CHECK_REG_CMD,
148 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
149
150 rtsx_send_cmd_no_wait(chip);
151
152 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
153 use_sg, dir, chip->mspro_timeout);
154 if (retval < 0) {
155 ms_set_err_code(chip, err_code);
156 if (retval == -ETIMEDOUT)
157 retval = STATUS_TIMEDOUT;
158 else
159 retval = STATUS_FAIL;
160
161 return retval;
162 }
163
164 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
165 if (retval) {
166 return retval;
167 }
168 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
169 return STATUS_FAIL;
170 }
171
172 return STATUS_SUCCESS;
173 }
174
175 static int ms_write_bytes(struct rtsx_chip *chip,
176 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
177 {
178 struct ms_info *ms_card = &chip->ms_card;
179 int retval, i;
180
181 if (!data || (data_len < cnt)) {
182 return STATUS_ERROR;
183 }
184
185 rtsx_init_cmd(chip);
186
187 for (i = 0; i < cnt; i++) {
188 rtsx_add_cmd(chip, WRITE_REG_CMD,
189 PPBUF_BASE2 + i, 0xFF, data[i]);
190 }
191 if (cnt % 2)
192 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
193
194 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
195 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
196 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
197 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
198 0x01, PINGPONG_BUFFER);
199
200 rtsx_add_cmd(chip, WRITE_REG_CMD,
201 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
202 rtsx_add_cmd(chip, CHECK_REG_CMD,
203 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
204
205 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
206 if (retval < 0) {
207 u8 val = 0;
208
209 rtsx_read_register(chip, MS_TRANS_CFG, &val);
210 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val);
211
212 rtsx_clear_ms_error(chip);
213
214 if (!(tpc & 0x08)) {
215 if (val & MS_CRC16_ERR) {
216 ms_set_err_code(chip, MS_CRC16_ERROR);
217 return ms_parse_err_code(chip);
218 }
219 } else {
220 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
221 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
222 ms_set_err_code(chip, MS_CMD_NK);
223 return ms_parse_err_code(chip);
224 }
225 }
226 }
227
228 if (val & MS_RDY_TIMEOUT) {
229 ms_set_err_code(chip, MS_TO_ERROR);
230 return ms_parse_err_code(chip);
231 }
232
233 ms_set_err_code(chip, MS_TO_ERROR);
234 return ms_parse_err_code(chip);
235 }
236
237 return STATUS_SUCCESS;
238 }
239
240 static int ms_read_bytes(struct rtsx_chip *chip,
241 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
242 {
243 struct ms_info *ms_card = &chip->ms_card;
244 int retval, i;
245 u8 *ptr;
246
247 if (!data) {
248 return STATUS_ERROR;
249 }
250
251 rtsx_init_cmd(chip);
252
253 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
254 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
255 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
256 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
257 0x01, PINGPONG_BUFFER);
258
259 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
260 MS_TRANSFER_START | MS_TM_READ_BYTES);
261 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
262 MS_TRANSFER_END, MS_TRANSFER_END);
263
264 for (i = 0; i < data_len - 1; i++)
265 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
266
267 if (data_len % 2)
268 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
269 else
270 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
271 0, 0);
272
273 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
274 if (retval < 0) {
275 u8 val = 0;
276
277 rtsx_read_register(chip, MS_TRANS_CFG, &val);
278 rtsx_clear_ms_error(chip);
279
280 if (!(tpc & 0x08)) {
281 if (val & MS_CRC16_ERR) {
282 ms_set_err_code(chip, MS_CRC16_ERROR);
283 return ms_parse_err_code(chip);
284 }
285 } else {
286 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
287 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
288 ms_set_err_code(chip, MS_CMD_NK);
289 return ms_parse_err_code(chip);
290 }
291 }
292 }
293
294 if (val & MS_RDY_TIMEOUT) {
295 ms_set_err_code(chip, MS_TO_ERROR);
296 return ms_parse_err_code(chip);
297 }
298
299 ms_set_err_code(chip, MS_TO_ERROR);
300 return ms_parse_err_code(chip);
301 }
302
303 ptr = rtsx_get_cmd_data(chip) + 1;
304
305 for (i = 0; i < data_len; i++)
306 data[i] = ptr[i];
307
308 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
309 dev_dbg(rtsx_dev(chip), "Read format progress:\n");
310 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr,
311 cnt);
312 }
313
314 return STATUS_SUCCESS;
315 }
316
317 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start,
318 u8 read_cnt, u8 write_start, u8 write_cnt)
319 {
320 int retval, i;
321 u8 data[4];
322
323 data[0] = read_start;
324 data[1] = read_cnt;
325 data[2] = write_start;
326 data[3] = write_cnt;
327
328 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
329 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
330 NO_WAIT_INT, data, 4);
331 if (retval == STATUS_SUCCESS)
332 return STATUS_SUCCESS;
333 rtsx_clear_ms_error(chip);
334 }
335
336 return STATUS_FAIL;
337 }
338
339 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
340 {
341 u8 data[2];
342
343 data[0] = cmd;
344 data[1] = 0;
345
346 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
347 }
348
349 static int ms_set_init_para(struct rtsx_chip *chip)
350 {
351 struct ms_info *ms_card = &chip->ms_card;
352 int retval;
353
354 if (CHK_HG8BIT(ms_card)) {
355 if (chip->asic_code)
356 ms_card->ms_clock = chip->asic_ms_hg_clk;
357 else
358 ms_card->ms_clock = chip->fpga_ms_hg_clk;
359
360 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
361 if (chip->asic_code)
362 ms_card->ms_clock = chip->asic_ms_4bit_clk;
363 else
364 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
365
366 } else {
367 if (chip->asic_code)
368 ms_card->ms_clock = chip->asic_ms_1bit_clk;
369 else
370 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
371 }
372
373 retval = switch_clock(chip, ms_card->ms_clock);
374 if (retval != STATUS_SUCCESS) {
375 return STATUS_FAIL;
376 }
377
378 retval = select_card(chip, MS_CARD);
379 if (retval != STATUS_SUCCESS) {
380 return STATUS_FAIL;
381 }
382
383 return STATUS_SUCCESS;
384 }
385
386 static int ms_switch_clock(struct rtsx_chip *chip)
387 {
388 struct ms_info *ms_card = &chip->ms_card;
389 int retval;
390
391 retval = select_card(chip, MS_CARD);
392 if (retval != STATUS_SUCCESS) {
393 return STATUS_FAIL;
394 }
395
396 retval = switch_clock(chip, ms_card->ms_clock);
397 if (retval != STATUS_SUCCESS) {
398 return STATUS_FAIL;
399 }
400
401 return STATUS_SUCCESS;
402 }
403
404 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
405 {
406 int retval;
407
408 if (CHECK_PID(chip, 0x5208)) {
409 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
410 MS_D1_PD | MS_D2_PD | MS_CLK_PD |
411 MS_D6_PD);
412 if (retval) {
413 return retval;
414 }
415 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
416 MS_D3_PD | MS_D0_PD | MS_BS_PD |
417 XD_D4_PD);
418 if (retval) {
419 return retval;
420 }
421 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
422 MS_D7_PD | XD_CE_PD | XD_CLE_PD |
423 XD_CD_PU);
424 if (retval) {
425 return retval;
426 }
427 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
428 XD_RDY_PD | SD_D3_PD | SD_D2_PD |
429 XD_ALE_PD);
430 if (retval) {
431 return retval;
432 }
433 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
434 MS_INS_PU | SD_WP_PD | SD_CD_PU |
435 SD_CMD_PD);
436 if (retval) {
437 return retval;
438 }
439 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
440 MS_D5_PD | MS_D4_PD);
441 if (retval) {
442 return retval;
443 }
444 } else if (CHECK_PID(chip, 0x5288)) {
445 if (CHECK_BARO_PKG(chip, QFN)) {
446 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
447 0xFF, 0x55);
448 if (retval) {
449 return retval;
450 }
451 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
452 0xFF, 0x55);
453 if (retval) {
454 return retval;
455 }
456 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
457 0xFF, 0x4B);
458 if (retval) {
459 return retval;
460 }
461 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
462 0xFF, 0x69);
463 if (retval) {
464 return retval;
465 }
466 }
467 }
468
469 return STATUS_SUCCESS;
470 }
471
472 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
473 {
474 int retval;
475
476 rtsx_init_cmd(chip);
477
478 if (CHECK_PID(chip, 0x5208)) {
479 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
480 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
481 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
482 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
483 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
484 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
485 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
486 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
487 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
488 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
489 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
490 MS_D5_PD | MS_D4_PD);
491 } else if (CHECK_PID(chip, 0x5288)) {
492 if (CHECK_BARO_PKG(chip, QFN)) {
493 rtsx_add_cmd(chip, WRITE_REG_CMD,
494 CARD_PULL_CTL1, 0xFF, 0x55);
495 rtsx_add_cmd(chip, WRITE_REG_CMD,
496 CARD_PULL_CTL2, 0xFF, 0x45);
497 rtsx_add_cmd(chip, WRITE_REG_CMD,
498 CARD_PULL_CTL3, 0xFF, 0x4B);
499 rtsx_add_cmd(chip, WRITE_REG_CMD,
500 CARD_PULL_CTL4, 0xFF, 0x29);
501 }
502 }
503
504 retval = rtsx_send_cmd(chip, MS_CARD, 100);
505 if (retval < 0) {
506 return STATUS_FAIL;
507 }
508
509 return STATUS_SUCCESS;
510 }
511
512 static int ms_prepare_reset(struct rtsx_chip *chip)
513 {
514 struct ms_info *ms_card = &chip->ms_card;
515 int retval;
516 u8 oc_mask = 0;
517
518 ms_card->ms_type = 0;
519 ms_card->check_ms_flow = 0;
520 ms_card->switch_8bit_fail = 0;
521 ms_card->delay_write.delay_write_flag = 0;
522
523 ms_card->pro_under_formatting = 0;
524
525 retval = ms_power_off_card3v3(chip);
526 if (retval != STATUS_SUCCESS) {
527 return STATUS_FAIL;
528 }
529
530 if (!chip->ft2_fast_mode)
531 wait_timeout(250);
532
533 retval = enable_card_clock(chip, MS_CARD);
534 if (retval != STATUS_SUCCESS) {
535 return STATUS_FAIL;
536 }
537
538 if (chip->asic_code) {
539 retval = ms_pull_ctl_enable(chip);
540 if (retval != STATUS_SUCCESS) {
541 return STATUS_FAIL;
542 }
543 } else {
544 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
545 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
546 if (retval) {
547 return retval;
548 }
549 }
550
551 if (!chip->ft2_fast_mode) {
552 retval = card_power_on(chip, MS_CARD);
553 if (retval != STATUS_SUCCESS) {
554 return STATUS_FAIL;
555 }
556
557 wait_timeout(150);
558
559 #ifdef SUPPORT_OCP
560 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
561 oc_mask = MS_OC_NOW | MS_OC_EVER;
562 else
563 oc_mask = SD_OC_NOW | SD_OC_EVER;
564
565 if (chip->ocp_stat & oc_mask) {
566 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
567 chip->ocp_stat);
568 return STATUS_FAIL;
569 }
570 #endif
571 }
572
573 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
574 MS_OUTPUT_EN);
575 if (retval) {
576 return retval;
577 }
578
579 if (chip->asic_code) {
580 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
581 SAMPLE_TIME_RISING |
582 PUSH_TIME_DEFAULT |
583 NO_EXTEND_TOGGLE |
584 MS_BUS_WIDTH_1);
585 if (retval) {
586 return retval;
587 }
588 } else {
589 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
590 SAMPLE_TIME_FALLING |
591 PUSH_TIME_DEFAULT |
592 NO_EXTEND_TOGGLE |
593 MS_BUS_WIDTH_1);
594 if (retval) {
595 return retval;
596 }
597 }
598 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF,
599 NO_WAIT_INT | NO_AUTO_READ_INT_REG);
600 if (retval) {
601 return retval;
602 }
603 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR,
604 MS_STOP | MS_CLR_ERR);
605 if (retval) {
606 return retval;
607 }
608
609 retval = ms_set_init_para(chip);
610 if (retval != STATUS_SUCCESS) {
611 return STATUS_FAIL;
612 }
613
614 return STATUS_SUCCESS;
615 }
616
617 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
618 {
619 struct ms_info *ms_card = &chip->ms_card;
620 int retval, i;
621 u8 val;
622
623 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
624 if (retval != STATUS_SUCCESS) {
625 return STATUS_FAIL;
626 }
627
628 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
629 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
630 6, NO_WAIT_INT);
631 if (retval == STATUS_SUCCESS)
632 break;
633 }
634 if (i == MS_MAX_RETRY_COUNT) {
635 return STATUS_FAIL;
636 }
637
638 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val);
639 if (retval) {
640 return retval;
641 }
642 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);
643 if (val != 0x01) {
644 if (val != 0x02)
645 ms_card->check_ms_flow = 1;
646
647 return STATUS_FAIL;
648 }
649
650 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val);
651 if (retval) {
652 return retval;
653 }
654 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);
655 if (val != 0) {
656 ms_card->check_ms_flow = 1;
657 return STATUS_FAIL;
658 }
659
660 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val);
661 if (retval) {
662 return retval;
663 }
664 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);
665 if (val == 0) {
666 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
667 if (retval) {
668 return retval;
669 }
670 if (val & WRT_PRTCT)
671 chip->card_wp |= MS_CARD;
672 else
673 chip->card_wp &= ~MS_CARD;
674
675 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
676 chip->card_wp |= MS_CARD;
677 } else {
678 ms_card->check_ms_flow = 1;
679 return STATUS_FAIL;
680 }
681
682 ms_card->ms_type |= TYPE_MSPRO;
683
684 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val);
685 if (retval) {
686 return retval;
687 }
688 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);
689 if (val == 0) {
690 ms_card->ms_type &= 0x0F;
691 } else if (val == 7) {
692 if (switch_8bit_bus)
693 ms_card->ms_type |= MS_HG;
694 else
695 ms_card->ms_type &= 0x0F;
696
697 } else {
698 return STATUS_FAIL;
699 }
700
701 return STATUS_SUCCESS;
702 }
703
704 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
705 {
706 int retval, i, k;
707 u8 val;
708
709 /* Confirm CPU StartUp */
710 k = 0;
711 do {
712 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
713 ms_set_err_code(chip, MS_NO_CARD);
714 return STATUS_FAIL;
715 }
716
717 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
718 retval = ms_read_bytes(chip, GET_INT, 1,
719 NO_WAIT_INT, &val, 1);
720 if (retval == STATUS_SUCCESS)
721 break;
722 }
723 if (i == MS_MAX_RETRY_COUNT) {
724 return STATUS_FAIL;
725 }
726
727 if (k > 100) {
728 return STATUS_FAIL;
729 }
730
731 k++;
732 wait_timeout(100);
733 } while (!(val & INT_REG_CED));
734
735 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
736 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
737 if (retval == STATUS_SUCCESS)
738 break;
739 }
740 if (i == MS_MAX_RETRY_COUNT) {
741 return STATUS_FAIL;
742 }
743
744 if (val & INT_REG_ERR) {
745 if (val & INT_REG_CMDNK) {
746 chip->card_wp |= (MS_CARD);
747 } else {
748 return STATUS_FAIL;
749 }
750 }
751 /* -- end confirm CPU startup */
752
753 return STATUS_SUCCESS;
754 }
755
756 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
757 {
758 int retval, i;
759 u8 data[2];
760
761 data[0] = PARALLEL_4BIT_IF;
762 data[1] = 0;
763 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
764 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
765 data, 2);
766 if (retval == STATUS_SUCCESS)
767 break;
768 }
769 if (retval != STATUS_SUCCESS) {
770 return STATUS_FAIL;
771 }
772
773 return STATUS_SUCCESS;
774 }
775
776 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
777 {
778 struct ms_info *ms_card = &chip->ms_card;
779 int retval, i;
780 u8 data[2];
781
782 data[0] = PARALLEL_8BIT_IF;
783 data[1] = 0;
784 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
785 retval = ms_write_bytes(chip, WRITE_REG, 1,
786 NO_WAIT_INT, data, 2);
787 if (retval == STATUS_SUCCESS)
788 break;
789 }
790 if (retval != STATUS_SUCCESS) {
791 return STATUS_FAIL;
792 }
793
794 retval = rtsx_write_register(chip, MS_CFG, 0x98,
795 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
796 if (retval) {
797 return retval;
798 }
799 ms_card->ms_type |= MS_8BIT;
800 retval = ms_set_init_para(chip);
801 if (retval != STATUS_SUCCESS) {
802 return STATUS_FAIL;
803 }
804
805 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
806 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
807 1, NO_WAIT_INT);
808 if (retval != STATUS_SUCCESS) {
809 return STATUS_FAIL;
810 }
811 }
812
813 return STATUS_SUCCESS;
814 }
815
816 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
817 {
818 struct ms_info *ms_card = &chip->ms_card;
819 int retval, i;
820
821 for (i = 0; i < 3; i++) {
822 retval = ms_prepare_reset(chip);
823 if (retval != STATUS_SUCCESS) {
824 return STATUS_FAIL;
825 }
826
827 retval = ms_identify_media_type(chip, switch_8bit_bus);
828 if (retval != STATUS_SUCCESS) {
829 return STATUS_FAIL;
830 }
831
832 retval = ms_confirm_cpu_startup(chip);
833 if (retval != STATUS_SUCCESS) {
834 return STATUS_FAIL;
835 }
836
837 retval = ms_switch_parallel_bus(chip);
838 if (retval != STATUS_SUCCESS) {
839 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
840 ms_set_err_code(chip, MS_NO_CARD);
841 return STATUS_FAIL;
842 }
843 continue;
844 } else {
845 break;
846 }
847 }
848
849 if (retval != STATUS_SUCCESS) {
850 return STATUS_FAIL;
851 }
852
853 /* Switch MS-PRO into Parallel mode */
854 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
855 if (retval) {
856 return retval;
857 }
858 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD,
859 PUSH_TIME_ODD);
860 if (retval) {
861 return retval;
862 }
863
864 retval = ms_set_init_para(chip);
865 if (retval != STATUS_SUCCESS) {
866 return STATUS_FAIL;
867 }
868
869 /* If MSPro HG Card, We shall try to switch to 8-bit bus */
870 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
871 retval = ms_switch_8bit_bus(chip);
872 if (retval != STATUS_SUCCESS) {
873 ms_card->switch_8bit_fail = 1;
874 return STATUS_FAIL;
875 }
876 }
877
878 return STATUS_SUCCESS;
879 }
880
881 #ifdef XC_POWERCLASS
882 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
883 {
884 int retval;
885 u8 buf[6];
886
887 ms_cleanup_work(chip);
888
889 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
890 if (retval != STATUS_SUCCESS) {
891 return STATUS_FAIL;
892 }
893
894 buf[0] = 0;
895 buf[1] = mode;
896 buf[2] = 0;
897 buf[3] = 0;
898 buf[4] = 0;
899 buf[5] = 0;
900
901 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
902 if (retval != STATUS_SUCCESS) {
903 return STATUS_FAIL;
904 }
905
906 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
907 if (retval != STATUS_SUCCESS) {
908 return STATUS_FAIL;
909 }
910
911 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf);
912 if (retval) {
913 return retval;
914 }
915 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {
916 return STATUS_FAIL;
917 }
918
919 return STATUS_SUCCESS;
920 }
921 #endif
922
923 static int ms_read_attribute_info(struct rtsx_chip *chip)
924 {
925 struct ms_info *ms_card = &chip->ms_card;
926 int retval, i;
927 u8 val, *buf, class_code, device_type, sub_class, data[16];
928 u16 total_blk = 0, blk_size = 0;
929 #ifdef SUPPORT_MSXC
930 u32 xc_total_blk = 0, xc_blk_size = 0;
931 #endif
932 u32 sys_info_addr = 0, sys_info_size;
933 #ifdef SUPPORT_PCGL_1P18
934 u32 model_name_addr = 0, model_name_size;
935 int found_sys_info = 0, found_model_name = 0;
936 #endif
937
938 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
939 if (retval != STATUS_SUCCESS) {
940 return STATUS_FAIL;
941 }
942
943 if (CHK_MS8BIT(ms_card))
944 data[0] = PARALLEL_8BIT_IF;
945 else
946 data[0] = PARALLEL_4BIT_IF;
947
948 data[1] = 0;
949
950 data[2] = 0x40;
951 data[3] = 0;
952 data[4] = 0;
953 data[5] = 0;
954 data[6] = 0;
955 data[7] = 0;
956
957 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
958 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
959 data, 8);
960 if (retval == STATUS_SUCCESS)
961 break;
962 }
963 if (retval != STATUS_SUCCESS) {
964 return STATUS_FAIL;
965 }
966
967 buf = kmalloc(64 * 512, GFP_KERNEL);
968 if (!buf) {
969 return STATUS_ERROR;
970 }
971
972 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
973 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
974 if (retval != STATUS_SUCCESS)
975 continue;
976
977 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
978 if (retval != STATUS_SUCCESS) {
979 kfree(buf);
980 return STATUS_FAIL;
981 }
982 if (!(val & MS_INT_BREQ)) {
983 kfree(buf);
984 return STATUS_FAIL;
985 }
986 retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
987 PRO_READ_LONG_DATA, 0x40, WAIT_INT,
988 0, 0, buf, 64 * 512);
989 if (retval == STATUS_SUCCESS)
990 break;
991
992 rtsx_clear_ms_error(chip);
993 }
994 if (retval != STATUS_SUCCESS) {
995 kfree(buf);
996 return STATUS_FAIL;
997 }
998
999 i = 0;
1000 do {
1001 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
1002 if (retval != STATUS_SUCCESS) {
1003 kfree(buf);
1004 return STATUS_FAIL;
1005 }
1006
1007 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
1008 break;
1009
1010 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
1011 PRO_READ_LONG_DATA, 0, WAIT_INT);
1012 if (retval != STATUS_SUCCESS) {
1013 kfree(buf);
1014 return STATUS_FAIL;
1015 }
1016
1017 i++;
1018 } while (i < 1024);
1019
1020 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
1021 /* Signature code is wrong */
1022 kfree(buf);
1023 return STATUS_FAIL;
1024 }
1025
1026 if ((buf[4] < 1) || (buf[4] > 12)) {
1027 kfree(buf);
1028 return STATUS_FAIL;
1029 }
1030
1031 for (i = 0; i < buf[4]; i++) {
1032 int cur_addr_off = 16 + i * 12;
1033
1034 #ifdef SUPPORT_MSXC
1035 if ((buf[cur_addr_off + 8] == 0x10) ||
1036 (buf[cur_addr_off + 8] == 0x13)) {
1037 #else
1038 if (buf[cur_addr_off + 8] == 0x10) {
1039 #endif
1040 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1041 ((u32)buf[cur_addr_off + 1] << 16) |
1042 ((u32)buf[cur_addr_off + 2] << 8) |
1043 buf[cur_addr_off + 3];
1044 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
1045 ((u32)buf[cur_addr_off + 5] << 16) |
1046 ((u32)buf[cur_addr_off + 6] << 8) |
1047 buf[cur_addr_off + 7];
1048 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
1049 sys_info_addr, sys_info_size);
1050 if (sys_info_size != 96) {
1051 kfree(buf);
1052 return STATUS_FAIL;
1053 }
1054 if (sys_info_addr < 0x1A0) {
1055 kfree(buf);
1056 return STATUS_FAIL;
1057 }
1058 if ((sys_info_size + sys_info_addr) > 0x8000) {
1059 kfree(buf);
1060 return STATUS_FAIL;
1061 }
1062
1063 #ifdef SUPPORT_MSXC
1064 if (buf[cur_addr_off + 8] == 0x13)
1065 ms_card->ms_type |= MS_XC;
1066 #endif
1067 #ifdef SUPPORT_PCGL_1P18
1068 found_sys_info = 1;
1069 #else
1070 break;
1071 #endif
1072 }
1073 #ifdef SUPPORT_PCGL_1P18
1074 if (buf[cur_addr_off + 8] == 0x15) {
1075 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1076 ((u32)buf[cur_addr_off + 1] << 16) |
1077 ((u32)buf[cur_addr_off + 2] << 8) |
1078 buf[cur_addr_off + 3];
1079 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
1080 ((u32)buf[cur_addr_off + 5] << 16) |
1081 ((u32)buf[cur_addr_off + 6] << 8) |
1082 buf[cur_addr_off + 7];
1083 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n",
1084 model_name_addr, model_name_size);
1085 if (model_name_size != 48) {
1086 kfree(buf);
1087 return STATUS_FAIL;
1088 }
1089 if (model_name_addr < 0x1A0) {
1090 kfree(buf);
1091 return STATUS_FAIL;
1092 }
1093 if ((model_name_size + model_name_addr) > 0x8000) {
1094 kfree(buf);
1095 return STATUS_FAIL;
1096 }
1097
1098 found_model_name = 1;
1099 }
1100
1101 if (found_sys_info && found_model_name)
1102 break;
1103 #endif
1104 }
1105
1106 if (i == buf[4]) {
1107 kfree(buf);
1108 return STATUS_FAIL;
1109 }
1110
1111 class_code = buf[sys_info_addr + 0];
1112 device_type = buf[sys_info_addr + 56];
1113 sub_class = buf[sys_info_addr + 46];
1114 #ifdef SUPPORT_MSXC
1115 if (CHK_MSXC(ms_card)) {
1116 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
1117 ((u32)buf[sys_info_addr + 7] << 16) |
1118 ((u32)buf[sys_info_addr + 8] << 8) |
1119 buf[sys_info_addr + 9];
1120 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1121 ((u32)buf[sys_info_addr + 33] << 16) |
1122 ((u32)buf[sys_info_addr + 34] << 8) |
1123 buf[sys_info_addr + 35];
1124 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1125 xc_total_blk, xc_blk_size);
1126 } else {
1127 total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
1128 buf[sys_info_addr + 7];
1129 blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
1130 buf[sys_info_addr + 3];
1131 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1132 total_blk, blk_size);
1133 }
1134 #else
1135 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1136 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1137 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1138 total_blk, blk_size);
1139 #endif
1140
1141 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1142 class_code, device_type, sub_class);
1143
1144 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1145 #ifdef SUPPORT_PCGL_1P18
1146 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1147 #endif
1148
1149 kfree(buf);
1150
1151 #ifdef SUPPORT_MSXC
1152 if (CHK_MSXC(ms_card)) {
1153 if (class_code != 0x03) {
1154 return STATUS_FAIL;
1155 }
1156 } else {
1157 if (class_code != 0x02) {
1158 return STATUS_FAIL;
1159 }
1160 }
1161 #else
1162 if (class_code != 0x02) {
1163 return STATUS_FAIL;
1164 }
1165 #endif
1166
1167 if (device_type != 0x00) {
1168 if ((device_type == 0x01) || (device_type == 0x02) ||
1169 (device_type == 0x03)) {
1170 chip->card_wp |= MS_CARD;
1171 } else {
1172 return STATUS_FAIL;
1173 }
1174 }
1175
1176 if (sub_class & 0xC0) {
1177 return STATUS_FAIL;
1178 }
1179
1180 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1181 class_code, device_type, sub_class);
1182
1183 #ifdef SUPPORT_MSXC
1184 if (CHK_MSXC(ms_card)) {
1185 chip->capacity[chip->card2lun[MS_CARD]] =
1186 ms_card->capacity = xc_total_blk * xc_blk_size;
1187 } else {
1188 chip->capacity[chip->card2lun[MS_CARD]] =
1189 ms_card->capacity = total_blk * blk_size;
1190 }
1191 #else
1192 ms_card->capacity = total_blk * blk_size;
1193 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1194 #endif
1195
1196 return STATUS_SUCCESS;
1197 }
1198
1199 #ifdef SUPPORT_MAGIC_GATE
1200 static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
1201 int type, u8 mg_entry_num);
1202 #endif
1203
1204 static int reset_ms_pro(struct rtsx_chip *chip)
1205 {
1206 struct ms_info *ms_card = &chip->ms_card;
1207 int retval;
1208 #ifdef XC_POWERCLASS
1209 u8 change_power_class;
1210
1211 if (chip->ms_power_class_en & 0x02)
1212 change_power_class = 2;
1213 else if (chip->ms_power_class_en & 0x01)
1214 change_power_class = 1;
1215 else
1216 change_power_class = 0;
1217 #endif
1218
1219 #ifdef XC_POWERCLASS
1220 retry:
1221 #endif
1222 retval = ms_pro_reset_flow(chip, 1);
1223 if (retval != STATUS_SUCCESS) {
1224 if (ms_card->switch_8bit_fail) {
1225 retval = ms_pro_reset_flow(chip, 0);
1226 if (retval != STATUS_SUCCESS) {
1227 return STATUS_FAIL;
1228 }
1229 } else {
1230 return STATUS_FAIL;
1231 }
1232 }
1233
1234 retval = ms_read_attribute_info(chip);
1235 if (retval != STATUS_SUCCESS) {
1236 return STATUS_FAIL;
1237 }
1238
1239 #ifdef XC_POWERCLASS
1240 if (CHK_HG8BIT(ms_card))
1241 change_power_class = 0;
1242
1243 if (change_power_class && CHK_MSXC(ms_card)) {
1244 u8 power_class_en = chip->ms_power_class_en;
1245
1246 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n",
1247 power_class_en);
1248 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n",
1249 change_power_class);
1250
1251 if (change_power_class)
1252 power_class_en &= (1 << (change_power_class - 1));
1253 else
1254 power_class_en = 0;
1255
1256 if (power_class_en) {
1257 u8 power_class_mode =
1258 (ms_card->raw_sys_info[46] & 0x18) >> 3;
1259 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x",
1260 power_class_mode);
1261 if (change_power_class > power_class_mode)
1262 change_power_class = power_class_mode;
1263 if (change_power_class) {
1264 retval = msxc_change_power(chip,
1265 change_power_class);
1266 if (retval != STATUS_SUCCESS) {
1267 change_power_class--;
1268 goto retry;
1269 }
1270 }
1271 }
1272 }
1273 #endif
1274
1275 #ifdef SUPPORT_MAGIC_GATE
1276 retval = mg_set_tpc_para_sub(chip, 0, 0);
1277 if (retval != STATUS_SUCCESS) {
1278 return STATUS_FAIL;
1279 }
1280 #endif
1281
1282 if (CHK_HG8BIT(ms_card))
1283 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1284 else
1285 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1286
1287 return STATUS_SUCCESS;
1288 }
1289
1290 static int ms_read_status_reg(struct rtsx_chip *chip)
1291 {
1292 int retval;
1293 u8 val[2];
1294
1295 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1296 if (retval != STATUS_SUCCESS) {
1297 return STATUS_FAIL;
1298 }
1299
1300 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1301 if (retval != STATUS_SUCCESS) {
1302 return STATUS_FAIL;
1303 }
1304
1305 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1306 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1307 return STATUS_FAIL;
1308 }
1309
1310 return STATUS_SUCCESS;
1311 }
1312
1313 static int ms_read_extra_data(struct rtsx_chip *chip,
1314 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1315 {
1316 struct ms_info *ms_card = &chip->ms_card;
1317 int retval, i;
1318 u8 val, data[10];
1319
1320 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1321 SystemParm, 6);
1322 if (retval != STATUS_SUCCESS) {
1323 return STATUS_FAIL;
1324 }
1325
1326 if (CHK_MS4BIT(ms_card)) {
1327 /* Parallel interface */
1328 data[0] = 0x88;
1329 } else {
1330 /* Serial interface */
1331 data[0] = 0x80;
1332 }
1333 data[1] = 0;
1334 data[2] = (u8)(block_addr >> 8);
1335 data[3] = (u8)block_addr;
1336 data[4] = 0x40;
1337 data[5] = page_num;
1338
1339 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1340 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1341 data, 6);
1342 if (retval == STATUS_SUCCESS)
1343 break;
1344 }
1345 if (i == MS_MAX_RETRY_COUNT) {
1346 return STATUS_FAIL;
1347 }
1348
1349 ms_set_err_code(chip, MS_NO_ERROR);
1350
1351 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1352 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1353 if (retval == STATUS_SUCCESS)
1354 break;
1355 }
1356 if (i == MS_MAX_RETRY_COUNT) {
1357 return STATUS_FAIL;
1358 }
1359
1360 ms_set_err_code(chip, MS_NO_ERROR);
1361 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1362 if (retval != STATUS_SUCCESS) {
1363 return STATUS_FAIL;
1364 }
1365
1366 if (val & INT_REG_CMDNK) {
1367 ms_set_err_code(chip, MS_CMD_NK);
1368 return STATUS_FAIL;
1369 }
1370 if (val & INT_REG_CED) {
1371 if (val & INT_REG_ERR) {
1372 retval = ms_read_status_reg(chip);
1373 if (retval != STATUS_SUCCESS) {
1374 return STATUS_FAIL;
1375 }
1376
1377 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1378 MS_EXTRA_SIZE, SystemParm,
1379 6);
1380 if (retval != STATUS_SUCCESS) {
1381 return STATUS_FAIL;
1382 }
1383 }
1384 }
1385
1386 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
1387 data, MS_EXTRA_SIZE);
1388 if (retval != STATUS_SUCCESS) {
1389 return STATUS_FAIL;
1390 }
1391
1392 if (buf && buf_len) {
1393 if (buf_len > MS_EXTRA_SIZE)
1394 buf_len = MS_EXTRA_SIZE;
1395 memcpy(buf, data, buf_len);
1396 }
1397
1398 return STATUS_SUCCESS;
1399 }
1400
1401 static int ms_write_extra_data(struct rtsx_chip *chip, u16 block_addr,
1402 u8 page_num, u8 *buf, int buf_len)
1403 {
1404 struct ms_info *ms_card = &chip->ms_card;
1405 int retval, i;
1406 u8 val, data[16];
1407
1408 if (!buf || (buf_len < MS_EXTRA_SIZE)) {
1409 return STATUS_FAIL;
1410 }
1411
1412 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1413 SystemParm, 6 + MS_EXTRA_SIZE);
1414 if (retval != STATUS_SUCCESS) {
1415 return STATUS_FAIL;
1416 }
1417
1418 if (CHK_MS4BIT(ms_card))
1419 data[0] = 0x88;
1420 else
1421 data[0] = 0x80;
1422
1423 data[1] = 0;
1424 data[2] = (u8)(block_addr >> 8);
1425 data[3] = (u8)block_addr;
1426 data[4] = 0x40;
1427 data[5] = page_num;
1428
1429 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1430 data[i] = buf[i - 6];
1431
1432 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1433 NO_WAIT_INT, data, 16);
1434 if (retval != STATUS_SUCCESS) {
1435 return STATUS_FAIL;
1436 }
1437
1438 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1439 if (retval != STATUS_SUCCESS) {
1440 return STATUS_FAIL;
1441 }
1442
1443 ms_set_err_code(chip, MS_NO_ERROR);
1444 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1445 if (retval != STATUS_SUCCESS) {
1446 return STATUS_FAIL;
1447 }
1448
1449 if (val & INT_REG_CMDNK) {
1450 ms_set_err_code(chip, MS_CMD_NK);
1451 return STATUS_FAIL;
1452 }
1453 if (val & INT_REG_CED) {
1454 if (val & INT_REG_ERR) {
1455 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1456 return STATUS_FAIL;
1457 }
1458 }
1459
1460 return STATUS_SUCCESS;
1461 }
1462
1463 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1464 {
1465 struct ms_info *ms_card = &chip->ms_card;
1466 int retval;
1467 u8 val, data[6];
1468
1469 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1470 SystemParm, 6);
1471 if (retval != STATUS_SUCCESS) {
1472 return STATUS_FAIL;
1473 }
1474
1475 if (CHK_MS4BIT(ms_card))
1476 data[0] = 0x88;
1477 else
1478 data[0] = 0x80;
1479
1480 data[1] = 0;
1481 data[2] = (u8)(block_addr >> 8);
1482 data[3] = (u8)block_addr;
1483 data[4] = 0x20;
1484 data[5] = page_num;
1485
1486 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1487 if (retval != STATUS_SUCCESS) {
1488 return STATUS_FAIL;
1489 }
1490
1491 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1492 if (retval != STATUS_SUCCESS) {
1493 return STATUS_FAIL;
1494 }
1495
1496 ms_set_err_code(chip, MS_NO_ERROR);
1497 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1498 if (retval != STATUS_SUCCESS) {
1499 return STATUS_FAIL;
1500 }
1501
1502 if (val & INT_REG_CMDNK) {
1503 ms_set_err_code(chip, MS_CMD_NK);
1504 return STATUS_FAIL;
1505 }
1506
1507 if (val & INT_REG_CED) {
1508 if (val & INT_REG_ERR) {
1509 if (!(val & INT_REG_BREQ)) {
1510 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1511 return STATUS_FAIL;
1512 }
1513 retval = ms_read_status_reg(chip);
1514 if (retval != STATUS_SUCCESS)
1515 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1516
1517 } else {
1518 if (!(val & INT_REG_BREQ)) {
1519 ms_set_err_code(chip, MS_BREQ_ERROR);
1520 return STATUS_FAIL;
1521 }
1522 }
1523 }
1524
1525 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
1526 0, NO_WAIT_INT);
1527 if (retval != STATUS_SUCCESS) {
1528 return STATUS_FAIL;
1529 }
1530
1531 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1532 return STATUS_FAIL;
1533 }
1534
1535 return STATUS_SUCCESS;
1536 }
1537
1538 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1539 {
1540 struct ms_info *ms_card = &chip->ms_card;
1541 int retval;
1542 u8 val, data[8], extra[MS_EXTRA_SIZE];
1543
1544 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1545 if (retval != STATUS_SUCCESS) {
1546 return STATUS_FAIL;
1547 }
1548
1549 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1550 SystemParm, 7);
1551 if (retval != STATUS_SUCCESS) {
1552 return STATUS_FAIL;
1553 }
1554
1555 ms_set_err_code(chip, MS_NO_ERROR);
1556
1557 if (CHK_MS4BIT(ms_card))
1558 data[0] = 0x88;
1559 else
1560 data[0] = 0x80;
1561
1562 data[1] = 0;
1563 data[2] = (u8)(phy_blk >> 8);
1564 data[3] = (u8)phy_blk;
1565 data[4] = 0x80;
1566 data[5] = 0;
1567 data[6] = extra[0] & 0x7F;
1568 data[7] = 0xFF;
1569
1570 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1571 if (retval != STATUS_SUCCESS) {
1572 return STATUS_FAIL;
1573 }
1574
1575 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1576 if (retval != STATUS_SUCCESS) {
1577 return STATUS_FAIL;
1578 }
1579
1580 ms_set_err_code(chip, MS_NO_ERROR);
1581 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1582 if (retval != STATUS_SUCCESS) {
1583 return STATUS_FAIL;
1584 }
1585
1586 if (val & INT_REG_CMDNK) {
1587 ms_set_err_code(chip, MS_CMD_NK);
1588 return STATUS_FAIL;
1589 }
1590
1591 if (val & INT_REG_CED) {
1592 if (val & INT_REG_ERR) {
1593 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1594 return STATUS_FAIL;
1595 }
1596 }
1597
1598 return STATUS_SUCCESS;
1599 }
1600
1601 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1602 {
1603 struct ms_info *ms_card = &chip->ms_card;
1604 int retval, i = 0;
1605 u8 val, data[6];
1606
1607 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1608 SystemParm, 6);
1609 if (retval != STATUS_SUCCESS) {
1610 return STATUS_FAIL;
1611 }
1612
1613 ms_set_err_code(chip, MS_NO_ERROR);
1614
1615 if (CHK_MS4BIT(ms_card))
1616 data[0] = 0x88;
1617 else
1618 data[0] = 0x80;
1619
1620 data[1] = 0;
1621 data[2] = (u8)(phy_blk >> 8);
1622 data[3] = (u8)phy_blk;
1623 data[4] = 0;
1624 data[5] = 0;
1625
1626 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1627 if (retval != STATUS_SUCCESS) {
1628 return STATUS_FAIL;
1629 }
1630
1631 ERASE_RTY:
1632 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1633 if (retval != STATUS_SUCCESS) {
1634 return STATUS_FAIL;
1635 }
1636
1637 ms_set_err_code(chip, MS_NO_ERROR);
1638 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1639 if (retval != STATUS_SUCCESS) {
1640 return STATUS_FAIL;
1641 }
1642
1643 if (val & INT_REG_CMDNK) {
1644 if (i < 3) {
1645 i++;
1646 goto ERASE_RTY;
1647 }
1648
1649 ms_set_err_code(chip, MS_CMD_NK);
1650 ms_set_bad_block(chip, phy_blk);
1651 return STATUS_FAIL;
1652 }
1653
1654 if (val & INT_REG_CED) {
1655 if (val & INT_REG_ERR) {
1656 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1657 return STATUS_FAIL;
1658 }
1659 }
1660
1661 return STATUS_SUCCESS;
1662 }
1663
1664 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1665 {
1666 if (!extra || (extra_len < MS_EXTRA_SIZE))
1667 return;
1668
1669 memset(extra, 0xFF, MS_EXTRA_SIZE);
1670
1671 if (type == setPS_NG) {
1672 /* set page status as 1:NG,and block status keep 1:OK */
1673 extra[0] = 0xB8;
1674 } else {
1675 /* set page status as 0:Data Error,and block status keep 1:OK */
1676 extra[0] = 0x98;
1677 }
1678
1679 extra[2] = (u8)(log_blk >> 8);
1680 extra[3] = (u8)log_blk;
1681 }
1682
1683 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
1684 u8 start_page, u8 end_page)
1685 {
1686 int retval;
1687 u8 extra[MS_EXTRA_SIZE], i;
1688
1689 memset(extra, 0xff, MS_EXTRA_SIZE);
1690
1691 extra[0] = 0xf8; /* Block, page OK, data erased */
1692 extra[1] = 0xff;
1693 extra[2] = (u8)(log_blk >> 8);
1694 extra[3] = (u8)log_blk;
1695
1696 for (i = start_page; i < end_page; i++) {
1697 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1698 ms_set_err_code(chip, MS_NO_CARD);
1699 return STATUS_FAIL;
1700 }
1701
1702 retval = ms_write_extra_data(chip, phy_blk, i,
1703 extra, MS_EXTRA_SIZE);
1704 if (retval != STATUS_SUCCESS) {
1705 return STATUS_FAIL;
1706 }
1707 }
1708
1709 return STATUS_SUCCESS;
1710 }
1711
1712 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1713 u16 log_blk, u8 start_page, u8 end_page)
1714 {
1715 struct ms_info *ms_card = &chip->ms_card;
1716 bool uncorrect_flag = false;
1717 int retval, rty_cnt;
1718 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1719
1720 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1721 old_blk, new_blk, log_blk);
1722 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n",
1723 start_page, end_page);
1724
1725 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1726 if (retval != STATUS_SUCCESS) {
1727 return STATUS_FAIL;
1728 }
1729
1730 retval = ms_read_status_reg(chip);
1731 if (retval != STATUS_SUCCESS) {
1732 return STATUS_FAIL;
1733 }
1734
1735 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
1736 if (retval) {
1737 return retval;
1738 }
1739
1740 if (val & BUF_FULL) {
1741 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1742 if (retval != STATUS_SUCCESS) {
1743 return STATUS_FAIL;
1744 }
1745
1746 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1747 if (retval != STATUS_SUCCESS) {
1748 return STATUS_FAIL;
1749 }
1750
1751 if (!(val & INT_REG_CED)) {
1752 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1753 return STATUS_FAIL;
1754 }
1755 }
1756
1757 for (i = start_page; i < end_page; i++) {
1758 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1759 ms_set_err_code(chip, MS_NO_CARD);
1760 return STATUS_FAIL;
1761 }
1762
1763 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1764
1765 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1766 MS_EXTRA_SIZE, SystemParm, 6);
1767 if (retval != STATUS_SUCCESS) {
1768 return STATUS_FAIL;
1769 }
1770
1771 ms_set_err_code(chip, MS_NO_ERROR);
1772
1773 if (CHK_MS4BIT(ms_card))
1774 data[0] = 0x88;
1775 else
1776 data[0] = 0x80;
1777
1778 data[1] = 0;
1779 data[2] = (u8)(old_blk >> 8);
1780 data[3] = (u8)old_blk;
1781 data[4] = 0x20;
1782 data[5] = i;
1783
1784 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1785 data, 6);
1786 if (retval != STATUS_SUCCESS) {
1787 return STATUS_FAIL;
1788 }
1789
1790 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1791 if (retval != STATUS_SUCCESS) {
1792 return STATUS_FAIL;
1793 }
1794
1795 ms_set_err_code(chip, MS_NO_ERROR);
1796 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1797 if (retval != STATUS_SUCCESS) {
1798 return STATUS_FAIL;
1799 }
1800
1801 if (val & INT_REG_CMDNK) {
1802 ms_set_err_code(chip, MS_CMD_NK);
1803 return STATUS_FAIL;
1804 }
1805
1806 if (val & INT_REG_CED) {
1807 if (val & INT_REG_ERR) {
1808 retval = ms_read_status_reg(chip);
1809 if (retval != STATUS_SUCCESS) {
1810 uncorrect_flag = true;
1811 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n");
1812 } else {
1813 uncorrect_flag = false;
1814 }
1815
1816 retval = ms_transfer_tpc(chip,
1817 MS_TM_NORMAL_READ,
1818 READ_PAGE_DATA,
1819 0, NO_WAIT_INT);
1820 if (retval != STATUS_SUCCESS) {
1821 return STATUS_FAIL;
1822 }
1823
1824 if (uncorrect_flag) {
1825 ms_set_page_status(log_blk, setPS_NG,
1826 extra,
1827 MS_EXTRA_SIZE);
1828 if (i == 0)
1829 extra[0] &= 0xEF;
1830
1831 ms_write_extra_data(chip, old_blk, i,
1832 extra,
1833 MS_EXTRA_SIZE);
1834 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n",
1835 i, extra[0]);
1836 MS_SET_BAD_BLOCK_FLG(ms_card);
1837
1838 ms_set_page_status(log_blk, setPS_Error,
1839 extra,
1840 MS_EXTRA_SIZE);
1841 ms_write_extra_data(chip, new_blk, i,
1842 extra,
1843 MS_EXTRA_SIZE);
1844 continue;
1845 }
1846
1847 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
1848 rty_cnt++) {
1849 retval = ms_transfer_tpc(
1850 chip,
1851 MS_TM_NORMAL_WRITE,
1852 WRITE_PAGE_DATA,
1853 0, NO_WAIT_INT);
1854 if (retval == STATUS_SUCCESS)
1855 break;
1856 }
1857 if (rty_cnt == MS_MAX_RETRY_COUNT) {
1858 return STATUS_FAIL;
1859 }
1860 }
1861
1862 if (!(val & INT_REG_BREQ)) {
1863 ms_set_err_code(chip, MS_BREQ_ERROR);
1864 return STATUS_FAIL;
1865 }
1866 }
1867
1868 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1869 SystemParm, (6 + MS_EXTRA_SIZE));
1870
1871 ms_set_err_code(chip, MS_NO_ERROR);
1872
1873 if (CHK_MS4BIT(ms_card))
1874 data[0] = 0x88;
1875 else
1876 data[0] = 0x80;
1877
1878 data[1] = 0;
1879 data[2] = (u8)(new_blk >> 8);
1880 data[3] = (u8)new_blk;
1881 data[4] = 0x20;
1882 data[5] = i;
1883
1884 if ((extra[0] & 0x60) != 0x60)
1885 data[6] = extra[0];
1886 else
1887 data[6] = 0xF8;
1888
1889 data[6 + 1] = 0xFF;
1890 data[6 + 2] = (u8)(log_blk >> 8);
1891 data[6 + 3] = (u8)log_blk;
1892
1893 for (j = 4; j <= MS_EXTRA_SIZE; j++)
1894 data[6 + j] = 0xFF;
1895
1896 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1897 NO_WAIT_INT, data, 16);
1898 if (retval != STATUS_SUCCESS) {
1899 return STATUS_FAIL;
1900 }
1901
1902 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1903 if (retval != STATUS_SUCCESS) {
1904 return STATUS_FAIL;
1905 }
1906
1907 ms_set_err_code(chip, MS_NO_ERROR);
1908 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1909 if (retval != STATUS_SUCCESS) {
1910 return STATUS_FAIL;
1911 }
1912
1913 if (val & INT_REG_CMDNK) {
1914 ms_set_err_code(chip, MS_CMD_NK);
1915 return STATUS_FAIL;
1916 }
1917
1918 if (val & INT_REG_CED) {
1919 if (val & INT_REG_ERR) {
1920 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1921 return STATUS_FAIL;
1922 }
1923 }
1924
1925 if (i == 0) {
1926 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1927 MS_EXTRA_SIZE, SystemParm,
1928 7);
1929 if (retval != STATUS_SUCCESS) {
1930 return STATUS_FAIL;
1931 }
1932
1933 ms_set_err_code(chip, MS_NO_ERROR);
1934
1935 if (CHK_MS4BIT(ms_card))
1936 data[0] = 0x88;
1937 else
1938 data[0] = 0x80;
1939
1940 data[1] = 0;
1941 data[2] = (u8)(old_blk >> 8);
1942 data[3] = (u8)old_blk;
1943 data[4] = 0x80;
1944 data[5] = 0;
1945 data[6] = 0xEF;
1946 data[7] = 0xFF;
1947
1948 retval = ms_write_bytes(chip, WRITE_REG, 7,
1949 NO_WAIT_INT, data, 8);
1950 if (retval != STATUS_SUCCESS) {
1951 return STATUS_FAIL;
1952 }
1953
1954 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1955 if (retval != STATUS_SUCCESS) {
1956 return STATUS_FAIL;
1957 }
1958
1959 ms_set_err_code(chip, MS_NO_ERROR);
1960 retval = ms_read_bytes(chip, GET_INT, 1,
1961 NO_WAIT_INT, &val, 1);
1962 if (retval != STATUS_SUCCESS) {
1963 return STATUS_FAIL;
1964 }
1965
1966 if (val & INT_REG_CMDNK) {
1967 ms_set_err_code(chip, MS_CMD_NK);
1968 return STATUS_FAIL;
1969 }
1970
1971 if (val & INT_REG_CED) {
1972 if (val & INT_REG_ERR) {
1973 ms_set_err_code(chip,
1974 MS_FLASH_WRITE_ERROR);
1975 return STATUS_FAIL;
1976 }
1977 }
1978 }
1979 }
1980
1981 return STATUS_SUCCESS;
1982 }
1983
1984 static int reset_ms(struct rtsx_chip *chip)
1985 {
1986 struct ms_info *ms_card = &chip->ms_card;
1987 int retval;
1988 u16 i, reg_addr, block_size;
1989 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
1990 #ifndef SUPPORT_MAGIC_GATE
1991 u16 eblock_cnt;
1992 #endif
1993
1994 retval = ms_prepare_reset(chip);
1995 if (retval != STATUS_SUCCESS) {
1996 return STATUS_FAIL;
1997 }
1998
1999 ms_card->ms_type |= TYPE_MS;
2000
2001 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
2002 if (retval != STATUS_SUCCESS) {
2003 return STATUS_FAIL;
2004 }
2005
2006 retval = ms_read_status_reg(chip);
2007 if (retval != STATUS_SUCCESS) {
2008 return STATUS_FAIL;
2009 }
2010
2011 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
2012 if (retval) {
2013 return retval;
2014 }
2015 if (val & WRT_PRTCT)
2016 chip->card_wp |= MS_CARD;
2017 else
2018 chip->card_wp &= ~MS_CARD;
2019
2020 i = 0;
2021
2022 RE_SEARCH:
2023 /* Search Boot Block */
2024 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
2025 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2026 ms_set_err_code(chip, MS_NO_CARD);
2027 return STATUS_FAIL;
2028 }
2029
2030 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
2031 if (retval != STATUS_SUCCESS) {
2032 i++;
2033 continue;
2034 }
2035
2036 if (extra[0] & BLOCK_OK) {
2037 if (!(extra[1] & NOT_BOOT_BLOCK)) {
2038 ms_card->boot_block = i;
2039 break;
2040 }
2041 }
2042 i++;
2043 }
2044
2045 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
2046 dev_dbg(rtsx_dev(chip), "No boot block found!");
2047 return STATUS_FAIL;
2048 }
2049
2050 for (j = 0; j < 3; j++) {
2051 retval = ms_read_page(chip, ms_card->boot_block, j);
2052 if (retval != STATUS_SUCCESS) {
2053 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
2054 i = ms_card->boot_block + 1;
2055 ms_set_err_code(chip, MS_NO_ERROR);
2056 goto RE_SEARCH;
2057 }
2058 }
2059 }
2060
2061 retval = ms_read_page(chip, ms_card->boot_block, 0);
2062 if (retval != STATUS_SUCCESS) {
2063 return STATUS_FAIL;
2064 }
2065
2066 /* Read MS system information as sys_info */
2067 rtsx_init_cmd(chip);
2068
2069 for (i = 0; i < 96; i++)
2070 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
2071
2072 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2073 if (retval < 0) {
2074 return STATUS_FAIL;
2075 }
2076
2077 ptr = rtsx_get_cmd_data(chip);
2078 memcpy(ms_card->raw_sys_info, ptr, 96);
2079
2080 /* Read useful block contents */
2081 rtsx_init_cmd(chip);
2082
2083 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
2084 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
2085
2086 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
2087 reg_addr++)
2088 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2089
2090 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
2091 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2092
2093 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
2094 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
2095
2096 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2097 if (retval < 0) {
2098 return STATUS_FAIL;
2099 }
2100
2101 ptr = rtsx_get_cmd_data(chip);
2102
2103 dev_dbg(rtsx_dev(chip), "Boot block data:\n");
2104 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr);
2105
2106 /* Block ID error
2107 * HEADER_ID0, HEADER_ID1
2108 */
2109 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
2110 i = ms_card->boot_block + 1;
2111 goto RE_SEARCH;
2112 }
2113
2114 /* Page size error
2115 * PAGE_SIZE_0, PAGE_SIZE_1
2116 */
2117 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
2118 i = ms_card->boot_block + 1;
2119 goto RE_SEARCH;
2120 }
2121
2122 if ((ptr[14] == 1) || (ptr[14] == 3))
2123 chip->card_wp |= MS_CARD;
2124
2125 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
2126 block_size = ((u16)ptr[6] << 8) | ptr[7];
2127 if (block_size == 0x0010) {
2128 /* Block size 16KB */
2129 ms_card->block_shift = 5;
2130 ms_card->page_off = 0x1F;
2131 } else if (block_size == 0x0008) {
2132 /* Block size 8KB */
2133 ms_card->block_shift = 4;
2134 ms_card->page_off = 0x0F;
2135 }
2136
2137 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
2138 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
2139
2140 #ifdef SUPPORT_MAGIC_GATE
2141 j = ptr[10];
2142
2143 if (ms_card->block_shift == 4) { /* 4MB or 8MB */
2144 if (j < 2) { /* Effective block for 4MB: 0x1F0 */
2145 ms_card->capacity = 0x1EE0;
2146 } else { /* Effective block for 8MB: 0x3E0 */
2147 ms_card->capacity = 0x3DE0;
2148 }
2149 } else { /* 16MB, 32MB, 64MB or 128MB */
2150 if (j < 5) { /* Effective block for 16MB: 0x3E0 */
2151 ms_card->capacity = 0x7BC0;
2152 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
2153 ms_card->capacity = 0xF7C0;
2154 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
2155 ms_card->capacity = 0x1EF80;
2156 } else { /* Effective block for 128MB: 0x1F00 */
2157 ms_card->capacity = 0x3DF00;
2158 }
2159 }
2160 #else
2161 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
2162 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
2163
2164 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
2165 #endif
2166
2167 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2168
2169 /* Switch I/F Mode */
2170 if (ptr[15]) {
2171 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2172 if (retval != STATUS_SUCCESS) {
2173 return STATUS_FAIL;
2174 }
2175
2176 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88);
2177 if (retval) {
2178 return retval;
2179 }
2180 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2181 if (retval) {
2182 return retval;
2183 }
2184
2185 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
2186 NO_WAIT_INT);
2187 if (retval != STATUS_SUCCESS) {
2188 return STATUS_FAIL;
2189 }
2190
2191 retval = rtsx_write_register(chip, MS_CFG,
2192 0x58 | MS_NO_CHECK_INT,
2193 MS_BUS_WIDTH_4 |
2194 PUSH_TIME_ODD |
2195 MS_NO_CHECK_INT);
2196 if (retval) {
2197 return retval;
2198 }
2199
2200 ms_card->ms_type |= MS_4BIT;
2201 }
2202
2203 if (CHK_MS4BIT(ms_card))
2204 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2205 else
2206 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2207
2208 return STATUS_SUCCESS;
2209 }
2210
2211 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2212 {
2213 struct ms_info *ms_card = &chip->ms_card;
2214 int size, i, seg_no, retval;
2215 u16 defect_block, reg_addr;
2216 u8 val1, val2;
2217
2218 ms_card->segment_cnt = ms_card->total_block >> 9;
2219 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n",
2220 ms_card->segment_cnt);
2221
2222 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2223 ms_card->segment = vzalloc(size);
2224 if (!ms_card->segment) {
2225 return STATUS_FAIL;
2226 }
2227
2228 retval = ms_read_page(chip, ms_card->boot_block, 1);
2229 if (retval != STATUS_SUCCESS) {
2230 goto INIT_FAIL;
2231 }
2232
2233 reg_addr = PPBUF_BASE2;
2234 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2235 int block_no;
2236
2237 retval = rtsx_read_register(chip, reg_addr++, &val1);
2238 if (retval != STATUS_SUCCESS) {
2239 goto INIT_FAIL;
2240 }
2241
2242 retval = rtsx_read_register(chip, reg_addr++, &val2);
2243 if (retval != STATUS_SUCCESS) {
2244 goto INIT_FAIL;
2245 }
2246
2247 defect_block = ((u16)val1 << 8) | val2;
2248 if (defect_block == 0xFFFF)
2249 break;
2250
2251 seg_no = defect_block / 512;
2252
2253 block_no = ms_card->segment[seg_no].disable_count++;
2254 ms_card->segment[seg_no].defect_list[block_no] = defect_block;
2255 }
2256
2257 for (i = 0; i < ms_card->segment_cnt; i++) {
2258 ms_card->segment[i].build_flag = 0;
2259 ms_card->segment[i].l2p_table = NULL;
2260 ms_card->segment[i].free_table = NULL;
2261 ms_card->segment[i].get_index = 0;
2262 ms_card->segment[i].set_index = 0;
2263 ms_card->segment[i].unused_blk_cnt = 0;
2264
2265 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n",
2266 i, ms_card->segment[i].disable_count);
2267 }
2268
2269 return STATUS_SUCCESS;
2270
2271 INIT_FAIL:
2272 vfree(ms_card->segment);
2273 ms_card->segment = NULL;
2274
2275 return STATUS_FAIL;
2276 }
2277
2278 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2279 {
2280 struct ms_info *ms_card = &chip->ms_card;
2281 struct zone_entry *segment;
2282
2283 if (!ms_card->segment)
2284 return 0xFFFF;
2285
2286 segment = &ms_card->segment[seg_no];
2287
2288 if (segment->l2p_table)
2289 return segment->l2p_table[log_off];
2290
2291 return 0xFFFF;
2292 }
2293
2294 static void ms_set_l2p_tbl(struct rtsx_chip *chip,
2295 int seg_no, u16 log_off, u16 phy_blk)
2296 {
2297 struct ms_info *ms_card = &chip->ms_card;
2298 struct zone_entry *segment;
2299
2300 if (!ms_card->segment)
2301 return;
2302
2303 segment = &ms_card->segment[seg_no];
2304 if (segment->l2p_table)
2305 segment->l2p_table[log_off] = phy_blk;
2306 }
2307
2308 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2309 {
2310 struct ms_info *ms_card = &chip->ms_card;
2311 struct zone_entry *segment;
2312 int seg_no;
2313
2314 seg_no = (int)phy_blk >> 9;
2315 segment = &ms_card->segment[seg_no];
2316
2317 segment->free_table[segment->set_index++] = phy_blk;
2318 if (segment->set_index >= MS_FREE_TABLE_CNT)
2319 segment->set_index = 0;
2320
2321 segment->unused_blk_cnt++;
2322 }
2323
2324 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2325 {
2326 struct ms_info *ms_card = &chip->ms_card;
2327 struct zone_entry *segment;
2328 u16 phy_blk;
2329
2330 segment = &ms_card->segment[seg_no];
2331
2332 if (segment->unused_blk_cnt <= 0)
2333 return 0xFFFF;
2334
2335 phy_blk = segment->free_table[segment->get_index];
2336 segment->free_table[segment->get_index++] = 0xFFFF;
2337 if (segment->get_index >= MS_FREE_TABLE_CNT)
2338 segment->get_index = 0;
2339
2340 segment->unused_blk_cnt--;
2341
2342 return phy_blk;
2343 }
2344
2345 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
2346 2974, 3470, 3966, 4462, 4958,
2347 5454, 5950, 6446, 6942, 7438,
2348 7934};
2349
2350 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
2351 u16 log_off, u8 us1, u8 us2)
2352 {
2353 struct ms_info *ms_card = &chip->ms_card;
2354 struct zone_entry *segment;
2355 int seg_no;
2356 u16 tmp_blk;
2357
2358 seg_no = (int)phy_blk >> 9;
2359 segment = &ms_card->segment[seg_no];
2360 tmp_blk = segment->l2p_table[log_off];
2361
2362 if (us1 != us2) {
2363 if (us1 == 0) {
2364 if (!(chip->card_wp & MS_CARD))
2365 ms_erase_block(chip, tmp_blk);
2366
2367 ms_set_unused_block(chip, tmp_blk);
2368 segment->l2p_table[log_off] = phy_blk;
2369 } else {
2370 if (!(chip->card_wp & MS_CARD))
2371 ms_erase_block(chip, phy_blk);
2372
2373 ms_set_unused_block(chip, phy_blk);
2374 }
2375 } else {
2376 if (phy_blk < tmp_blk) {
2377 if (!(chip->card_wp & MS_CARD))
2378 ms_erase_block(chip, phy_blk);
2379
2380 ms_set_unused_block(chip, phy_blk);
2381 } else {
2382 if (!(chip->card_wp & MS_CARD))
2383 ms_erase_block(chip, tmp_blk);
2384
2385 ms_set_unused_block(chip, tmp_blk);
2386 segment->l2p_table[log_off] = phy_blk;
2387 }
2388 }
2389
2390 return STATUS_SUCCESS;
2391 }
2392
2393 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2394 {
2395 struct ms_info *ms_card = &chip->ms_card;
2396 struct zone_entry *segment;
2397 bool defect_flag;
2398 int retval, table_size, disable_cnt, i;
2399 u16 start, end, phy_blk, log_blk, tmp_blk, idx;
2400 u8 extra[MS_EXTRA_SIZE], us1, us2;
2401
2402 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, seg_no);
2403
2404 if (!ms_card->segment) {
2405 retval = ms_init_l2p_tbl(chip);
2406 if (retval != STATUS_SUCCESS) {
2407 return retval;
2408 }
2409 }
2410
2411 if (ms_card->segment[seg_no].build_flag) {
2412 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n",
2413 seg_no);
2414 return STATUS_SUCCESS;
2415 }
2416
2417 if (seg_no == 0)
2418 table_size = 494;
2419 else
2420 table_size = 496;
2421
2422 segment = &ms_card->segment[seg_no];
2423
2424 if (!segment->l2p_table) {
2425 segment->l2p_table = vmalloc(array_size(table_size, 2));
2426 if (!segment->l2p_table) {
2427 goto BUILD_FAIL;
2428 }
2429 }
2430 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2431
2432 if (!segment->free_table) {
2433 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2434 if (!segment->free_table) {
2435 goto BUILD_FAIL;
2436 }
2437 }
2438 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2439
2440 start = (u16)seg_no << 9;
2441 end = (u16)(seg_no + 1) << 9;
2442
2443 disable_cnt = segment->disable_count;
2444
2445 segment->get_index = 0;
2446 segment->set_index = 0;
2447 segment->unused_blk_cnt = 0;
2448
2449 for (phy_blk = start; phy_blk < end; phy_blk++) {
2450 if (disable_cnt) {
2451 defect_flag = false;
2452 for (i = 0; i < segment->disable_count; i++) {
2453 if (phy_blk == segment->defect_list[i]) {
2454 defect_flag = true;
2455 break;
2456 }
2457 }
2458 if (defect_flag) {
2459 disable_cnt--;
2460 continue;
2461 }
2462 }
2463
2464 retval = ms_read_extra_data(chip, phy_blk, 0,
2465 extra, MS_EXTRA_SIZE);
2466 if (retval != STATUS_SUCCESS) {
2467 dev_dbg(rtsx_dev(chip), "read extra data fail\n");
2468 ms_set_bad_block(chip, phy_blk);
2469 continue;
2470 }
2471
2472 if (seg_no == ms_card->segment_cnt - 1) {
2473 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2474 if (!(chip->card_wp & MS_CARD)) {
2475 retval = ms_erase_block(chip, phy_blk);
2476 if (retval != STATUS_SUCCESS)
2477 continue;
2478 extra[2] = 0xff;
2479 extra[3] = 0xff;
2480 }
2481 }
2482 }
2483
2484 if (!(extra[0] & BLOCK_OK))
2485 continue;
2486 if (!(extra[1] & NOT_BOOT_BLOCK))
2487 continue;
2488 if ((extra[0] & PAGE_OK) != PAGE_OK)
2489 continue;
2490
2491 log_blk = ((u16)extra[2] << 8) | extra[3];
2492
2493 if (log_blk == 0xFFFF) {
2494 if (!(chip->card_wp & MS_CARD)) {
2495 retval = ms_erase_block(chip, phy_blk);
2496 if (retval != STATUS_SUCCESS)
2497 continue;
2498 }
2499 ms_set_unused_block(chip, phy_blk);
2500 continue;
2501 }
2502
2503 if ((log_blk < ms_start_idx[seg_no]) ||
2504 (log_blk >= ms_start_idx[seg_no + 1])) {
2505 if (!(chip->card_wp & MS_CARD)) {
2506 retval = ms_erase_block(chip, phy_blk);
2507 if (retval != STATUS_SUCCESS)
2508 continue;
2509 }
2510 ms_set_unused_block(chip, phy_blk);
2511 continue;
2512 }
2513
2514 idx = log_blk - ms_start_idx[seg_no];
2515
2516 if (segment->l2p_table[idx] == 0xFFFF) {
2517 segment->l2p_table[idx] = phy_blk;
2518 continue;
2519 }
2520
2521 us1 = extra[0] & 0x10;
2522 tmp_blk = segment->l2p_table[idx];
2523 retval = ms_read_extra_data(chip, tmp_blk, 0,
2524 extra, MS_EXTRA_SIZE);
2525 if (retval != STATUS_SUCCESS)
2526 continue;
2527 us2 = extra[0] & 0x10;
2528
2529 (void)ms_arbitrate_l2p(chip, phy_blk,
2530 log_blk - ms_start_idx[seg_no], us1, us2);
2531 continue;
2532 }
2533
2534 segment->build_flag = 1;
2535
2536 dev_dbg(rtsx_dev(chip), "unused block count: %d\n",
2537 segment->unused_blk_cnt);
2538
2539 /* Logical Address Confirmation Process */
2540 if (seg_no == ms_card->segment_cnt - 1) {
2541 if (segment->unused_blk_cnt < 2)
2542 chip->card_wp |= MS_CARD;
2543 } else {
2544 if (segment->unused_blk_cnt < 1)
2545 chip->card_wp |= MS_CARD;
2546 }
2547
2548 if (chip->card_wp & MS_CARD)
2549 return STATUS_SUCCESS;
2550
2551 for (log_blk = ms_start_idx[seg_no];
2552 log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2553 idx = log_blk - ms_start_idx[seg_no];
2554 if (segment->l2p_table[idx] == 0xFFFF) {
2555 phy_blk = ms_get_unused_block(chip, seg_no);
2556 if (phy_blk == 0xFFFF) {
2557 chip->card_wp |= MS_CARD;
2558 return STATUS_SUCCESS;
2559 }
2560 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2561 if (retval != STATUS_SUCCESS) {
2562 goto BUILD_FAIL;
2563 }
2564
2565 segment->l2p_table[idx] = phy_blk;
2566 if (seg_no == ms_card->segment_cnt - 1) {
2567 if (segment->unused_blk_cnt < 2) {
2568 chip->card_wp |= MS_CARD;
2569 return STATUS_SUCCESS;
2570 }
2571 } else {
2572 if (segment->unused_blk_cnt < 1) {
2573 chip->card_wp |= MS_CARD;
2574 return STATUS_SUCCESS;
2575 }
2576 }
2577 }
2578 }
2579
2580 /* Make boot block be the first normal block */
2581 if (seg_no == 0) {
2582 for (log_blk = 0; log_blk < 494; log_blk++) {
2583 tmp_blk = segment->l2p_table[log_blk];
2584 if (tmp_blk < ms_card->boot_block) {
2585 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n");
2586
2587 if (chip->card_wp & MS_CARD)
2588 break;
2589
2590 phy_blk = ms_get_unused_block(chip, 0);
2591 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2592 log_blk, 0,
2593 ms_card->page_off + 1);
2594 if (retval != STATUS_SUCCESS) {
2595 return STATUS_FAIL;
2596 }
2597
2598 segment->l2p_table[log_blk] = phy_blk;
2599
2600 retval = ms_set_bad_block(chip, tmp_blk);
2601 if (retval != STATUS_SUCCESS) {
2602 return STATUS_FAIL;
2603 }
2604 }
2605 }
2606 }
2607
2608 return STATUS_SUCCESS;
2609
2610 BUILD_FAIL:
2611 segment->build_flag = 0;
2612 vfree(segment->l2p_table);
2613 segment->l2p_table = NULL;
2614 vfree(segment->free_table);
2615 segment->free_table = NULL;
2616
2617 return STATUS_FAIL;
2618 }
2619
2620 int reset_ms_card(struct rtsx_chip *chip)
2621 {
2622 struct ms_info *ms_card = &chip->ms_card;
2623 int seg_no = ms_card->total_block / 512 - 1;
2624 int retval;
2625
2626 memset(ms_card, 0, sizeof(struct ms_info));
2627
2628 retval = enable_card_clock(chip, MS_CARD);
2629 if (retval != STATUS_SUCCESS) {
2630 return STATUS_FAIL;
2631 }
2632
2633 retval = select_card(chip, MS_CARD);
2634 if (retval != STATUS_SUCCESS) {
2635 return STATUS_FAIL;
2636 }
2637
2638 ms_card->ms_type = 0;
2639
2640 retval = reset_ms_pro(chip);
2641 if (retval != STATUS_SUCCESS) {
2642 if (ms_card->check_ms_flow) {
2643 retval = reset_ms(chip);
2644 if (retval != STATUS_SUCCESS) {
2645 return STATUS_FAIL;
2646 }
2647 } else {
2648 return STATUS_FAIL;
2649 }
2650 }
2651
2652 retval = ms_set_init_para(chip);
2653 if (retval != STATUS_SUCCESS) {
2654 return STATUS_FAIL;
2655 }
2656
2657 if (!CHK_MSPRO(ms_card)) {
2658 /* Build table for the last segment,
2659 * to check if L2P table block exists, erasing it
2660 */
2661 retval = ms_build_l2p_tbl(chip, seg_no);
2662 if (retval != STATUS_SUCCESS) {
2663 return STATUS_FAIL;
2664 }
2665 }
2666
2667 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2668
2669 return STATUS_SUCCESS;
2670 }
2671
2672 static int mspro_set_rw_cmd(struct rtsx_chip *chip,
2673 u32 start_sec, u16 sec_cnt, u8 cmd)
2674 {
2675 int retval, i;
2676 u8 data[8];
2677
2678 data[0] = cmd;
2679 data[1] = (u8)(sec_cnt >> 8);
2680 data[2] = (u8)sec_cnt;
2681 data[3] = (u8)(start_sec >> 24);
2682 data[4] = (u8)(start_sec >> 16);
2683 data[5] = (u8)(start_sec >> 8);
2684 data[6] = (u8)start_sec;
2685 data[7] = 0;
2686
2687 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2688 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
2689 WAIT_INT, data, 8);
2690 if (retval == STATUS_SUCCESS)
2691 break;
2692 }
2693 if (i == MS_MAX_RETRY_COUNT) {
2694 return STATUS_FAIL;
2695 }
2696
2697 return STATUS_SUCCESS;
2698 }
2699
2700 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2701 {
2702 struct ms_info *ms_card = &chip->ms_card;
2703 int retval;
2704
2705 if (ms_card->seq_mode) {
2706 retval = ms_switch_clock(chip);
2707 if (retval != STATUS_SUCCESS)
2708 return;
2709
2710 ms_card->seq_mode = 0;
2711 ms_card->total_sec_cnt = 0;
2712 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2713
2714 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2715 }
2716 }
2717
2718 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2719 {
2720 struct ms_info *ms_card = &chip->ms_card;
2721 int retval;
2722
2723 if (chip->asic_code) {
2724 if (ms_card->ms_clock > 30)
2725 ms_card->ms_clock -= 20;
2726 } else {
2727 if (ms_card->ms_clock == CLK_80)
2728 ms_card->ms_clock = CLK_60;
2729 else if (ms_card->ms_clock == CLK_60)
2730 ms_card->ms_clock = CLK_40;
2731 }
2732
2733 retval = ms_switch_clock(chip);
2734 if (retval != STATUS_SUCCESS) {
2735 return STATUS_FAIL;
2736 }
2737
2738 return STATUS_SUCCESS;
2739 }
2740
2741 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2742 struct rtsx_chip *chip, u32 start_sector,
2743 u16 sector_cnt)
2744 {
2745 struct ms_info *ms_card = &chip->ms_card;
2746 bool mode_2k = false;
2747 int retval;
2748 u16 count;
2749 u8 val, trans_mode, rw_tpc, rw_cmd;
2750
2751 ms_set_err_code(chip, MS_NO_ERROR);
2752
2753 ms_card->cleanup_counter = 0;
2754
2755 if (CHK_MSHG(ms_card)) {
2756 if ((start_sector % 4) || (sector_cnt % 4)) {
2757 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2758 rw_tpc = PRO_READ_LONG_DATA;
2759 rw_cmd = PRO_READ_DATA;
2760 } else {
2761 rw_tpc = PRO_WRITE_LONG_DATA;
2762 rw_cmd = PRO_WRITE_DATA;
2763 }
2764 } else {
2765 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2766 rw_tpc = PRO_READ_QUAD_DATA;
2767 rw_cmd = PRO_READ_2K_DATA;
2768 } else {
2769 rw_tpc = PRO_WRITE_QUAD_DATA;
2770 rw_cmd = PRO_WRITE_2K_DATA;
2771 }
2772 mode_2k = true;
2773 }
2774 } else {
2775 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2776 rw_tpc = PRO_READ_LONG_DATA;
2777 rw_cmd = PRO_READ_DATA;
2778 } else {
2779 rw_tpc = PRO_WRITE_LONG_DATA;
2780 rw_cmd = PRO_WRITE_DATA;
2781 }
2782 }
2783
2784 retval = ms_switch_clock(chip);
2785 if (retval != STATUS_SUCCESS) {
2786 return STATUS_FAIL;
2787 }
2788
2789 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2790 trans_mode = MS_TM_AUTO_READ;
2791 else
2792 trans_mode = MS_TM_AUTO_WRITE;
2793
2794 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
2795 if (retval) {
2796 return retval;
2797 }
2798
2799 if (ms_card->seq_mode) {
2800 if ((ms_card->pre_dir != srb->sc_data_direction) ||
2801 ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) !=
2802 start_sector) ||
2803 (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) ||
2804 (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) ||
2805 !(val & MS_INT_BREQ) ||
2806 ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2807 ms_card->seq_mode = 0;
2808 ms_card->total_sec_cnt = 0;
2809 if (val & MS_INT_BREQ) {
2810 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2811 if (retval != STATUS_SUCCESS) {
2812 return STATUS_FAIL;
2813 }
2814
2815 rtsx_write_register(chip, RBCTL, RB_FLUSH,
2816 RB_FLUSH);
2817 }
2818 }
2819 }
2820
2821 if (!ms_card->seq_mode) {
2822 ms_card->total_sec_cnt = 0;
2823 if (sector_cnt >= SEQ_START_CRITERIA) {
2824 if ((ms_card->capacity - start_sector) > 0xFE00)
2825 count = 0xFE00;
2826 else
2827 count = (u16)(ms_card->capacity - start_sector);
2828
2829 if (count > sector_cnt) {
2830 if (mode_2k)
2831 ms_card->seq_mode = MODE_2K_SEQ;
2832 else
2833 ms_card->seq_mode = MODE_512_SEQ;
2834 }
2835 } else {
2836 count = sector_cnt;
2837 }
2838 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2839 if (retval != STATUS_SUCCESS) {
2840 ms_card->seq_mode = 0;
2841 return STATUS_FAIL;
2842 }
2843 }
2844
2845 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
2846 WAIT_INT, mode_2k, scsi_sg_count(srb),
2847 scsi_sglist(srb), scsi_bufflen(srb));
2848 if (retval != STATUS_SUCCESS) {
2849 ms_card->seq_mode = 0;
2850 rtsx_read_register(chip, MS_TRANS_CFG, &val);
2851 rtsx_clear_ms_error(chip);
2852
2853 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2854 chip->rw_need_retry = 0;
2855 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n",
2856 __func__);
2857 return STATUS_FAIL;
2858 }
2859
2860 if (val & MS_INT_BREQ)
2861 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2862
2863 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2864 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n");
2865 chip->rw_need_retry = 1;
2866 ms_auto_tune_clock(chip);
2867 }
2868
2869 return retval;
2870 }
2871
2872 if (ms_card->seq_mode) {
2873 ms_card->pre_sec_addr = start_sector;
2874 ms_card->pre_sec_cnt = sector_cnt;
2875 ms_card->pre_dir = srb->sc_data_direction;
2876 ms_card->total_sec_cnt += sector_cnt;
2877 }
2878
2879 return STATUS_SUCCESS;
2880 }
2881
2882 static int mspro_read_format_progress(struct rtsx_chip *chip,
2883 const int short_data_len)
2884 {
2885 struct ms_info *ms_card = &chip->ms_card;
2886 int retval, i;
2887 u32 total_progress, cur_progress;
2888 u8 cnt, tmp;
2889 u8 data[8];
2890
2891 dev_dbg(rtsx_dev(chip), "%s, short_data_len = %d\n", __func__,
2892 short_data_len);
2893
2894 retval = ms_switch_clock(chip);
2895 if (retval != STATUS_SUCCESS) {
2896 ms_card->format_status = FORMAT_FAIL;
2897 return STATUS_FAIL;
2898 }
2899
2900 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2901 if (retval != STATUS_SUCCESS) {
2902 ms_card->format_status = FORMAT_FAIL;
2903 return STATUS_FAIL;
2904 }
2905
2906 if (!(tmp & MS_INT_BREQ)) {
2907 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK |
2908 MS_INT_ERR)) == MS_INT_CED) {
2909 ms_card->format_status = FORMAT_SUCCESS;
2910 return STATUS_SUCCESS;
2911 }
2912 ms_card->format_status = FORMAT_FAIL;
2913 return STATUS_FAIL;
2914 }
2915
2916 if (short_data_len >= 256)
2917 cnt = 0;
2918 else
2919 cnt = (u8)short_data_len;
2920
2921 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
2922 MS_NO_CHECK_INT);
2923 if (retval != STATUS_SUCCESS) {
2924 ms_card->format_status = FORMAT_FAIL;
2925 return STATUS_FAIL;
2926 }
2927
2928 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
2929 data, 8);
2930 if (retval != STATUS_SUCCESS) {
2931 ms_card->format_status = FORMAT_FAIL;
2932 return STATUS_FAIL;
2933 }
2934
2935 total_progress = (data[0] << 24) | (data[1] << 16) |
2936 (data[2] << 8) | data[3];
2937 cur_progress = (data[4] << 24) | (data[5] << 16) |
2938 (data[6] << 8) | data[7];
2939
2940 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n",
2941 total_progress, cur_progress);
2942
2943 if (total_progress == 0) {
2944 ms_card->progress = 0;
2945 } else {
2946 u64 ulltmp = (u64)cur_progress * (u64)65535;
2947
2948 do_div(ulltmp, total_progress);
2949 ms_card->progress = (u16)ulltmp;
2950 }
2951 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress);
2952
2953 for (i = 0; i < 5000; i++) {
2954 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2955 if (retval != STATUS_SUCCESS) {
2956 ms_card->format_status = FORMAT_FAIL;
2957 return STATUS_FAIL;
2958 }
2959 if (tmp & (MS_INT_CED | MS_INT_CMDNK |
2960 MS_INT_BREQ | MS_INT_ERR))
2961 break;
2962
2963 wait_timeout(1);
2964 }
2965
2966 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
2967 if (retval != STATUS_SUCCESS) {
2968 ms_card->format_status = FORMAT_FAIL;
2969 return STATUS_FAIL;
2970 }
2971
2972 if (i == 5000) {
2973 ms_card->format_status = FORMAT_FAIL;
2974 return STATUS_FAIL;
2975 }
2976
2977 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2978 ms_card->format_status = FORMAT_FAIL;
2979 return STATUS_FAIL;
2980 }
2981
2982 if (tmp & MS_INT_CED) {
2983 ms_card->format_status = FORMAT_SUCCESS;
2984 ms_card->pro_under_formatting = 0;
2985 } else if (tmp & MS_INT_BREQ) {
2986 ms_card->format_status = FORMAT_IN_PROGRESS;
2987 } else {
2988 ms_card->format_status = FORMAT_FAIL;
2989 ms_card->pro_under_formatting = 0;
2990 return STATUS_FAIL;
2991 }
2992
2993 return STATUS_SUCCESS;
2994 }
2995
2996 void mspro_polling_format_status(struct rtsx_chip *chip)
2997 {
2998 struct ms_info *ms_card = &chip->ms_card;
2999 int i;
3000
3001 if (ms_card->pro_under_formatting &&
3002 (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
3003 rtsx_set_stat(chip, RTSX_STAT_RUN);
3004
3005 for (i = 0; i < 65535; i++) {
3006 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
3007 if (ms_card->format_status != FORMAT_IN_PROGRESS)
3008 break;
3009 }
3010 }
3011 }
3012
3013 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3014 int short_data_len, bool quick_format)
3015 {
3016 struct ms_info *ms_card = &chip->ms_card;
3017 int retval, i;
3018 u8 buf[8], tmp;
3019 u16 para;
3020
3021 retval = ms_switch_clock(chip);
3022 if (retval != STATUS_SUCCESS) {
3023 return STATUS_FAIL;
3024 }
3025
3026 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
3027 if (retval != STATUS_SUCCESS) {
3028 return STATUS_FAIL;
3029 }
3030
3031 memset(buf, 0, 2);
3032 switch (short_data_len) {
3033 case 32:
3034 buf[0] = 0;
3035 break;
3036 case 64:
3037 buf[0] = 1;
3038 break;
3039 case 128:
3040 buf[0] = 2;
3041 break;
3042 case 256:
3043 default:
3044 buf[0] = 3;
3045 break;
3046 }
3047
3048 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3049 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
3050 NO_WAIT_INT, buf, 2);
3051 if (retval == STATUS_SUCCESS)
3052 break;
3053 }
3054 if (i == MS_MAX_RETRY_COUNT) {
3055 return STATUS_FAIL;
3056 }
3057
3058 if (quick_format)
3059 para = 0x0000;
3060 else
3061 para = 0x0001;
3062
3063 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
3064 if (retval != STATUS_SUCCESS) {
3065 return STATUS_FAIL;
3066 }
3067
3068 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3069 if (retval) {
3070 return retval;
3071 }
3072
3073 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
3074 return STATUS_FAIL;
3075 }
3076
3077 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
3078 ms_card->pro_under_formatting = 1;
3079 ms_card->progress = 0;
3080 ms_card->format_status = FORMAT_IN_PROGRESS;
3081 return STATUS_SUCCESS;
3082 }
3083
3084 if (tmp & MS_INT_CED) {
3085 ms_card->pro_under_formatting = 0;
3086 ms_card->progress = 0;
3087 ms_card->format_status = FORMAT_SUCCESS;
3088 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
3089 return STATUS_SUCCESS;
3090 }
3091
3092 return STATUS_FAIL;
3093 }
3094
3095 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
3096 u16 log_blk, u8 start_page, u8 end_page,
3097 u8 *buf, unsigned int *index,
3098 unsigned int *offset)
3099 {
3100 struct ms_info *ms_card = &chip->ms_card;
3101 int retval, i;
3102 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
3103 u8 *ptr;
3104
3105 retval = ms_read_extra_data(chip, phy_blk, start_page,
3106 extra, MS_EXTRA_SIZE);
3107 if (retval == STATUS_SUCCESS) {
3108 if ((extra[1] & 0x30) != 0x30) {
3109 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3110 return STATUS_FAIL;
3111 }
3112 }
3113
3114 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3115 SystemParm, 6);
3116 if (retval != STATUS_SUCCESS) {
3117 return STATUS_FAIL;
3118 }
3119
3120 if (CHK_MS4BIT(ms_card))
3121 data[0] = 0x88;
3122 else
3123 data[0] = 0x80;
3124
3125 data[1] = 0;
3126 data[2] = (u8)(phy_blk >> 8);
3127 data[3] = (u8)phy_blk;
3128 data[4] = 0;
3129 data[5] = start_page;
3130
3131 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3132 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
3133 data, 6);
3134 if (retval == STATUS_SUCCESS)
3135 break;
3136 }
3137 if (i == MS_MAX_RETRY_COUNT) {
3138 return STATUS_FAIL;
3139 }
3140
3141 ms_set_err_code(chip, MS_NO_ERROR);
3142
3143 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
3144 if (retval != STATUS_SUCCESS) {
3145 return STATUS_FAIL;
3146 }
3147
3148 ptr = buf;
3149
3150 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3151 ms_set_err_code(chip, MS_NO_ERROR);
3152
3153 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3154 ms_set_err_code(chip, MS_NO_CARD);
3155 return STATUS_FAIL;
3156 }
3157
3158 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3159 if (retval != STATUS_SUCCESS) {
3160 return STATUS_FAIL;
3161 }
3162
3163 if (val & INT_REG_CMDNK) {
3164 ms_set_err_code(chip, MS_CMD_NK);
3165 return STATUS_FAIL;
3166 }
3167 if (val & INT_REG_ERR) {
3168 if (val & INT_REG_BREQ) {
3169 retval = ms_read_status_reg(chip);
3170 if (retval != STATUS_SUCCESS) {
3171 if (!(chip->card_wp & MS_CARD)) {
3172 reset_ms(chip);
3173 ms_set_page_status
3174 (log_blk, setPS_NG,
3175 extra,
3176 MS_EXTRA_SIZE);
3177 ms_write_extra_data
3178 (chip, phy_blk,
3179 page_addr, extra,
3180 MS_EXTRA_SIZE);
3181 }
3182 ms_set_err_code(chip,
3183 MS_FLASH_READ_ERROR);
3184 return STATUS_FAIL;
3185 }
3186 } else {
3187 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3188 return STATUS_FAIL;
3189 }
3190 } else {
3191 if (!(val & INT_REG_BREQ)) {
3192 ms_set_err_code(chip, MS_BREQ_ERROR);
3193 return STATUS_FAIL;
3194 }
3195 }
3196
3197 if (page_addr == (end_page - 1)) {
3198 if (!(val & INT_REG_CED)) {
3199 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3200 if (retval != STATUS_SUCCESS) {
3201 return STATUS_FAIL;
3202 }
3203 }
3204
3205 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
3206 &val, 1);
3207 if (retval != STATUS_SUCCESS) {
3208 return STATUS_FAIL;
3209 }
3210
3211 if (!(val & INT_REG_CED)) {
3212 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3213 return STATUS_FAIL;
3214 }
3215
3216 trans_cfg = NO_WAIT_INT;
3217 } else {
3218 trans_cfg = WAIT_INT;
3219 }
3220
3221 rtsx_init_cmd(chip);
3222
3223 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3224 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3225 0xFF, trans_cfg);
3226 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3227 0x01, RING_BUFFER);
3228
3229 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3230
3231 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3232 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3233 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3234 MS_TRANSFER_END, MS_TRANSFER_END);
3235
3236 rtsx_send_cmd_no_wait(chip);
3237
3238 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512,
3239 scsi_sg_count(chip->srb),
3240 index, offset,
3241 DMA_FROM_DEVICE,
3242 chip->ms_timeout);
3243 if (retval < 0) {
3244 if (retval == -ETIMEDOUT) {
3245 ms_set_err_code(chip, MS_TO_ERROR);
3246 rtsx_clear_ms_error(chip);
3247 return STATUS_TIMEDOUT;
3248 }
3249
3250 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3251 if (retval != STATUS_SUCCESS) {
3252 ms_set_err_code(chip, MS_TO_ERROR);
3253 rtsx_clear_ms_error(chip);
3254 return STATUS_TIMEDOUT;
3255 }
3256 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3257 ms_set_err_code(chip, MS_CRC16_ERROR);
3258 rtsx_clear_ms_error(chip);
3259 return STATUS_FAIL;
3260 }
3261 }
3262
3263 if (scsi_sg_count(chip->srb) == 0)
3264 ptr += 512;
3265 }
3266
3267 return STATUS_SUCCESS;
3268 }
3269
3270 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
3271 u16 new_blk, u16 log_blk, u8 start_page,
3272 u8 end_page, u8 *buf, unsigned int *index,
3273 unsigned int *offset)
3274 {
3275 struct ms_info *ms_card = &chip->ms_card;
3276 int retval, i;
3277 u8 page_addr, val, data[16];
3278 u8 *ptr;
3279
3280 if (!start_page) {
3281 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3282 SystemParm, 7);
3283 if (retval != STATUS_SUCCESS) {
3284 return STATUS_FAIL;
3285 }
3286
3287 if (CHK_MS4BIT(ms_card))
3288 data[0] = 0x88;
3289 else
3290 data[0] = 0x80;
3291
3292 data[1] = 0;
3293 data[2] = (u8)(old_blk >> 8);
3294 data[3] = (u8)old_blk;
3295 data[4] = 0x80;
3296 data[5] = 0;
3297 data[6] = 0xEF;
3298 data[7] = 0xFF;
3299
3300 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
3301 data, 8);
3302 if (retval != STATUS_SUCCESS) {
3303 return STATUS_FAIL;
3304 }
3305
3306 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3307 if (retval != STATUS_SUCCESS) {
3308 return STATUS_FAIL;
3309 }
3310
3311 ms_set_err_code(chip, MS_NO_ERROR);
3312 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3313 NO_WAIT_INT);
3314 if (retval != STATUS_SUCCESS) {
3315 return STATUS_FAIL;
3316 }
3317 }
3318
3319 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3320 SystemParm, (6 + MS_EXTRA_SIZE));
3321 if (retval != STATUS_SUCCESS) {
3322 return STATUS_FAIL;
3323 }
3324
3325 ms_set_err_code(chip, MS_NO_ERROR);
3326
3327 if (CHK_MS4BIT(ms_card))
3328 data[0] = 0x88;
3329 else
3330 data[0] = 0x80;
3331
3332 data[1] = 0;
3333 data[2] = (u8)(new_blk >> 8);
3334 data[3] = (u8)new_blk;
3335 if ((end_page - start_page) == 1)
3336 data[4] = 0x20;
3337 else
3338 data[4] = 0;
3339
3340 data[5] = start_page;
3341 data[6] = 0xF8;
3342 data[7] = 0xFF;
3343 data[8] = (u8)(log_blk >> 8);
3344 data[9] = (u8)log_blk;
3345
3346 for (i = 0x0A; i < 0x10; i++)
3347 data[i] = 0xFF;
3348
3349 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3350 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3351 NO_WAIT_INT, data, 16);
3352 if (retval == STATUS_SUCCESS)
3353 break;
3354 }
3355 if (i == MS_MAX_RETRY_COUNT) {
3356 return STATUS_FAIL;
3357 }
3358
3359 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3360 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3361 if (retval == STATUS_SUCCESS)
3362 break;
3363 }
3364 if (i == MS_MAX_RETRY_COUNT) {
3365 return STATUS_FAIL;
3366 }
3367
3368 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3369 if (retval != STATUS_SUCCESS) {
3370 return STATUS_FAIL;
3371 }
3372
3373 ptr = buf;
3374 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3375 ms_set_err_code(chip, MS_NO_ERROR);
3376
3377 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3378 ms_set_err_code(chip, MS_NO_CARD);
3379 return STATUS_FAIL;
3380 }
3381
3382 if (val & INT_REG_CMDNK) {
3383 ms_set_err_code(chip, MS_CMD_NK);
3384 return STATUS_FAIL;
3385 }
3386 if (val & INT_REG_ERR) {
3387 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3388 return STATUS_FAIL;
3389 }
3390 if (!(val & INT_REG_BREQ)) {
3391 ms_set_err_code(chip, MS_BREQ_ERROR);
3392 return STATUS_FAIL;
3393 }
3394
3395 udelay(30);
3396
3397 rtsx_init_cmd(chip);
3398
3399 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
3400 0xFF, WRITE_PAGE_DATA);
3401 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3402 0xFF, WAIT_INT);
3403 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3404 0x01, RING_BUFFER);
3405
3406 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3407
3408 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3409 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3410 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3411 MS_TRANSFER_END, MS_TRANSFER_END);
3412
3413 rtsx_send_cmd_no_wait(chip);
3414
3415 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512,
3416 scsi_sg_count(chip->srb),
3417 index, offset,
3418 DMA_TO_DEVICE,
3419 chip->ms_timeout);
3420 if (retval < 0) {
3421 ms_set_err_code(chip, MS_TO_ERROR);
3422 rtsx_clear_ms_error(chip);
3423
3424 if (retval == -ETIMEDOUT) {
3425 return STATUS_TIMEDOUT;
3426 }
3427 return STATUS_FAIL;
3428 }
3429
3430 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3431 if (retval != STATUS_SUCCESS) {
3432 return STATUS_FAIL;
3433 }
3434
3435 if ((end_page - start_page) == 1) {
3436 if (!(val & INT_REG_CED)) {
3437 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3438 return STATUS_FAIL;
3439 }
3440 } else {
3441 if (page_addr == (end_page - 1)) {
3442 if (!(val & INT_REG_CED)) {
3443 retval = ms_send_cmd(chip, BLOCK_END,
3444 WAIT_INT);
3445 if (retval != STATUS_SUCCESS) {
3446 return STATUS_FAIL;
3447 }
3448 }
3449
3450 retval = ms_read_bytes(chip, GET_INT, 1,
3451 NO_WAIT_INT, &val, 1);
3452 if (retval != STATUS_SUCCESS) {
3453 return STATUS_FAIL;
3454 }
3455 }
3456
3457 if ((page_addr == (end_page - 1)) ||
3458 (page_addr == ms_card->page_off)) {
3459 if (!(val & INT_REG_CED)) {
3460 ms_set_err_code(chip,
3461 MS_FLASH_WRITE_ERROR);
3462 return STATUS_FAIL;
3463 }
3464 }
3465 }
3466
3467 if (scsi_sg_count(chip->srb) == 0)
3468 ptr += 512;
3469 }
3470
3471 return STATUS_SUCCESS;
3472 }
3473
3474 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3475 u16 log_blk, u8 page_off)
3476 {
3477 struct ms_info *ms_card = &chip->ms_card;
3478 int retval, seg_no;
3479
3480 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3481 page_off, ms_card->page_off + 1);
3482 if (retval != STATUS_SUCCESS) {
3483 return STATUS_FAIL;
3484 }
3485
3486 seg_no = old_blk >> 9;
3487
3488 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3489 MS_CLR_BAD_BLOCK_FLG(ms_card);
3490 ms_set_bad_block(chip, old_blk);
3491 } else {
3492 retval = ms_erase_block(chip, old_blk);
3493 if (retval == STATUS_SUCCESS)
3494 ms_set_unused_block(chip, old_blk);
3495 }
3496
3497 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3498
3499 return STATUS_SUCCESS;
3500 }
3501
3502 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3503 u16 log_blk, u8 start_page)
3504 {
3505 int retval;
3506
3507 if (start_page) {
3508 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3509 0, start_page);
3510 if (retval != STATUS_SUCCESS) {
3511 return STATUS_FAIL;
3512 }
3513 }
3514
3515 return STATUS_SUCCESS;
3516 }
3517
3518 #ifdef MS_DELAY_WRITE
3519 int ms_delay_write(struct rtsx_chip *chip)
3520 {
3521 struct ms_info *ms_card = &chip->ms_card;
3522 struct ms_delay_write_tag *delay_write = &ms_card->delay_write;
3523 int retval;
3524
3525 if (delay_write->delay_write_flag) {
3526 retval = ms_set_init_para(chip);
3527 if (retval != STATUS_SUCCESS) {
3528 return STATUS_FAIL;
3529 }
3530
3531 delay_write->delay_write_flag = 0;
3532 retval = ms_finish_write(chip,
3533 delay_write->old_phyblock,
3534 delay_write->new_phyblock,
3535 delay_write->logblock,
3536 delay_write->pageoff);
3537 if (retval != STATUS_SUCCESS) {
3538 return STATUS_FAIL;
3539 }
3540 }
3541
3542 return STATUS_SUCCESS;
3543 }
3544 #endif
3545
3546 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3547 {
3548 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3549 set_sense_type(chip, SCSI_LUN(srb),
3550 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3551 else
3552 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3553 }
3554
3555 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3556 u32 start_sector, u16 sector_cnt)
3557 {
3558 struct ms_info *ms_card = &chip->ms_card;
3559 unsigned int lun = SCSI_LUN(srb);
3560 int retval, seg_no;
3561 unsigned int index = 0, offset = 0;
3562 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3563 u8 start_page, end_page = 0, page_cnt;
3564 u8 *ptr;
3565 #ifdef MS_DELAY_WRITE
3566 struct ms_delay_write_tag *delay_write = &ms_card->delay_write;
3567 #endif
3568
3569 ms_set_err_code(chip, MS_NO_ERROR);
3570
3571 ms_card->cleanup_counter = 0;
3572
3573 ptr = (u8 *)scsi_sglist(srb);
3574
3575 retval = ms_switch_clock(chip);
3576 if (retval != STATUS_SUCCESS) {
3577 ms_rw_fail(srb, chip);
3578 return STATUS_FAIL;
3579 }
3580
3581 log_blk = (u16)(start_sector >> ms_card->block_shift);
3582 start_page = (u8)(start_sector & ms_card->page_off);
3583
3584 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3585 if (log_blk < ms_start_idx[seg_no + 1])
3586 break;
3587 }
3588
3589 if (ms_card->segment[seg_no].build_flag == 0) {
3590 retval = ms_build_l2p_tbl(chip, seg_no);
3591 if (retval != STATUS_SUCCESS) {
3592 chip->card_fail |= MS_CARD;
3593 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3594 return STATUS_FAIL;
3595 }
3596 }
3597
3598 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3599 #ifdef MS_DELAY_WRITE
3600 if (delay_write->delay_write_flag &&
3601 (delay_write->logblock == log_blk) &&
3602 (start_page > delay_write->pageoff)) {
3603 delay_write->delay_write_flag = 0;
3604 retval = ms_copy_page(chip,
3605 delay_write->old_phyblock,
3606 delay_write->new_phyblock,
3607 log_blk,
3608 delay_write->pageoff, start_page);
3609 if (retval != STATUS_SUCCESS) {
3610 set_sense_type(chip, lun,
3611 SENSE_TYPE_MEDIA_WRITE_ERR);
3612 return STATUS_FAIL;
3613 }
3614 old_blk = delay_write->old_phyblock;
3615 new_blk = delay_write->new_phyblock;
3616 } else if (delay_write->delay_write_flag &&
3617 (delay_write->logblock == log_blk) &&
3618 (start_page == delay_write->pageoff)) {
3619 delay_write->delay_write_flag = 0;
3620 old_blk = delay_write->old_phyblock;
3621 new_blk = delay_write->new_phyblock;
3622 } else {
3623 retval = ms_delay_write(chip);
3624 if (retval != STATUS_SUCCESS) {
3625 set_sense_type(chip, lun,
3626 SENSE_TYPE_MEDIA_WRITE_ERR);
3627 return STATUS_FAIL;
3628 }
3629 #endif
3630 old_blk = ms_get_l2p_tbl
3631 (chip, seg_no,
3632 log_blk - ms_start_idx[seg_no]);
3633 new_blk = ms_get_unused_block(chip, seg_no);
3634 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3635 set_sense_type(chip, lun,
3636 SENSE_TYPE_MEDIA_WRITE_ERR);
3637 return STATUS_FAIL;
3638 }
3639
3640 retval = ms_prepare_write(chip, old_blk, new_blk,
3641 log_blk, start_page);
3642 if (retval != STATUS_SUCCESS) {
3643 if (detect_card_cd(chip, MS_CARD) !=
3644 STATUS_SUCCESS) {
3645 set_sense_type
3646 (chip, lun,
3647 SENSE_TYPE_MEDIA_NOT_PRESENT);
3648 return STATUS_FAIL;
3649 }
3650 set_sense_type(chip, lun,
3651 SENSE_TYPE_MEDIA_WRITE_ERR);
3652 return STATUS_FAIL;
3653 }
3654 #ifdef MS_DELAY_WRITE
3655 }
3656 #endif
3657 } else {
3658 #ifdef MS_DELAY_WRITE
3659 retval = ms_delay_write(chip);
3660 if (retval != STATUS_SUCCESS) {
3661 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3662 set_sense_type(chip, lun,
3663 SENSE_TYPE_MEDIA_NOT_PRESENT);
3664 return STATUS_FAIL;
3665 }
3666 set_sense_type(chip, lun,
3667 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3668 return STATUS_FAIL;
3669 }
3670 #endif
3671 old_blk = ms_get_l2p_tbl(chip, seg_no,
3672 log_blk - ms_start_idx[seg_no]);
3673 if (old_blk == 0xFFFF) {
3674 set_sense_type(chip, lun,
3675 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3676 return STATUS_FAIL;
3677 }
3678 }
3679
3680 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3681 seg_no, old_blk, new_blk);
3682
3683 while (total_sec_cnt) {
3684 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3685 end_page = ms_card->page_off + 1;
3686 else
3687 end_page = start_page + (u8)total_sec_cnt;
3688
3689 page_cnt = end_page - start_page;
3690
3691 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n",
3692 start_page, end_page, page_cnt);
3693
3694 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3695 retval = ms_read_multiple_pages(chip,
3696 old_blk, log_blk,
3697 start_page, end_page,
3698 ptr, &index, &offset);
3699 } else {
3700 retval = ms_write_multiple_pages(chip, old_blk, new_blk,
3701 log_blk, start_page,
3702 end_page, ptr, &index,
3703 &offset);
3704 }
3705
3706 if (retval != STATUS_SUCCESS) {
3707 toggle_gpio(chip, 1);
3708 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3709 set_sense_type(chip, lun,
3710 SENSE_TYPE_MEDIA_NOT_PRESENT);
3711 return STATUS_FAIL;
3712 }
3713 ms_rw_fail(srb, chip);
3714 return STATUS_FAIL;
3715 }
3716
3717 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3718 if (end_page == (ms_card->page_off + 1)) {
3719 retval = ms_erase_block(chip, old_blk);
3720 if (retval == STATUS_SUCCESS)
3721 ms_set_unused_block(chip, old_blk);
3722
3723 ms_set_l2p_tbl(chip, seg_no,
3724 log_blk - ms_start_idx[seg_no],
3725 new_blk);
3726 }
3727 }
3728
3729 total_sec_cnt -= page_cnt;
3730 if (scsi_sg_count(srb) == 0)
3731 ptr += page_cnt * 512;
3732
3733 if (total_sec_cnt == 0)
3734 break;
3735
3736 log_blk++;
3737
3738 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
3739 seg_no++) {
3740 if (log_blk < ms_start_idx[seg_no + 1])
3741 break;
3742 }
3743
3744 if (ms_card->segment[seg_no].build_flag == 0) {
3745 retval = ms_build_l2p_tbl(chip, seg_no);
3746 if (retval != STATUS_SUCCESS) {
3747 chip->card_fail |= MS_CARD;
3748 set_sense_type(chip, lun,
3749 SENSE_TYPE_MEDIA_NOT_PRESENT);
3750 return STATUS_FAIL;
3751 }
3752 }
3753
3754 old_blk = ms_get_l2p_tbl(chip, seg_no,
3755 log_blk - ms_start_idx[seg_no]);
3756 if (old_blk == 0xFFFF) {
3757 ms_rw_fail(srb, chip);
3758 return STATUS_FAIL;
3759 }
3760
3761 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3762 new_blk = ms_get_unused_block(chip, seg_no);
3763 if (new_blk == 0xFFFF) {
3764 ms_rw_fail(srb, chip);
3765 return STATUS_FAIL;
3766 }
3767 }
3768
3769 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3770 seg_no, old_blk, new_blk);
3771
3772 start_page = 0;
3773 }
3774
3775 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3776 if (end_page < (ms_card->page_off + 1)) {
3777 #ifdef MS_DELAY_WRITE
3778 delay_write->delay_write_flag = 1;
3779 delay_write->old_phyblock = old_blk;
3780 delay_write->new_phyblock = new_blk;
3781 delay_write->logblock = log_blk;
3782 delay_write->pageoff = end_page;
3783 #else
3784 retval = ms_finish_write(chip, old_blk, new_blk,
3785 log_blk, end_page);
3786 if (retval != STATUS_SUCCESS) {
3787 if (detect_card_cd(chip, MS_CARD) !=
3788 STATUS_SUCCESS) {
3789 set_sense_type
3790 (chip, lun,
3791 SENSE_TYPE_MEDIA_NOT_PRESENT);
3792 return STATUS_FAIL;
3793 }
3794
3795 ms_rw_fail(srb, chip);
3796 return STATUS_FAIL;
3797 }
3798 #endif
3799 }
3800 }
3801
3802 scsi_set_resid(srb, 0);
3803
3804 return STATUS_SUCCESS;
3805 }
3806
3807 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3808 u32 start_sector, u16 sector_cnt)
3809 {
3810 struct ms_info *ms_card = &chip->ms_card;
3811 int retval;
3812
3813 if (CHK_MSPRO(ms_card))
3814 retval = mspro_rw_multi_sector(srb, chip, start_sector,
3815 sector_cnt);
3816 else
3817 retval = ms_rw_multi_sector(srb, chip, start_sector,
3818 sector_cnt);
3819
3820 return retval;
3821 }
3822
3823 void ms_free_l2p_tbl(struct rtsx_chip *chip)
3824 {
3825 struct ms_info *ms_card = &chip->ms_card;
3826 int i = 0;
3827
3828 if (ms_card->segment) {
3829 for (i = 0; i < ms_card->segment_cnt; i++) {
3830 vfree(ms_card->segment[i].l2p_table);
3831 ms_card->segment[i].l2p_table = NULL;
3832 vfree(ms_card->segment[i].free_table);
3833 ms_card->segment[i].free_table = NULL;
3834 }
3835 vfree(ms_card->segment);
3836 ms_card->segment = NULL;
3837 }
3838 }
3839
3840 #ifdef SUPPORT_MAGIC_GATE
3841
3842 #ifdef READ_BYTES_WAIT_INT
3843 static int ms_poll_int(struct rtsx_chip *chip)
3844 {
3845 int retval;
3846 u8 val;
3847
3848 rtsx_init_cmd(chip);
3849
3850 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
3851
3852 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
3853 if (retval != STATUS_SUCCESS) {
3854 return STATUS_FAIL;
3855 }
3856
3857 val = *rtsx_get_cmd_data(chip);
3858 if (val & MS_INT_ERR) {
3859 return STATUS_FAIL;
3860 }
3861
3862 return STATUS_SUCCESS;
3863 }
3864 #endif
3865
3866 #ifdef MS_SAMPLE_INT_ERR
3867 static int check_ms_err(struct rtsx_chip *chip)
3868 {
3869 int retval;
3870 u8 val;
3871
3872 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3873 if (retval != STATUS_SUCCESS)
3874 return 1;
3875 if (val & MS_TRANSFER_ERR)
3876 return 1;
3877
3878 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3879 if (retval != STATUS_SUCCESS)
3880 return 1;
3881
3882 if (val & (MS_INT_ERR | MS_INT_CMDNK))
3883 return 1;
3884
3885 return 0;
3886 }
3887 #else
3888 static int check_ms_err(struct rtsx_chip *chip)
3889 {
3890 int retval;
3891 u8 val;
3892
3893 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3894 if (retval != STATUS_SUCCESS)
3895 return 1;
3896 if (val & MS_TRANSFER_ERR)
3897 return 1;
3898
3899 return 0;
3900 }
3901 #endif
3902
3903 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
3904 {
3905 int retval, i;
3906 u8 data[8];
3907
3908 data[0] = cmd;
3909 data[1] = 0;
3910 data[2] = 0;
3911 data[3] = 0;
3912 data[4] = 0;
3913 data[5] = 0;
3914 data[6] = entry_num;
3915 data[7] = 0;
3916
3917 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3918 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
3919 data, 8);
3920 if (retval == STATUS_SUCCESS)
3921 break;
3922 }
3923 if (i == MS_MAX_RETRY_COUNT) {
3924 return STATUS_FAIL;
3925 }
3926
3927 if (check_ms_err(chip)) {
3928 rtsx_clear_ms_error(chip);
3929 return STATUS_FAIL;
3930 }
3931
3932 return STATUS_SUCCESS;
3933 }
3934
3935 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
3936 u8 mg_entry_num)
3937 {
3938 int retval;
3939 u8 buf[6];
3940
3941 if (type == 0)
3942 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
3943 else
3944 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
3945
3946 if (retval != STATUS_SUCCESS) {
3947 return STATUS_FAIL;
3948 }
3949
3950 buf[0] = 0;
3951 buf[1] = 0;
3952 if (type == 1) {
3953 buf[2] = 0;
3954 buf[3] = 0;
3955 buf[4] = 0;
3956 buf[5] = mg_entry_num;
3957 }
3958 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
3959 NO_WAIT_INT, buf, 6);
3960 if (retval != STATUS_SUCCESS) {
3961 return STATUS_FAIL;
3962 }
3963
3964 return STATUS_SUCCESS;
3965 }
3966
3967 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3968 {
3969 int retval;
3970 int i;
3971 unsigned int lun = SCSI_LUN(srb);
3972 u8 buf1[32], buf2[12];
3973
3974 if (scsi_bufflen(srb) < 12) {
3975 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3976 return STATUS_FAIL;
3977 }
3978
3979 ms_cleanup_work(chip);
3980
3981 retval = ms_switch_clock(chip);
3982 if (retval != STATUS_SUCCESS) {
3983 return STATUS_FAIL;
3984 }
3985
3986 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
3987 if (retval != STATUS_SUCCESS) {
3988 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3989 return STATUS_FAIL;
3990 }
3991
3992 memset(buf1, 0, 32);
3993 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
3994 for (i = 0; i < 8; i++)
3995 buf1[8 + i] = buf2[4 + i];
3996
3997 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
3998 buf1, 32);
3999 if (retval != STATUS_SUCCESS) {
4000 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4001 return STATUS_FAIL;
4002 }
4003 if (check_ms_err(chip)) {
4004 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4005 rtsx_clear_ms_error(chip);
4006 return STATUS_FAIL;
4007 }
4008
4009 return STATUS_SUCCESS;
4010 }
4011
4012 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4013 {
4014 int retval = STATUS_FAIL;
4015 int bufflen;
4016 unsigned int lun = SCSI_LUN(srb);
4017 u8 *buf = NULL;
4018
4019 ms_cleanup_work(chip);
4020
4021 retval = ms_switch_clock(chip);
4022 if (retval != STATUS_SUCCESS) {
4023 return STATUS_FAIL;
4024 }
4025
4026 buf = kmalloc(1540, GFP_KERNEL);
4027 if (!buf) {
4028 return STATUS_ERROR;
4029 }
4030
4031 buf[0] = 0x04;
4032 buf[1] = 0x1A;
4033 buf[2] = 0x00;
4034 buf[3] = 0x00;
4035
4036 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
4037 if (retval != STATUS_SUCCESS) {
4038 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4039 goto free_buffer;
4040 }
4041
4042 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4043 3, WAIT_INT, 0, 0, buf + 4, 1536);
4044 if (retval != STATUS_SUCCESS) {
4045 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4046 rtsx_clear_ms_error(chip);
4047 goto free_buffer;
4048 }
4049 if (check_ms_err(chip)) {
4050 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4051 rtsx_clear_ms_error(chip);
4052 retval = STATUS_FAIL;
4053 goto free_buffer;
4054 }
4055
4056 bufflen = min_t(int, 1052, scsi_bufflen(srb));
4057 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4058
4059 free_buffer:
4060 kfree(buf);
4061 return retval;
4062 }
4063
4064 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4065 {
4066 struct ms_info *ms_card = &chip->ms_card;
4067 int retval;
4068 int bufflen;
4069 int i;
4070 unsigned int lun = SCSI_LUN(srb);
4071 u8 buf[32];
4072
4073 ms_cleanup_work(chip);
4074
4075 retval = ms_switch_clock(chip);
4076 if (retval != STATUS_SUCCESS) {
4077 return STATUS_FAIL;
4078 }
4079
4080 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
4081 if (retval != STATUS_SUCCESS) {
4082 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4083 return STATUS_FAIL;
4084 }
4085
4086 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4087 buf, 32);
4088 if (retval != STATUS_SUCCESS) {
4089 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4090 return STATUS_FAIL;
4091 }
4092 if (check_ms_err(chip)) {
4093 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4094 rtsx_clear_ms_error(chip);
4095 return STATUS_FAIL;
4096 }
4097
4098 memcpy(ms_card->magic_gate_id, buf, 16);
4099
4100 #ifdef READ_BYTES_WAIT_INT
4101 retval = ms_poll_int(chip);
4102 if (retval != STATUS_SUCCESS) {
4103 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4104 return STATUS_FAIL;
4105 }
4106 #endif
4107
4108 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
4109 if (retval != STATUS_SUCCESS) {
4110 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4111 return STATUS_FAIL;
4112 }
4113
4114 bufflen = min_t(int, 12, scsi_bufflen(srb));
4115 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4116
4117 for (i = 0; i < 8; i++)
4118 buf[i] = buf[4 + i];
4119
4120 for (i = 0; i < 24; i++)
4121 buf[8 + i] = 0;
4122
4123 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
4124 32, WAIT_INT, buf, 32);
4125 if (retval != STATUS_SUCCESS) {
4126 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4127 return STATUS_FAIL;
4128 }
4129 if (check_ms_err(chip)) {
4130 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4131 rtsx_clear_ms_error(chip);
4132 return STATUS_FAIL;
4133 }
4134
4135 ms_card->mg_auth = 0;
4136
4137 return STATUS_SUCCESS;
4138 }
4139
4140 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4141 {
4142 struct ms_info *ms_card = &chip->ms_card;
4143 int retval;
4144 int bufflen;
4145 unsigned int lun = SCSI_LUN(srb);
4146 u8 buf1[32], buf2[36];
4147
4148 ms_cleanup_work(chip);
4149
4150 retval = ms_switch_clock(chip);
4151 if (retval != STATUS_SUCCESS) {
4152 return STATUS_FAIL;
4153 }
4154
4155 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
4156 if (retval != STATUS_SUCCESS) {
4157 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4158 return STATUS_FAIL;
4159 }
4160
4161 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4162 buf1, 32);
4163 if (retval != STATUS_SUCCESS) {
4164 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4165 return STATUS_FAIL;
4166 }
4167 if (check_ms_err(chip)) {
4168 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4169 rtsx_clear_ms_error(chip);
4170 return STATUS_FAIL;
4171 }
4172
4173 buf2[0] = 0x00;
4174 buf2[1] = 0x22;
4175 buf2[2] = 0x00;
4176 buf2[3] = 0x00;
4177
4178 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
4179 memcpy(buf2 + 20, buf1, 16);
4180
4181 bufflen = min_t(int, 36, scsi_bufflen(srb));
4182 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
4183
4184 #ifdef READ_BYTES_WAIT_INT
4185 retval = ms_poll_int(chip);
4186 if (retval != STATUS_SUCCESS) {
4187 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4188 return STATUS_FAIL;
4189 }
4190 #endif
4191
4192 return STATUS_SUCCESS;
4193 }
4194
4195 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4196 {
4197 struct ms_info *ms_card = &chip->ms_card;
4198 int retval;
4199 int i;
4200 int bufflen;
4201 unsigned int lun = SCSI_LUN(srb);
4202 u8 buf[32];
4203
4204 ms_cleanup_work(chip);
4205
4206 retval = ms_switch_clock(chip);
4207 if (retval != STATUS_SUCCESS) {
4208 return STATUS_FAIL;
4209 }
4210
4211 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
4212 if (retval != STATUS_SUCCESS) {
4213 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4214 return STATUS_FAIL;
4215 }
4216
4217 bufflen = min_t(int, 12, scsi_bufflen(srb));
4218 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4219
4220 for (i = 0; i < 8; i++)
4221 buf[i] = buf[4 + i];
4222
4223 for (i = 0; i < 24; i++)
4224 buf[8 + i] = 0;
4225
4226 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
4227 buf, 32);
4228 if (retval != STATUS_SUCCESS) {
4229 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4230 return STATUS_FAIL;
4231 }
4232 if (check_ms_err(chip)) {
4233 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4234 rtsx_clear_ms_error(chip);
4235 return STATUS_FAIL;
4236 }
4237
4238 ms_card->mg_auth = 1;
4239
4240 return STATUS_SUCCESS;
4241 }
4242
4243 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4244 {
4245 struct ms_info *ms_card = &chip->ms_card;
4246 int retval;
4247 int bufflen;
4248 unsigned int lun = SCSI_LUN(srb);
4249 u8 *buf = NULL;
4250
4251 ms_cleanup_work(chip);
4252
4253 retval = ms_switch_clock(chip);
4254 if (retval != STATUS_SUCCESS) {
4255 return STATUS_FAIL;
4256 }
4257
4258 buf = kmalloc(1028, GFP_KERNEL);
4259 if (!buf) {
4260 return STATUS_ERROR;
4261 }
4262
4263 buf[0] = 0x04;
4264 buf[1] = 0x02;
4265 buf[2] = 0x00;
4266 buf[3] = 0x00;
4267
4268 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
4269 if (retval != STATUS_SUCCESS) {
4270 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4271 goto free_buffer;
4272 }
4273
4274 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4275 2, WAIT_INT, 0, 0, buf + 4, 1024);
4276 if (retval != STATUS_SUCCESS) {
4277 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4278 rtsx_clear_ms_error(chip);
4279 goto free_buffer;
4280 }
4281 if (check_ms_err(chip)) {
4282 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4283 rtsx_clear_ms_error(chip);
4284 retval = STATUS_FAIL;
4285 goto free_buffer;
4286 }
4287
4288 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4289 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4290
4291 free_buffer:
4292 kfree(buf);
4293 return retval;
4294 }
4295
4296 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4297 {
4298 struct ms_info *ms_card = &chip->ms_card;
4299 int retval;
4300 int bufflen;
4301 #ifdef MG_SET_ICV_SLOW
4302 int i;
4303 #endif
4304 unsigned int lun = SCSI_LUN(srb);
4305 u8 *buf = NULL;
4306
4307 ms_cleanup_work(chip);
4308
4309 retval = ms_switch_clock(chip);
4310 if (retval != STATUS_SUCCESS) {
4311 return STATUS_FAIL;
4312 }
4313
4314 buf = kmalloc(1028, GFP_KERNEL);
4315 if (!buf) {
4316 return STATUS_ERROR;
4317 }
4318
4319 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4320 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4321
4322 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4323 if (retval != STATUS_SUCCESS) {
4324 if (ms_card->mg_auth == 0) {
4325 if ((buf[5] & 0xC0) != 0)
4326 set_sense_type
4327 (chip, lun,
4328 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4329 else
4330 set_sense_type(chip, lun,
4331 SENSE_TYPE_MG_WRITE_ERR);
4332 } else {
4333 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4334 }
4335 goto SetICVFinish;
4336 }
4337
4338 #ifdef MG_SET_ICV_SLOW
4339 for (i = 0; i < 2; i++) {
4340 udelay(50);
4341
4342 rtsx_init_cmd(chip);
4343
4344 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
4345 0xFF, PRO_WRITE_LONG_DATA);
4346 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4347 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4348 0x01, RING_BUFFER);
4349
4350 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4351
4352 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4353 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4354 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
4355 MS_TRANSFER_END, MS_TRANSFER_END);
4356
4357 rtsx_send_cmd_no_wait(chip);
4358
4359 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512,
4360 512, 0, DMA_TO_DEVICE, 3000);
4361 if ((retval < 0) || check_ms_err(chip)) {
4362 rtsx_clear_ms_error(chip);
4363 if (ms_card->mg_auth == 0) {
4364 if ((buf[5] & 0xC0) != 0)
4365 set_sense_type
4366 (chip, lun,
4367 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4368 else
4369 set_sense_type(chip, lun,
4370 SENSE_TYPE_MG_WRITE_ERR);
4371 } else {
4372 set_sense_type(chip, lun,
4373 SENSE_TYPE_MG_WRITE_ERR);
4374 }
4375 retval = STATUS_FAIL;
4376 goto SetICVFinish;
4377 }
4378 }
4379 #else
4380 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4381 2, WAIT_INT, 0, 0, buf + 4, 1024);
4382 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
4383 rtsx_clear_ms_error(chip);
4384 if (ms_card->mg_auth == 0) {
4385 if ((buf[5] & 0xC0) != 0)
4386 set_sense_type
4387 (chip, lun,
4388 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4389 else
4390 set_sense_type(chip, lun,
4391 SENSE_TYPE_MG_WRITE_ERR);
4392 } else {
4393 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4394 }
4395 goto SetICVFinish;
4396 }
4397 #endif
4398
4399 SetICVFinish:
4400 kfree(buf);
4401 return retval;
4402 }
4403
4404 #endif /* SUPPORT_MAGIC_GATE */
4405
4406 void ms_cleanup_work(struct rtsx_chip *chip)
4407 {
4408 struct ms_info *ms_card = &chip->ms_card;
4409
4410 if (CHK_MSPRO(ms_card)) {
4411 if (ms_card->seq_mode) {
4412 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n");
4413 mspro_stop_seq_mode(chip);
4414 ms_card->cleanup_counter = 0;
4415 }
4416 if (CHK_MSHG(ms_card)) {
4417 rtsx_write_register(chip, MS_CFG,
4418 MS_2K_SECTOR_MODE, 0x00);
4419 }
4420 }
4421 #ifdef MS_DELAY_WRITE
4422 else if ((!CHK_MSPRO(ms_card)) &&
4423 ms_card->delay_write.delay_write_flag) {
4424 dev_dbg(rtsx_dev(chip), "MS: delay write\n");
4425 ms_delay_write(chip);
4426 ms_card->cleanup_counter = 0;
4427 }
4428 #endif
4429 }
4430
4431 int ms_power_off_card3v3(struct rtsx_chip *chip)
4432 {
4433 int retval;
4434
4435 retval = disable_card_clock(chip, MS_CARD);
4436 if (retval != STATUS_SUCCESS) {
4437 return STATUS_FAIL;
4438 }
4439
4440 if (chip->asic_code) {
4441 retval = ms_pull_ctl_disable(chip);
4442 if (retval != STATUS_SUCCESS) {
4443 return STATUS_FAIL;
4444 }
4445 } else {
4446 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4447 FPGA_MS_PULL_CTL_BIT | 0x20,
4448 FPGA_MS_PULL_CTL_BIT);
4449 if (retval) {
4450 return retval;
4451 }
4452 }
4453 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
4454 if (retval) {
4455 return retval;
4456 }
4457 if (!chip->ft2_fast_mode) {
4458 retval = card_power_off(chip, MS_CARD);
4459 if (retval != STATUS_SUCCESS) {
4460 return STATUS_FAIL;
4461 }
4462 }
4463
4464 return STATUS_SUCCESS;
4465 }
4466
4467 int release_ms_card(struct rtsx_chip *chip)
4468 {
4469 struct ms_info *ms_card = &chip->ms_card;
4470 int retval;
4471
4472 #ifdef MS_DELAY_WRITE
4473 ms_card->delay_write.delay_write_flag = 0;
4474 #endif
4475 ms_card->pro_under_formatting = 0;
4476
4477 chip->card_ready &= ~MS_CARD;
4478 chip->card_fail &= ~MS_CARD;
4479 chip->card_wp &= ~MS_CARD;
4480
4481 ms_free_l2p_tbl(chip);
4482
4483 memset(ms_card->raw_sys_info, 0, 96);
4484 #ifdef SUPPORT_PCGL_1P18
4485 memset(ms_card->raw_model_name, 0, 48);
4486 #endif
4487
4488 retval = ms_power_off_card3v3(chip);
4489 if (retval != STATUS_SUCCESS) {
4490 return STATUS_FAIL;
4491 }
4492
4493 return STATUS_SUCCESS;
4494 }
Linux with added FPC-III support