drivers/thunderbolt/eeprom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Thunderbolt Cactus Ridge driver - eeprom access
   4  *
   5  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
   6  */
   7
   8 #include <linux/crc32.h>
   9 #include <linux/property.h>
  10 #include <linux/slab.h>
  11 #include "tb.h"
  12
  13 /**
  14  * tb_eeprom_ctl_write() - write control word
  15  */
  16 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
  17 {
  18         return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
  19 }
  20
  21 /**
  22  * tb_eeprom_ctl_write() - read control word
  23  */
  24 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
  25 {
  26         return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
  27 }
  28
  29 enum tb_eeprom_transfer {
  30         TB_EEPROM_IN,
  31         TB_EEPROM_OUT,
  32 };
  33
  34 /**
  35  * tb_eeprom_active - enable rom access
  36  *
  37  * WARNING: Always disable access after usage. Otherwise the controller will
  38  * fail to reprobe.
  39  */
  40 static int tb_eeprom_active(struct tb_switch *sw, bool enable)
  41 {
  42         struct tb_eeprom_ctl ctl;
  43         int res = tb_eeprom_ctl_read(sw, &ctl);
  44         if (res)
  45                 return res;
  46         if (enable) {
  47                 ctl.access_high = 1;
  48                 res = tb_eeprom_ctl_write(sw, &ctl);
  49                 if (res)
  50                         return res;
  51                 ctl.access_low = 0;
  52                 return tb_eeprom_ctl_write(sw, &ctl);
  53         } else {
  54                 ctl.access_low = 1;
  55                 res = tb_eeprom_ctl_write(sw, &ctl);
  56                 if (res)
  57                         return res;
  58                 ctl.access_high = 0;
  59                 return tb_eeprom_ctl_write(sw, &ctl);
  60         }
  61 }
  62
  63 /**
  64  * tb_eeprom_transfer - transfer one bit
  65  *
  66  * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
  67  * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
  68  */
  69 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
  70                               enum tb_eeprom_transfer direction)
  71 {
  72         int res;
  73         if (direction == TB_EEPROM_OUT) {
  74                 res = tb_eeprom_ctl_write(sw, ctl);
  75                 if (res)
  76                         return res;
  77         }
  78         ctl->clock = 1;
  79         res = tb_eeprom_ctl_write(sw, ctl);
  80         if (res)
  81                 return res;
  82         if (direction == TB_EEPROM_IN) {
  83                 res = tb_eeprom_ctl_read(sw, ctl);
  84                 if (res)
  85                         return res;
  86         }
  87         ctl->clock = 0;
  88         return tb_eeprom_ctl_write(sw, ctl);
  89 }
  90
  91 /**
  92  * tb_eeprom_out - write one byte to the bus
  93  */
  94 static int tb_eeprom_out(struct tb_switch *sw, u8 val)
  95 {
  96         struct tb_eeprom_ctl ctl;
  97         int i;
  98         int res = tb_eeprom_ctl_read(sw, &ctl);
  99         if (res)
 100                 return res;
 101         for (i = 0; i < 8; i++) {
 102                 ctl.data_out = val & 0x80;
 103                 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
 104                 if (res)
 105                         return res;
 106                 val <<= 1;
 107         }
 108         return 0;
 109 }
 110
 111 /**
 112  * tb_eeprom_in - read one byte from the bus
 113  */
 114 static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
 115 {
 116         struct tb_eeprom_ctl ctl;
 117         int i;
 118         int res = tb_eeprom_ctl_read(sw, &ctl);
 119         if (res)
 120                 return res;
 121         *val = 0;
 122         for (i = 0; i < 8; i++) {
 123                 *val <<= 1;
 124                 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
 125                 if (res)
 126                         return res;
 127                 *val |= ctl.data_in;
 128         }
 129         return 0;
 130 }
 131
 132 /**
 133  * tb_eeprom_read_n - read count bytes from offset into val
 134  */
 135 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
 136                 size_t count)
 137 {
 138         int i, res;
 139         res = tb_eeprom_active(sw, true);
 140         if (res)
 141                 return res;
 142         res = tb_eeprom_out(sw, 3);
 143         if (res)
 144                 return res;
 145         res = tb_eeprom_out(sw, offset >> 8);
 146         if (res)
 147                 return res;
 148         res = tb_eeprom_out(sw, offset);
 149         if (res)
 150                 return res;
 151         for (i = 0; i < count; i++) {
 152                 res = tb_eeprom_in(sw, val + i);
 153                 if (res)
 154                         return res;
 155         }
 156         return tb_eeprom_active(sw, false);
 157 }
 158
 159 static u8 tb_crc8(u8 *data, int len)
 160 {
 161         int i, j;
 162         u8 val = 0xff;
 163         for (i = 0; i < len; i++) {
 164                 val ^= data[i];
 165                 for (j = 0; j < 8; j++)
 166                         val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
 167         }
 168         return val;
 169 }
 170
 171 static u32 tb_crc32(void *data, size_t len)
 172 {
 173         return ~__crc32c_le(~0, data, len);
 174 }
 175
 176 #define TB_DROM_DATA_START 13
 177 struct tb_drom_header {
 178         /* BYTE 0 */
 179         u8 uid_crc8; /* checksum for uid */
 180         /* BYTES 1-8 */
 181         u64 uid;
 182         /* BYTES 9-12 */
 183         u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
 184         /* BYTE 13 */
 185         u8 device_rom_revision; /* should be <= 1 */
 186         u16 data_len:10;
 187         u8 __unknown1:6;
 188         /* BYTES 16-21 */
 189         u16 vendor_id;
 190         u16 model_id;
 191         u8 model_rev;
 192         u8 eeprom_rev;
 193 } __packed;
 194
 195 enum tb_drom_entry_type {
 196         /* force unsigned to prevent "one-bit signed bitfield" warning */
 197         TB_DROM_ENTRY_GENERIC = 0U,
 198         TB_DROM_ENTRY_PORT,
 199 };
 200
 201 struct tb_drom_entry_header {
 202         u8 len;
 203         u8 index:6;
 204         bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
 205         enum tb_drom_entry_type type:1;
 206 } __packed;
 207
 208 struct tb_drom_entry_generic {
 209         struct tb_drom_entry_header header;
 210         u8 data[0];
 211 } __packed;
 212
 213 struct tb_drom_entry_port {
 214         /* BYTES 0-1 */
 215         struct tb_drom_entry_header header;
 216         /* BYTE 2 */
 217         u8 dual_link_port_rid:4;
 218         u8 link_nr:1;
 219         u8 unknown1:2;
 220         bool has_dual_link_port:1;
 221
 222         /* BYTE 3 */
 223         u8 dual_link_port_nr:6;
 224         u8 unknown2:2;
 225
 226         /* BYTES 4 - 5 TODO decode */
 227         u8 micro2:4;
 228         u8 micro1:4;
 229         u8 micro3;
 230
 231         /* BYTES 6-7, TODO: verify (find hardware that has these set) */
 232         u8 peer_port_rid:4;
 233         u8 unknown3:3;
 234         bool has_peer_port:1;
 235         u8 peer_port_nr:6;
 236         u8 unknown4:2;
 237 } __packed;
 238
 239
 240 /**
 241  * tb_eeprom_get_drom_offset - get drom offset within eeprom
 242  */
 243 static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
 244 {
 245         struct tb_cap_plug_events cap;
 246         int res;
 247         if (!sw->cap_plug_events) {
 248                 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
 249                 return -ENOSYS;
 250         }
 251         res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
 252                              sizeof(cap) / 4);
 253         if (res)
 254                 return res;
 255
 256         if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
 257                 tb_sw_warn(sw, "no NVM\n");
 258                 return -ENOSYS;
 259         }
 260
 261         if (cap.drom_offset > 0xffff) {
 262                 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
 263                                 cap.drom_offset);
 264                 return -ENXIO;
 265         }
 266         *offset = cap.drom_offset;
 267         return 0;
 268 }
 269
 270 /**
 271  * tb_drom_read_uid_only - read uid directly from drom
 272  *
 273  * Does not use the cached copy in sw->drom. Used during resume to check switch
 274  * identity.
 275  */
 276 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
 277 {
 278         u8 data[9];
 279         u16 drom_offset;
 280         u8 crc;
 281         int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
 282         if (res)
 283                 return res;
 284
 285         if (drom_offset == 0)
 286                 return -ENODEV;
 287
 288         /* read uid */
 289         res = tb_eeprom_read_n(sw, drom_offset, data, 9);
 290         if (res)
 291                 return res;
 292
 293         crc = tb_crc8(data + 1, 8);
 294         if (crc != data[0]) {
 295                 tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
 296                                 data[0], crc);
 297                 return -EIO;
 298         }
 299
 300         *uid = *(u64 *)(data+1);
 301         return 0;
 302 }
 303
 304 static int tb_drom_parse_entry_generic(struct tb_switch *sw,
 305                 struct tb_drom_entry_header *header)
 306 {
 307         const struct tb_drom_entry_generic *entry =
 308                 (const struct tb_drom_entry_generic *)header;
 309
 310         switch (header->index) {
 311         case 1:
 312                 /* Length includes 2 bytes header so remove it before copy */
 313                 sw->vendor_name = kstrndup(entry->data,
 314                         header->len - sizeof(*header), GFP_KERNEL);
 315                 if (!sw->vendor_name)
 316                         return -ENOMEM;
 317                 break;
 318
 319         case 2:
 320                 sw->device_name = kstrndup(entry->data,
 321                         header->len - sizeof(*header), GFP_KERNEL);
 322                 if (!sw->device_name)
 323                         return -ENOMEM;
 324                 break;
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int tb_drom_parse_entry_port(struct tb_switch *sw,
 331                                     struct tb_drom_entry_header *header)
 332 {
 333         struct tb_port *port;
 334         int res;
 335         enum tb_port_type type;
 336
 337         /*
 338          * Some DROMs list more ports than the controller actually has
 339          * so we skip those but allow the parser to continue.
 340          */
 341         if (header->index > sw->config.max_port_number) {
 342                 dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
 343                 return 0;
 344         }
 345
 346         port = &sw->ports[header->index];
 347         port->disabled = header->port_disabled;
 348         if (port->disabled)
 349                 return 0;
 350
 351         res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
 352         if (res)
 353                 return res;
 354         type &= 0xffffff;
 355
 356         if (type == TB_TYPE_PORT) {
 357                 struct tb_drom_entry_port *entry = (void *) header;
 358                 if (header->len != sizeof(*entry)) {
 359                         tb_sw_warn(sw,
 360                                 "port entry has size %#x (expected %#zx)\n",
 361                                 header->len, sizeof(struct tb_drom_entry_port));
 362                         return -EIO;
 363                 }
 364                 port->link_nr = entry->link_nr;
 365                 if (entry->has_dual_link_port)
 366                         port->dual_link_port =
 367                                 &port->sw->ports[entry->dual_link_port_nr];
 368         }
 369         return 0;
 370 }
 371
 372 /**
 373  * tb_drom_parse_entries - parse the linked list of drom entries
 374  *
 375  * Drom must have been copied to sw->drom.
 376  */
 377 static int tb_drom_parse_entries(struct tb_switch *sw)
 378 {
 379         struct tb_drom_header *header = (void *) sw->drom;
 380         u16 pos = sizeof(*header);
 381         u16 drom_size = header->data_len + TB_DROM_DATA_START;
 382         int res;
 383
 384         while (pos < drom_size) {
 385                 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
 386                 if (pos + 1 == drom_size || pos + entry->len > drom_size
 387                                 || !entry->len) {
 388                         tb_sw_warn(sw, "drom buffer overrun, aborting\n");
 389                         return -EIO;
 390                 }
 391
 392                 switch (entry->type) {
 393                 case TB_DROM_ENTRY_GENERIC:
 394                         res = tb_drom_parse_entry_generic(sw, entry);
 395                         break;
 396                 case TB_DROM_ENTRY_PORT:
 397                         res = tb_drom_parse_entry_port(sw, entry);
 398                         break;
 399                 }
 400                 if (res)
 401                         return res;
 402
 403                 pos += entry->len;
 404         }
 405         return 0;
 406 }
 407
 408 /**
 409  * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
 410  */
 411 static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
 412 {
 413         struct device *dev = &sw->tb->nhi->pdev->dev;
 414         int len, res;
 415
 416         len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
 417         if (len < 0 || len < sizeof(struct tb_drom_header))
 418                 return -EINVAL;
 419
 420         sw->drom = kmalloc(len, GFP_KERNEL);
 421         if (!sw->drom)
 422                 return -ENOMEM;
 423
 424         res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
 425                                                                         len);
 426         if (res)
 427                 goto err;
 428
 429         *size = ((struct tb_drom_header *)sw->drom)->data_len +
 430                                                           TB_DROM_DATA_START;
 431         if (*size > len)
 432                 goto err;
 433
 434         return 0;
 435
 436 err:
 437         kfree(sw->drom);
 438         sw->drom = NULL;
 439         return -EINVAL;
 440 }
 441
 442 static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
 443 {
 444         u32 drom_offset;
 445         int ret;
 446
 447         if (!sw->dma_port)
 448                 return -ENODEV;
 449
 450         ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
 451                          sw->cap_plug_events + 12, 1);
 452         if (ret)
 453                 return ret;
 454
 455         if (!drom_offset)
 456                 return -ENODEV;
 457
 458         ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
 459                                   sizeof(*size));
 460         if (ret)
 461                 return ret;
 462
 463         /* Size includes CRC8 + UID + CRC32 */
 464         *size += 1 + 8 + 4;
 465         sw->drom = kzalloc(*size, GFP_KERNEL);
 466         if (!sw->drom)
 467                 return -ENOMEM;
 468
 469         ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
 470         if (ret)
 471                 goto err_free;
 472
 473         /*
 474          * Read UID from the minimal DROM because the one in NVM is just
 475          * a placeholder.
 476          */
 477         tb_drom_read_uid_only(sw, &sw->uid);
 478         return 0;
 479
 480 err_free:
 481         kfree(sw->drom);
 482         sw->drom = NULL;
 483         return ret;
 484 }
 485
 486 /**
 487  * tb_drom_read - copy drom to sw->drom and parse it
 488  */
 489 int tb_drom_read(struct tb_switch *sw)
 490 {
 491         u16 drom_offset;
 492         u16 size;
 493         u32 crc;
 494         struct tb_drom_header *header;
 495         int res;
 496         if (sw->drom)
 497                 return 0;
 498
 499         if (tb_route(sw) == 0) {
 500                 /*
 501                  * Apple's NHI EFI driver supplies a DROM for the root switch
 502                  * in a device property. Use it if available.
 503                  */
 504                 if (tb_drom_copy_efi(sw, &size) == 0)
 505                         goto parse;
 506
 507                 /* Non-Apple hardware has the DROM as part of NVM */
 508                 if (tb_drom_copy_nvm(sw, &size) == 0)
 509                         goto parse;
 510
 511                 /*
 512                  * The root switch contains only a dummy drom (header only,
 513                  * no entries). Hardcode the configuration here.
 514                  */
 515                 tb_drom_read_uid_only(sw, &sw->uid);
 516
 517                 sw->ports[1].link_nr = 0;
 518                 sw->ports[2].link_nr = 1;
 519                 sw->ports[1].dual_link_port = &sw->ports[2];
 520                 sw->ports[2].dual_link_port = &sw->ports[1];
 521
 522                 sw->ports[3].link_nr = 0;
 523                 sw->ports[4].link_nr = 1;
 524                 sw->ports[3].dual_link_port = &sw->ports[4];
 525                 sw->ports[4].dual_link_port = &sw->ports[3];
 526
 527                 /* Port 5 is inaccessible on this gen 1 controller */
 528                 if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
 529                         sw->ports[5].disabled = true;
 530
 531                 return 0;
 532         }
 533
 534         res = tb_eeprom_get_drom_offset(sw, &drom_offset);
 535         if (res)
 536                 return res;
 537
 538         res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
 539         if (res)
 540                 return res;
 541         size &= 0x3ff;
 542         size += TB_DROM_DATA_START;
 543         tb_sw_info(sw, "reading drom (length: %#x)\n", size);
 544         if (size < sizeof(*header)) {
 545                 tb_sw_warn(sw, "drom too small, aborting\n");
 546                 return -EIO;
 547         }
 548
 549         sw->drom = kzalloc(size, GFP_KERNEL);
 550         if (!sw->drom)
 551                 return -ENOMEM;
 552         res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
 553         if (res)
 554                 goto err;
 555
 556 parse:
 557         header = (void *) sw->drom;
 558
 559         if (header->data_len + TB_DROM_DATA_START != size) {
 560                 tb_sw_warn(sw, "drom size mismatch, aborting\n");
 561                 goto err;
 562         }
 563
 564         crc = tb_crc8((u8 *) &header->uid, 8);
 565         if (crc != header->uid_crc8) {
 566                 tb_sw_warn(sw,
 567                         "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
 568                         header->uid_crc8, crc);
 569                 goto err;
 570         }
 571         if (!sw->uid)
 572                 sw->uid = header->uid;
 573         sw->vendor = header->vendor_id;
 574         sw->device = header->model_id;
 575
 576         crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
 577         if (crc != header->data_crc32) {
 578                 tb_sw_warn(sw,
 579                         "drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
 580                         header->data_crc32, crc);
 581         }
 582
 583         if (header->device_rom_revision > 2)
 584                 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
 585                         header->device_rom_revision);
 586
 587         return tb_drom_parse_entries(sw);
 588 err:
 589         kfree(sw->drom);
 590         sw->drom = NULL;
 591         return -EIO;
 592
 593 }