?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blob4066cb2b79cb0c756e5be4232deaa61fd6a38ba9
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/platform_device.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/rational.h>
28 #include <linux/slab.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/io.h>
32 #include <linux/dma-mapping.h>
33
34 #include <asm/irq.h>
35 #include <linux/platform_data/serial-imx.h>
36 #include <linux/platform_data/dma-imx.h>
37
38 #include "serial_mctrl_gpio.h"
39
40 /* Register definitions */
41 #define URXD0 0x0 /* Receiver Register */
42 #define URTX0 0x40 /* Transmitter Register */
43 #define UCR1 0x80 /* Control Register 1 */
44 #define UCR2 0x84 /* Control Register 2 */
45 #define UCR3 0x88 /* Control Register 3 */
46 #define UCR4 0x8c /* Control Register 4 */
47 #define UFCR 0x90 /* FIFO Control Register */
48 #define USR1 0x94 /* Status Register 1 */
49 #define USR2 0x98 /* Status Register 2 */
50 #define UESC 0x9c /* Escape Character Register */
51 #define UTIM 0xa0 /* Escape Timer Register */
52 #define UBIR 0xa4 /* BRM Incremental Register */
53 #define UBMR 0xa8 /* BRM Modulator Register */
54 #define UBRC 0xac /* Baud Rate Count Register */
55 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
56 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
57 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
58
59 /* UART Control Register Bit Fields.*/
60 #define URXD_DUMMY_READ (1<<16)
61 #define URXD_CHARRDY (1<<15)
62 #define URXD_ERR (1<<14)
63 #define URXD_OVRRUN (1<<13)
64 #define URXD_FRMERR (1<<12)
65 #define URXD_BRK (1<<11)
66 #define URXD_PRERR (1<<10)
67 #define URXD_RX_DATA (0xFF<<0)
68 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
69 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
70 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
71 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
72 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
73 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
74 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
75 #define UCR1_IREN (1<<7) /* Infrared interface enable */
76 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
77 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
78 #define UCR1_SNDBRK (1<<4) /* Send break */
79 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
80 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
81 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82 #define UCR1_DOZE (1<<1) /* Doze */
83 #define UCR1_UARTEN (1<<0) /* UART enabled */
84 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
85 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
86 #define UCR2_CTSC (1<<13) /* CTS pin control */
87 #define UCR2_CTS (1<<12) /* Clear to send */
88 #define UCR2_ESCEN (1<<11) /* Escape enable */
89 #define UCR2_PREN (1<<8) /* Parity enable */
90 #define UCR2_PROE (1<<7) /* Parity odd/even */
91 #define UCR2_STPB (1<<6) /* Stop */
92 #define UCR2_WS (1<<5) /* Word size */
93 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
94 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
95 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
96 #define UCR2_RXEN (1<<1) /* Receiver enabled */
97 #define UCR2_SRST (1<<0) /* SW reset */
98 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
99 #define UCR3_PARERREN (1<<12) /* Parity enable */
100 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
101 #define UCR3_DSR (1<<10) /* Data set ready */
102 #define UCR3_DCD (1<<9) /* Data carrier detect */
103 #define UCR3_RI (1<<8) /* Ring indicator */
104 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
105 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
106 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
107 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
108 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
109 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
110 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
111 #define UCR3_BPEN (1<<0) /* Preset registers enable */
112 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
113 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
114 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
115 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
116 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
117 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
118 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
119 #define UCR4_IRSC (1<<5) /* IR special case */
120 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
121 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
122 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
123 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
124 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
125 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
126 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
127 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
128 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
129 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
130 #define USR1_RTSS (1<<14) /* RTS pin status */
131 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
132 #define USR1_RTSD (1<<12) /* RTS delta */
133 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
134 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
135 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
136 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
137 #define USR1_DTRD (1<<7) /* DTR Delta */
138 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
139 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
140 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
141 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
142 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
143 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
144 #define USR2_IDLE (1<<12) /* Idle condition */
145 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
146 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
147 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
148 #define USR2_WAKE (1<<7) /* Wake */
149 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
150 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
151 #define USR2_TXDC (1<<3) /* Transmitter complete */
152 #define USR2_BRCD (1<<2) /* Break condition */
153 #define USR2_ORE (1<<1) /* Overrun error */
154 #define USR2_RDR (1<<0) /* Recv data ready */
155 #define UTS_FRCPERR (1<<13) /* Force parity error */
156 #define UTS_LOOP (1<<12) /* Loop tx and rx */
157 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
158 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
159 #define UTS_TXFULL (1<<4) /* TxFIFO full */
160 #define UTS_RXFULL (1<<3) /* RxFIFO full */
161 #define UTS_SOFTRST (1<<0) /* Software reset */
162
163 /* We've been assigned a range on the "Low-density serial ports" major */
164 #define SERIAL_IMX_MAJOR 207
165 #define MINOR_START 16
166 #define DEV_NAME "ttymxc"
167
168 /*
169 * This determines how often we check the modem status signals
170 * for any change. They generally aren't connected to an IRQ
171 * so we have to poll them. We also check immediately before
172 * filling the TX fifo incase CTS has been dropped.
173 */
174 #define MCTRL_TIMEOUT (250*HZ/1000)
175
176 #define DRIVER_NAME "IMX-uart"
177
178 #define UART_NR 8
179
180 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
181 enum imx_uart_type {
182 IMX1_UART,
183 IMX21_UART,
184 IMX53_UART,
185 IMX6Q_UART,
186 };
187
188 /* device type dependent stuff */
189 struct imx_uart_data {
190 unsigned uts_reg;
191 enum imx_uart_type devtype;
192 };
193
194 struct imx_port {
195 struct uart_port port;
196 struct timer_list timer;
197 unsigned int old_status;
198 unsigned int have_rtscts:1;
199 unsigned int have_rtsgpio:1;
200 unsigned int dte_mode:1;
201 struct clk *clk_ipg;
202 struct clk *clk_per;
203 const struct imx_uart_data *devdata;
204
205 struct mctrl_gpios *gpios;
206
207 /* shadow registers */
208 unsigned int ucr1;
209 unsigned int ucr2;
210 unsigned int ucr3;
211 unsigned int ucr4;
212 unsigned int ufcr;
213
214 /* DMA fields */
215 unsigned int dma_is_enabled:1;
216 unsigned int dma_is_rxing:1;
217 unsigned int dma_is_txing:1;
218 struct dma_chan *dma_chan_rx, *dma_chan_tx;
219 struct scatterlist rx_sgl, tx_sgl[2];
220 void *rx_buf;
221 struct circ_buf rx_ring;
222 unsigned int rx_periods;
223 dma_cookie_t rx_cookie;
224 unsigned int tx_bytes;
225 unsigned int dma_tx_nents;
226 unsigned int saved_reg[10];
227 bool context_saved;
228 };
229
230 struct imx_port_ucrs {
231 unsigned int ucr1;
232 unsigned int ucr2;
233 unsigned int ucr3;
234 };
235
236 static struct imx_uart_data imx_uart_devdata[] = {
237 [IMX1_UART] = {
238 .uts_reg = IMX1_UTS,
239 .devtype = IMX1_UART,
240 },
241 [IMX21_UART] = {
242 .uts_reg = IMX21_UTS,
243 .devtype = IMX21_UART,
244 },
245 [IMX53_UART] = {
246 .uts_reg = IMX21_UTS,
247 .devtype = IMX53_UART,
248 },
249 [IMX6Q_UART] = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX6Q_UART,
252 },
253 };
254
255 static const struct platform_device_id imx_uart_devtype[] = {
256 {
257 .name = "imx1-uart",
258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
259 }, {
260 .name = "imx21-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
262 }, {
263 .name = "imx53-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
268 }, {
269 /* sentinel */
270 }
271 };
272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
274 static const struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
279 { /* sentinel */ }
280 };
281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
282
283 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
284 {
285 switch (offset) {
286 case UCR1:
287 sport->ucr1 = val;
288 break;
289 case UCR2:
290 sport->ucr2 = val;
291 break;
292 case UCR3:
293 sport->ucr3 = val;
294 break;
295 case UCR4:
296 sport->ucr4 = val;
297 break;
298 case UFCR:
299 sport->ufcr = val;
300 break;
301 default:
302 break;
303 }
304 writel(val, sport->port.membase + offset);
305 }
306
307 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
308 {
309 switch (offset) {
310 case UCR1:
311 return sport->ucr1;
312 break;
313 case UCR2:
314 /*
315 * UCR2_SRST is the only bit in the cached registers that might
316 * differ from the value that was last written. As it only
317 * automatically becomes one after being cleared, reread
318 * conditionally.
319 */
320 if (!(sport->ucr2 & UCR2_SRST))
321 sport->ucr2 = readl(sport->port.membase + offset);
322 return sport->ucr2;
323 break;
324 case UCR3:
325 return sport->ucr3;
326 break;
327 case UCR4:
328 return sport->ucr4;
329 break;
330 case UFCR:
331 return sport->ufcr;
332 break;
333 default:
334 return readl(sport->port.membase + offset);
335 }
336 }
337
338 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
339 {
340 return sport->devdata->uts_reg;
341 }
342
343 static inline int imx_uart_is_imx1(struct imx_port *sport)
344 {
345 return sport->devdata->devtype == IMX1_UART;
346 }
347
348 static inline int imx_uart_is_imx21(struct imx_port *sport)
349 {
350 return sport->devdata->devtype == IMX21_UART;
351 }
352
353 static inline int imx_uart_is_imx53(struct imx_port *sport)
354 {
355 return sport->devdata->devtype == IMX53_UART;
356 }
357
358 static inline int imx_uart_is_imx6q(struct imx_port *sport)
359 {
360 return sport->devdata->devtype == IMX6Q_UART;
361 }
362 /*
363 * Save and restore functions for UCR1, UCR2 and UCR3 registers
364 */
365 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
366 static void imx_uart_ucrs_save(struct imx_port *sport,
367 struct imx_port_ucrs *ucr)
368 {
369 /* save control registers */
370 ucr->ucr1 = imx_uart_readl(sport, UCR1);
371 ucr->ucr2 = imx_uart_readl(sport, UCR2);
372 ucr->ucr3 = imx_uart_readl(sport, UCR3);
373 }
374
375 static void imx_uart_ucrs_restore(struct imx_port *sport,
376 struct imx_port_ucrs *ucr)
377 {
378 /* restore control registers */
379 imx_uart_writel(sport, ucr->ucr1, UCR1);
380 imx_uart_writel(sport, ucr->ucr2, UCR2);
381 imx_uart_writel(sport, ucr->ucr3, UCR3);
382 }
383 #endif
384
385 /* called with port.lock taken and irqs caller dependent */
386 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
387 {
388 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
389
390 sport->port.mctrl |= TIOCM_RTS;
391 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
392 }
393
394 /* called with port.lock taken and irqs caller dependent */
395 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
396 {
397 *ucr2 &= ~UCR2_CTSC;
398 *ucr2 |= UCR2_CTS;
399
400 sport->port.mctrl &= ~TIOCM_RTS;
401 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
402 }
403
404 /* called with port.lock taken and irqs caller dependent */
405 static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2)
406 {
407 *ucr2 |= UCR2_CTSC;
408 }
409
410 /* called with port.lock taken and irqs off */
411 static void imx_uart_start_rx(struct uart_port *port)
412 {
413 struct imx_port *sport = (struct imx_port *)port;
414 unsigned int ucr1, ucr2;
415
416 ucr1 = imx_uart_readl(sport, UCR1);
417 ucr2 = imx_uart_readl(sport, UCR2);
418
419 ucr2 |= UCR2_RXEN;
420
421 if (sport->dma_is_enabled) {
422 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
423 } else {
424 ucr1 |= UCR1_RRDYEN;
425 ucr2 |= UCR2_ATEN;
426 }
427
428 /* Write UCR2 first as it includes RXEN */
429 imx_uart_writel(sport, ucr2, UCR2);
430 imx_uart_writel(sport, ucr1, UCR1);
431 }
432
433 /* called with port.lock taken and irqs off */
434 static void imx_uart_stop_tx(struct uart_port *port)
435 {
436 struct imx_port *sport = (struct imx_port *)port;
437 u32 ucr1;
438
439 /*
440 * We are maybe in the SMP context, so if the DMA TX thread is running
441 * on other cpu, we have to wait for it to finish.
442 */
443 if (sport->dma_is_txing)
444 return;
445
446 ucr1 = imx_uart_readl(sport, UCR1);
447 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
448
449 /* in rs485 mode disable transmitter if shifter is empty */
450 if (port->rs485.flags & SER_RS485_ENABLED &&
451 imx_uart_readl(sport, USR2) & USR2_TXDC) {
452 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
453 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
454 imx_uart_rts_active(sport, &ucr2);
455 else
456 imx_uart_rts_inactive(sport, &ucr2);
457 imx_uart_writel(sport, ucr2, UCR2);
458
459 imx_uart_start_rx(port);
460
461 ucr4 = imx_uart_readl(sport, UCR4);
462 ucr4 &= ~UCR4_TCEN;
463 imx_uart_writel(sport, ucr4, UCR4);
464 }
465 }
466
467 /* called with port.lock taken and irqs off */
468 static void imx_uart_stop_rx(struct uart_port *port)
469 {
470 struct imx_port *sport = (struct imx_port *)port;
471 u32 ucr1, ucr2;
472
473 ucr1 = imx_uart_readl(sport, UCR1);
474 ucr2 = imx_uart_readl(sport, UCR2);
475
476 if (sport->dma_is_enabled) {
477 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
478 } else {
479 ucr1 &= ~UCR1_RRDYEN;
480 ucr2 &= ~UCR2_ATEN;
481 }
482 imx_uart_writel(sport, ucr1, UCR1);
483
484 ucr2 &= ~UCR2_RXEN;
485 imx_uart_writel(sport, ucr2, UCR2);
486 }
487
488 /* called with port.lock taken and irqs off */
489 static void imx_uart_enable_ms(struct uart_port *port)
490 {
491 struct imx_port *sport = (struct imx_port *)port;
492
493 mod_timer(&sport->timer, jiffies);
494
495 mctrl_gpio_enable_ms(sport->gpios);
496 }
497
498 static void imx_uart_dma_tx(struct imx_port *sport);
499
500 /* called with port.lock taken and irqs off */
501 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
502 {
503 struct circ_buf *xmit = &sport->port.state->xmit;
504
505 if (sport->port.x_char) {
506 /* Send next char */
507 imx_uart_writel(sport, sport->port.x_char, URTX0);
508 sport->port.icount.tx++;
509 sport->port.x_char = 0;
510 return;
511 }
512
513 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
514 imx_uart_stop_tx(&sport->port);
515 return;
516 }
517
518 if (sport->dma_is_enabled) {
519 u32 ucr1;
520 /*
521 * We've just sent a X-char Ensure the TX DMA is enabled
522 * and the TX IRQ is disabled.
523 **/
524 ucr1 = imx_uart_readl(sport, UCR1);
525 ucr1 &= ~UCR1_TXMPTYEN;
526 if (sport->dma_is_txing) {
527 ucr1 |= UCR1_TXDMAEN;
528 imx_uart_writel(sport, ucr1, UCR1);
529 } else {
530 imx_uart_writel(sport, ucr1, UCR1);
531 imx_uart_dma_tx(sport);
532 }
533
534 return;
535 }
536
537 while (!uart_circ_empty(xmit) &&
538 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
539 /* send xmit->buf[xmit->tail]
540 * out the port here */
541 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
542 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
543 sport->port.icount.tx++;
544 }
545
546 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
547 uart_write_wakeup(&sport->port);
548
549 if (uart_circ_empty(xmit))
550 imx_uart_stop_tx(&sport->port);
551 }
552
553 static void imx_uart_dma_tx_callback(void *data)
554 {
555 struct imx_port *sport = data;
556 struct scatterlist *sgl = &sport->tx_sgl[0];
557 struct circ_buf *xmit = &sport->port.state->xmit;
558 unsigned long flags;
559 u32 ucr1;
560
561 spin_lock_irqsave(&sport->port.lock, flags);
562
563 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
564
565 ucr1 = imx_uart_readl(sport, UCR1);
566 ucr1 &= ~UCR1_TXDMAEN;
567 imx_uart_writel(sport, ucr1, UCR1);
568
569 /* update the stat */
570 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
571 sport->port.icount.tx += sport->tx_bytes;
572
573 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
574
575 sport->dma_is_txing = 0;
576
577 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
578 uart_write_wakeup(&sport->port);
579
580 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
581 imx_uart_dma_tx(sport);
582 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
583 u32 ucr4 = imx_uart_readl(sport, UCR4);
584 ucr4 |= UCR4_TCEN;
585 imx_uart_writel(sport, ucr4, UCR4);
586 }
587
588 spin_unlock_irqrestore(&sport->port.lock, flags);
589 }
590
591 /* called with port.lock taken and irqs off */
592 static void imx_uart_dma_tx(struct imx_port *sport)
593 {
594 struct circ_buf *xmit = &sport->port.state->xmit;
595 struct scatterlist *sgl = sport->tx_sgl;
596 struct dma_async_tx_descriptor *desc;
597 struct dma_chan *chan = sport->dma_chan_tx;
598 struct device *dev = sport->port.dev;
599 u32 ucr1, ucr4;
600 int ret;
601
602 if (sport->dma_is_txing)
603 return;
604
605 ucr4 = imx_uart_readl(sport, UCR4);
606 ucr4 &= ~UCR4_TCEN;
607 imx_uart_writel(sport, ucr4, UCR4);
608
609 sport->tx_bytes = uart_circ_chars_pending(xmit);
610
611 if (xmit->tail < xmit->head || xmit->head == 0) {
612 sport->dma_tx_nents = 1;
613 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
614 } else {
615 sport->dma_tx_nents = 2;
616 sg_init_table(sgl, 2);
617 sg_set_buf(sgl, xmit->buf + xmit->tail,
618 UART_XMIT_SIZE - xmit->tail);
619 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
620 }
621
622 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
623 if (ret == 0) {
624 dev_err(dev, "DMA mapping error for TX.\n");
625 return;
626 }
627 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
628 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
629 if (!desc) {
630 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
631 DMA_TO_DEVICE);
632 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
633 return;
634 }
635 desc->callback = imx_uart_dma_tx_callback;
636 desc->callback_param = sport;
637
638 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
639 uart_circ_chars_pending(xmit));
640
641 ucr1 = imx_uart_readl(sport, UCR1);
642 ucr1 |= UCR1_TXDMAEN;
643 imx_uart_writel(sport, ucr1, UCR1);
644
645 /* fire it */
646 sport->dma_is_txing = 1;
647 dmaengine_submit(desc);
648 dma_async_issue_pending(chan);
649 return;
650 }
651
652 /* called with port.lock taken and irqs off */
653 static void imx_uart_start_tx(struct uart_port *port)
654 {
655 struct imx_port *sport = (struct imx_port *)port;
656 u32 ucr1;
657
658 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
659 return;
660
661 if (port->rs485.flags & SER_RS485_ENABLED) {
662 u32 ucr2;
663
664 ucr2 = imx_uart_readl(sport, UCR2);
665 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
666 imx_uart_rts_active(sport, &ucr2);
667 else
668 imx_uart_rts_inactive(sport, &ucr2);
669 imx_uart_writel(sport, ucr2, UCR2);
670
671 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
672 imx_uart_stop_rx(port);
673
674 /*
675 * Enable transmitter and shifter empty irq only if DMA is off.
676 * In the DMA case this is done in the tx-callback.
677 */
678 if (!sport->dma_is_enabled) {
679 u32 ucr4 = imx_uart_readl(sport, UCR4);
680 ucr4 |= UCR4_TCEN;
681 imx_uart_writel(sport, ucr4, UCR4);
682 }
683 }
684
685 if (!sport->dma_is_enabled) {
686 ucr1 = imx_uart_readl(sport, UCR1);
687 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
688 }
689
690 if (sport->dma_is_enabled) {
691 if (sport->port.x_char) {
692 /* We have X-char to send, so enable TX IRQ and
693 * disable TX DMA to let TX interrupt to send X-char */
694 ucr1 = imx_uart_readl(sport, UCR1);
695 ucr1 &= ~UCR1_TXDMAEN;
696 ucr1 |= UCR1_TXMPTYEN;
697 imx_uart_writel(sport, ucr1, UCR1);
698 return;
699 }
700
701 if (!uart_circ_empty(&port->state->xmit) &&
702 !uart_tx_stopped(port))
703 imx_uart_dma_tx(sport);
704 return;
705 }
706 }
707
708 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
709 {
710 struct imx_port *sport = dev_id;
711 u32 usr1;
712 unsigned long flags;
713
714 spin_lock_irqsave(&sport->port.lock, flags);
715
716 imx_uart_writel(sport, USR1_RTSD, USR1);
717 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
718 uart_handle_cts_change(&sport->port, !!usr1);
719 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
720
721 spin_unlock_irqrestore(&sport->port.lock, flags);
722 return IRQ_HANDLED;
723 }
724
725 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
726 {
727 struct imx_port *sport = dev_id;
728 unsigned long flags;
729
730 spin_lock_irqsave(&sport->port.lock, flags);
731 imx_uart_transmit_buffer(sport);
732 spin_unlock_irqrestore(&sport->port.lock, flags);
733 return IRQ_HANDLED;
734 }
735
736 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
737 {
738 struct imx_port *sport = dev_id;
739 unsigned int rx, flg, ignored = 0;
740 struct tty_port *port = &sport->port.state->port;
741 unsigned long flags;
742
743 spin_lock_irqsave(&sport->port.lock, flags);
744
745 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
746 u32 usr2;
747
748 flg = TTY_NORMAL;
749 sport->port.icount.rx++;
750
751 rx = imx_uart_readl(sport, URXD0);
752
753 usr2 = imx_uart_readl(sport, USR2);
754 if (usr2 & USR2_BRCD) {
755 imx_uart_writel(sport, USR2_BRCD, USR2);
756 if (uart_handle_break(&sport->port))
757 continue;
758 }
759
760 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
761 continue;
762
763 if (unlikely(rx & URXD_ERR)) {
764 if (rx & URXD_BRK)
765 sport->port.icount.brk++;
766 else if (rx & URXD_PRERR)
767 sport->port.icount.parity++;
768 else if (rx & URXD_FRMERR)
769 sport->port.icount.frame++;
770 if (rx & URXD_OVRRUN)
771 sport->port.icount.overrun++;
772
773 if (rx & sport->port.ignore_status_mask) {
774 if (++ignored > 100)
775 goto out;
776 continue;
777 }
778
779 rx &= (sport->port.read_status_mask | 0xFF);
780
781 if (rx & URXD_BRK)
782 flg = TTY_BREAK;
783 else if (rx & URXD_PRERR)
784 flg = TTY_PARITY;
785 else if (rx & URXD_FRMERR)
786 flg = TTY_FRAME;
787 if (rx & URXD_OVRRUN)
788 flg = TTY_OVERRUN;
789
790 #ifdef SUPPORT_SYSRQ
791 sport->port.sysrq = 0;
792 #endif
793 }
794
795 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
796 goto out;
797
798 if (tty_insert_flip_char(port, rx, flg) == 0)
799 sport->port.icount.buf_overrun++;
800 }
801
802 out:
803 spin_unlock_irqrestore(&sport->port.lock, flags);
804 tty_flip_buffer_push(port);
805 return IRQ_HANDLED;
806 }
807
808 static void imx_uart_clear_rx_errors(struct imx_port *sport);
809
810 /*
811 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
812 */
813 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
814 {
815 unsigned int tmp = TIOCM_DSR;
816 unsigned usr1 = imx_uart_readl(sport, USR1);
817 unsigned usr2 = imx_uart_readl(sport, USR2);
818
819 if (usr1 & USR1_RTSS)
820 tmp |= TIOCM_CTS;
821
822 /* in DCE mode DCDIN is always 0 */
823 if (!(usr2 & USR2_DCDIN))
824 tmp |= TIOCM_CAR;
825
826 if (sport->dte_mode)
827 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
828 tmp |= TIOCM_RI;
829
830 return tmp;
831 }
832
833 /*
834 * Handle any change of modem status signal since we were last called.
835 */
836 static void imx_uart_mctrl_check(struct imx_port *sport)
837 {
838 unsigned int status, changed;
839
840 status = imx_uart_get_hwmctrl(sport);
841 changed = status ^ sport->old_status;
842
843 if (changed == 0)
844 return;
845
846 sport->old_status = status;
847
848 if (changed & TIOCM_RI && status & TIOCM_RI)
849 sport->port.icount.rng++;
850 if (changed & TIOCM_DSR)
851 sport->port.icount.dsr++;
852 if (changed & TIOCM_CAR)
853 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
854 if (changed & TIOCM_CTS)
855 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
856
857 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
858 }
859
860 static irqreturn_t imx_uart_int(int irq, void *dev_id)
861 {
862 struct imx_port *sport = dev_id;
863 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
864 irqreturn_t ret = IRQ_NONE;
865
866 usr1 = imx_uart_readl(sport, USR1);
867 usr2 = imx_uart_readl(sport, USR2);
868 ucr1 = imx_uart_readl(sport, UCR1);
869 ucr2 = imx_uart_readl(sport, UCR2);
870 ucr3 = imx_uart_readl(sport, UCR3);
871 ucr4 = imx_uart_readl(sport, UCR4);
872
873 /*
874 * Even if a condition is true that can trigger an irq only handle it if
875 * the respective irq source is enabled. This prevents some undesired
876 * actions, for example if a character that sits in the RX FIFO and that
877 * should be fetched via DMA is tried to be fetched using PIO. Or the
878 * receiver is currently off and so reading from URXD0 results in an
879 * exception. So just mask the (raw) status bits for disabled irqs.
880 */
881 if ((ucr1 & UCR1_RRDYEN) == 0)
882 usr1 &= ~USR1_RRDY;
883 if ((ucr2 & UCR2_ATEN) == 0)
884 usr1 &= ~USR1_AGTIM;
885 if ((ucr1 & UCR1_TXMPTYEN) == 0)
886 usr1 &= ~USR1_TRDY;
887 if ((ucr4 & UCR4_TCEN) == 0)
888 usr2 &= ~USR2_TXDC;
889 if ((ucr3 & UCR3_DTRDEN) == 0)
890 usr1 &= ~USR1_DTRD;
891 if ((ucr1 & UCR1_RTSDEN) == 0)
892 usr1 &= ~USR1_RTSD;
893 if ((ucr3 & UCR3_AWAKEN) == 0)
894 usr1 &= ~USR1_AWAKE;
895 if ((ucr4 & UCR4_OREN) == 0)
896 usr2 &= ~USR2_ORE;
897
898 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
899 imx_uart_rxint(irq, dev_id);
900 ret = IRQ_HANDLED;
901 }
902
903 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
904 imx_uart_txint(irq, dev_id);
905 ret = IRQ_HANDLED;
906 }
907
908 if (usr1 & USR1_DTRD) {
909 unsigned long flags;
910
911 imx_uart_writel(sport, USR1_DTRD, USR1);
912
913 spin_lock_irqsave(&sport->port.lock, flags);
914 imx_uart_mctrl_check(sport);
915 spin_unlock_irqrestore(&sport->port.lock, flags);
916
917 ret = IRQ_HANDLED;
918 }
919
920 if (usr1 & USR1_RTSD) {
921 imx_uart_rtsint(irq, dev_id);
922 ret = IRQ_HANDLED;
923 }
924
925 if (usr1 & USR1_AWAKE) {
926 imx_uart_writel(sport, USR1_AWAKE, USR1);
927 ret = IRQ_HANDLED;
928 }
929
930 if (usr2 & USR2_ORE) {
931 sport->port.icount.overrun++;
932 imx_uart_writel(sport, USR2_ORE, USR2);
933 ret = IRQ_HANDLED;
934 }
935
936 return ret;
937 }
938
939 /*
940 * Return TIOCSER_TEMT when transmitter is not busy.
941 */
942 static unsigned int imx_uart_tx_empty(struct uart_port *port)
943 {
944 struct imx_port *sport = (struct imx_port *)port;
945 unsigned int ret;
946
947 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
948
949 /* If the TX DMA is working, return 0. */
950 if (sport->dma_is_txing)
951 ret = 0;
952
953 return ret;
954 }
955
956 /* called with port.lock taken and irqs off */
957 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
958 {
959 struct imx_port *sport = (struct imx_port *)port;
960 unsigned int ret = imx_uart_get_hwmctrl(sport);
961
962 mctrl_gpio_get(sport->gpios, &ret);
963
964 return ret;
965 }
966
967 /* called with port.lock taken and irqs off */
968 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
969 {
970 struct imx_port *sport = (struct imx_port *)port;
971 u32 ucr3, uts;
972
973 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
974 u32 ucr2;
975
976 ucr2 = imx_uart_readl(sport, UCR2);
977 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
978 if (mctrl & TIOCM_RTS)
979 ucr2 |= UCR2_CTS | UCR2_CTSC;
980 imx_uart_writel(sport, ucr2, UCR2);
981 }
982
983 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
984 if (!(mctrl & TIOCM_DTR))
985 ucr3 |= UCR3_DSR;
986 imx_uart_writel(sport, ucr3, UCR3);
987
988 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
989 if (mctrl & TIOCM_LOOP)
990 uts |= UTS_LOOP;
991 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
992
993 mctrl_gpio_set(sport->gpios, mctrl);
994 }
995
996 /*
997 * Interrupts always disabled.
998 */
999 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1000 {
1001 struct imx_port *sport = (struct imx_port *)port;
1002 unsigned long flags;
1003 u32 ucr1;
1004
1005 spin_lock_irqsave(&sport->port.lock, flags);
1006
1007 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1008
1009 if (break_state != 0)
1010 ucr1 |= UCR1_SNDBRK;
1011
1012 imx_uart_writel(sport, ucr1, UCR1);
1013
1014 spin_unlock_irqrestore(&sport->port.lock, flags);
1015 }
1016
1017 /*
1018 * This is our per-port timeout handler, for checking the
1019 * modem status signals.
1020 */
1021 static void imx_uart_timeout(struct timer_list *t)
1022 {
1023 struct imx_port *sport = from_timer(sport, t, timer);
1024 unsigned long flags;
1025
1026 if (sport->port.state) {
1027 spin_lock_irqsave(&sport->port.lock, flags);
1028 imx_uart_mctrl_check(sport);
1029 spin_unlock_irqrestore(&sport->port.lock, flags);
1030
1031 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1032 }
1033 }
1034
1035 #define RX_BUF_SIZE (PAGE_SIZE)
1036
1037 /*
1038 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1039 * [1] the RX DMA buffer is full.
1040 * [2] the aging timer expires
1041 *
1042 * Condition [2] is triggered when a character has been sitting in the FIFO
1043 * for at least 8 byte durations.
1044 */
1045 static void imx_uart_dma_rx_callback(void *data)
1046 {
1047 struct imx_port *sport = data;
1048 struct dma_chan *chan = sport->dma_chan_rx;
1049 struct scatterlist *sgl = &sport->rx_sgl;
1050 struct tty_port *port = &sport->port.state->port;
1051 struct dma_tx_state state;
1052 struct circ_buf *rx_ring = &sport->rx_ring;
1053 enum dma_status status;
1054 unsigned int w_bytes = 0;
1055 unsigned int r_bytes;
1056 unsigned int bd_size;
1057
1058 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1059
1060 if (status == DMA_ERROR) {
1061 imx_uart_clear_rx_errors(sport);
1062 return;
1063 }
1064
1065 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1066
1067 /*
1068 * The state-residue variable represents the empty space
1069 * relative to the entire buffer. Taking this in consideration
1070 * the head is always calculated base on the buffer total
1071 * length - DMA transaction residue. The UART script from the
1072 * SDMA firmware will jump to the next buffer descriptor,
1073 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1074 * Taking this in consideration the tail is always at the
1075 * beginning of the buffer descriptor that contains the head.
1076 */
1077
1078 /* Calculate the head */
1079 rx_ring->head = sg_dma_len(sgl) - state.residue;
1080
1081 /* Calculate the tail. */
1082 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1083 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1084
1085 if (rx_ring->head <= sg_dma_len(sgl) &&
1086 rx_ring->head > rx_ring->tail) {
1087
1088 /* Move data from tail to head */
1089 r_bytes = rx_ring->head - rx_ring->tail;
1090
1091 /* CPU claims ownership of RX DMA buffer */
1092 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1093 DMA_FROM_DEVICE);
1094
1095 w_bytes = tty_insert_flip_string(port,
1096 sport->rx_buf + rx_ring->tail, r_bytes);
1097
1098 /* UART retrieves ownership of RX DMA buffer */
1099 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1100 DMA_FROM_DEVICE);
1101
1102 if (w_bytes != r_bytes)
1103 sport->port.icount.buf_overrun++;
1104
1105 sport->port.icount.rx += w_bytes;
1106 } else {
1107 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1108 WARN_ON(rx_ring->head <= rx_ring->tail);
1109 }
1110 }
1111
1112 if (w_bytes) {
1113 tty_flip_buffer_push(port);
1114 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1115 }
1116 }
1117
1118 /* RX DMA buffer periods */
1119 #define RX_DMA_PERIODS 4
1120
1121 static int imx_uart_start_rx_dma(struct imx_port *sport)
1122 {
1123 struct scatterlist *sgl = &sport->rx_sgl;
1124 struct dma_chan *chan = sport->dma_chan_rx;
1125 struct device *dev = sport->port.dev;
1126 struct dma_async_tx_descriptor *desc;
1127 int ret;
1128
1129 sport->rx_ring.head = 0;
1130 sport->rx_ring.tail = 0;
1131 sport->rx_periods = RX_DMA_PERIODS;
1132
1133 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1134 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1135 if (ret == 0) {
1136 dev_err(dev, "DMA mapping error for RX.\n");
1137 return -EINVAL;
1138 }
1139
1140 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1141 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1142 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1143
1144 if (!desc) {
1145 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1146 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1147 return -EINVAL;
1148 }
1149 desc->callback = imx_uart_dma_rx_callback;
1150 desc->callback_param = sport;
1151
1152 dev_dbg(dev, "RX: prepare for the DMA.\n");
1153 sport->dma_is_rxing = 1;
1154 sport->rx_cookie = dmaengine_submit(desc);
1155 dma_async_issue_pending(chan);
1156 return 0;
1157 }
1158
1159 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1160 {
1161 struct tty_port *port = &sport->port.state->port;
1162 u32 usr1, usr2;
1163
1164 usr1 = imx_uart_readl(sport, USR1);
1165 usr2 = imx_uart_readl(sport, USR2);
1166
1167 if (usr2 & USR2_BRCD) {
1168 sport->port.icount.brk++;
1169 imx_uart_writel(sport, USR2_BRCD, USR2);
1170 uart_handle_break(&sport->port);
1171 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1172 sport->port.icount.buf_overrun++;
1173 tty_flip_buffer_push(port);
1174 } else {
1175 dev_err(sport->port.dev, "DMA transaction error.\n");
1176 if (usr1 & USR1_FRAMERR) {
1177 sport->port.icount.frame++;
1178 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1179 } else if (usr1 & USR1_PARITYERR) {
1180 sport->port.icount.parity++;
1181 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1182 }
1183 }
1184
1185 if (usr2 & USR2_ORE) {
1186 sport->port.icount.overrun++;
1187 imx_uart_writel(sport, USR2_ORE, USR2);
1188 }
1189
1190 }
1191
1192 #define TXTL_DEFAULT 2 /* reset default */
1193 #define RXTL_DEFAULT 1 /* reset default */
1194 #define TXTL_DMA 8 /* DMA burst setting */
1195 #define RXTL_DMA 9 /* DMA burst setting */
1196
1197 static void imx_uart_setup_ufcr(struct imx_port *sport,
1198 unsigned char txwl, unsigned char rxwl)
1199 {
1200 unsigned int val;
1201
1202 /* set receiver / transmitter trigger level */
1203 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1204 val |= txwl << UFCR_TXTL_SHF | rxwl;
1205 imx_uart_writel(sport, val, UFCR);
1206 }
1207
1208 static void imx_uart_dma_exit(struct imx_port *sport)
1209 {
1210 if (sport->dma_chan_rx) {
1211 dmaengine_terminate_sync(sport->dma_chan_rx);
1212 dma_release_channel(sport->dma_chan_rx);
1213 sport->dma_chan_rx = NULL;
1214 sport->rx_cookie = -EINVAL;
1215 kfree(sport->rx_buf);
1216 sport->rx_buf = NULL;
1217 }
1218
1219 if (sport->dma_chan_tx) {
1220 dmaengine_terminate_sync(sport->dma_chan_tx);
1221 dma_release_channel(sport->dma_chan_tx);
1222 sport->dma_chan_tx = NULL;
1223 }
1224 }
1225
1226 static int imx_uart_dma_init(struct imx_port *sport)
1227 {
1228 struct dma_slave_config slave_config = {};
1229 struct device *dev = sport->port.dev;
1230 int ret;
1231
1232 /* Prepare for RX : */
1233 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1234 if (!sport->dma_chan_rx) {
1235 dev_dbg(dev, "cannot get the DMA channel.\n");
1236 ret = -EINVAL;
1237 goto err;
1238 }
1239
1240 slave_config.direction = DMA_DEV_TO_MEM;
1241 slave_config.src_addr = sport->port.mapbase + URXD0;
1242 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1243 /* one byte less than the watermark level to enable the aging timer */
1244 slave_config.src_maxburst = RXTL_DMA - 1;
1245 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1246 if (ret) {
1247 dev_err(dev, "error in RX dma configuration.\n");
1248 goto err;
1249 }
1250
1251 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1252 if (!sport->rx_buf) {
1253 ret = -ENOMEM;
1254 goto err;
1255 }
1256 sport->rx_ring.buf = sport->rx_buf;
1257
1258 /* Prepare for TX : */
1259 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1260 if (!sport->dma_chan_tx) {
1261 dev_err(dev, "cannot get the TX DMA channel!\n");
1262 ret = -EINVAL;
1263 goto err;
1264 }
1265
1266 slave_config.direction = DMA_MEM_TO_DEV;
1267 slave_config.dst_addr = sport->port.mapbase + URTX0;
1268 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1269 slave_config.dst_maxburst = TXTL_DMA;
1270 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1271 if (ret) {
1272 dev_err(dev, "error in TX dma configuration.");
1273 goto err;
1274 }
1275
1276 return 0;
1277 err:
1278 imx_uart_dma_exit(sport);
1279 return ret;
1280 }
1281
1282 static void imx_uart_enable_dma(struct imx_port *sport)
1283 {
1284 u32 ucr1;
1285
1286 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1287
1288 /* set UCR1 */
1289 ucr1 = imx_uart_readl(sport, UCR1);
1290 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1291 imx_uart_writel(sport, ucr1, UCR1);
1292
1293 sport->dma_is_enabled = 1;
1294 }
1295
1296 static void imx_uart_disable_dma(struct imx_port *sport)
1297 {
1298 u32 ucr1;
1299
1300 /* clear UCR1 */
1301 ucr1 = imx_uart_readl(sport, UCR1);
1302 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1303 imx_uart_writel(sport, ucr1, UCR1);
1304
1305 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1306
1307 sport->dma_is_enabled = 0;
1308 }
1309
1310 /* half the RX buffer size */
1311 #define CTSTL 16
1312
1313 static int imx_uart_startup(struct uart_port *port)
1314 {
1315 struct imx_port *sport = (struct imx_port *)port;
1316 int retval, i;
1317 unsigned long flags;
1318 int dma_is_inited = 0;
1319 u32 ucr1, ucr2, ucr4;
1320
1321 retval = clk_prepare_enable(sport->clk_per);
1322 if (retval)
1323 return retval;
1324 retval = clk_prepare_enable(sport->clk_ipg);
1325 if (retval) {
1326 clk_disable_unprepare(sport->clk_per);
1327 return retval;
1328 }
1329
1330 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1331
1332 /* disable the DREN bit (Data Ready interrupt enable) before
1333 * requesting IRQs
1334 */
1335 ucr4 = imx_uart_readl(sport, UCR4);
1336
1337 /* set the trigger level for CTS */
1338 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1339 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1340
1341 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1342
1343 /* Can we enable the DMA support? */
1344 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1345 dma_is_inited = 1;
1346
1347 spin_lock_irqsave(&sport->port.lock, flags);
1348 /* Reset fifo's and state machines */
1349 i = 100;
1350
1351 ucr2 = imx_uart_readl(sport, UCR2);
1352 ucr2 &= ~UCR2_SRST;
1353 imx_uart_writel(sport, ucr2, UCR2);
1354
1355 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1356 udelay(1);
1357
1358 /*
1359 * Finally, clear and enable interrupts
1360 */
1361 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1362 imx_uart_writel(sport, USR2_ORE, USR2);
1363
1364 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1365 ucr1 |= UCR1_UARTEN;
1366 if (sport->have_rtscts)
1367 ucr1 |= UCR1_RTSDEN;
1368
1369 imx_uart_writel(sport, ucr1, UCR1);
1370
1371 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1372 if (!sport->dma_is_enabled)
1373 ucr4 |= UCR4_OREN;
1374 imx_uart_writel(sport, ucr4, UCR4);
1375
1376 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1377 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1378 if (!sport->have_rtscts)
1379 ucr2 |= UCR2_IRTS;
1380 /*
1381 * make sure the edge sensitive RTS-irq is disabled,
1382 * we're using RTSD instead.
1383 */
1384 if (!imx_uart_is_imx1(sport))
1385 ucr2 &= ~UCR2_RTSEN;
1386 imx_uart_writel(sport, ucr2, UCR2);
1387
1388 if (!imx_uart_is_imx1(sport)) {
1389 u32 ucr3;
1390
1391 ucr3 = imx_uart_readl(sport, UCR3);
1392
1393 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1394
1395 if (sport->dte_mode)
1396 /* disable broken interrupts */
1397 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1398
1399 imx_uart_writel(sport, ucr3, UCR3);
1400 }
1401
1402 /*
1403 * Enable modem status interrupts
1404 */
1405 imx_uart_enable_ms(&sport->port);
1406
1407 if (dma_is_inited) {
1408 imx_uart_enable_dma(sport);
1409 imx_uart_start_rx_dma(sport);
1410 } else {
1411 ucr1 = imx_uart_readl(sport, UCR1);
1412 ucr1 |= UCR1_RRDYEN;
1413 imx_uart_writel(sport, ucr1, UCR1);
1414
1415 ucr2 = imx_uart_readl(sport, UCR2);
1416 ucr2 |= UCR2_ATEN;
1417 imx_uart_writel(sport, ucr2, UCR2);
1418 }
1419
1420 spin_unlock_irqrestore(&sport->port.lock, flags);
1421
1422 return 0;
1423 }
1424
1425 static void imx_uart_shutdown(struct uart_port *port)
1426 {
1427 struct imx_port *sport = (struct imx_port *)port;
1428 unsigned long flags;
1429 u32 ucr1, ucr2, ucr4;
1430
1431 if (sport->dma_is_enabled) {
1432 dmaengine_terminate_sync(sport->dma_chan_tx);
1433 if (sport->dma_is_txing) {
1434 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1435 sport->dma_tx_nents, DMA_TO_DEVICE);
1436 sport->dma_is_txing = 0;
1437 }
1438 dmaengine_terminate_sync(sport->dma_chan_rx);
1439 if (sport->dma_is_rxing) {
1440 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1441 1, DMA_FROM_DEVICE);
1442 sport->dma_is_rxing = 0;
1443 }
1444
1445 spin_lock_irqsave(&sport->port.lock, flags);
1446 imx_uart_stop_tx(port);
1447 imx_uart_stop_rx(port);
1448 imx_uart_disable_dma(sport);
1449 spin_unlock_irqrestore(&sport->port.lock, flags);
1450 imx_uart_dma_exit(sport);
1451 }
1452
1453 mctrl_gpio_disable_ms(sport->gpios);
1454
1455 spin_lock_irqsave(&sport->port.lock, flags);
1456 ucr2 = imx_uart_readl(sport, UCR2);
1457 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1458 imx_uart_writel(sport, ucr2, UCR2);
1459
1460 ucr4 = imx_uart_readl(sport, UCR4);
1461 ucr4 &= ~UCR4_OREN;
1462 imx_uart_writel(sport, ucr4, UCR4);
1463 spin_unlock_irqrestore(&sport->port.lock, flags);
1464
1465 /*
1466 * Stop our timer.
1467 */
1468 del_timer_sync(&sport->timer);
1469
1470 /*
1471 * Disable all interrupts, port and break condition.
1472 */
1473
1474 spin_lock_irqsave(&sport->port.lock, flags);
1475 ucr1 = imx_uart_readl(sport, UCR1);
1476 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1477
1478 imx_uart_writel(sport, ucr1, UCR1);
1479 spin_unlock_irqrestore(&sport->port.lock, flags);
1480
1481 clk_disable_unprepare(sport->clk_per);
1482 clk_disable_unprepare(sport->clk_ipg);
1483 }
1484
1485 /* called with port.lock taken and irqs off */
1486 static void imx_uart_flush_buffer(struct uart_port *port)
1487 {
1488 struct imx_port *sport = (struct imx_port *)port;
1489 struct scatterlist *sgl = &sport->tx_sgl[0];
1490 u32 ucr2;
1491 int i = 100, ubir, ubmr, uts;
1492
1493 if (!sport->dma_chan_tx)
1494 return;
1495
1496 sport->tx_bytes = 0;
1497 dmaengine_terminate_all(sport->dma_chan_tx);
1498 if (sport->dma_is_txing) {
1499 u32 ucr1;
1500
1501 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1502 DMA_TO_DEVICE);
1503 ucr1 = imx_uart_readl(sport, UCR1);
1504 ucr1 &= ~UCR1_TXDMAEN;
1505 imx_uart_writel(sport, ucr1, UCR1);
1506 sport->dma_is_txing = 0;
1507 }
1508
1509 /*
1510 * According to the Reference Manual description of the UART SRST bit:
1511 *
1512 * "Reset the transmit and receive state machines,
1513 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1514 * and UTS[6-3]".
1515 *
1516 * We don't need to restore the old values from USR1, USR2, URXD and
1517 * UTXD. UBRC is read only, so only save/restore the other three
1518 * registers.
1519 */
1520 ubir = imx_uart_readl(sport, UBIR);
1521 ubmr = imx_uart_readl(sport, UBMR);
1522 uts = imx_uart_readl(sport, IMX21_UTS);
1523
1524 ucr2 = imx_uart_readl(sport, UCR2);
1525 ucr2 &= ~UCR2_SRST;
1526 imx_uart_writel(sport, ucr2, UCR2);
1527
1528 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1529 udelay(1);
1530
1531 /* Restore the registers */
1532 imx_uart_writel(sport, ubir, UBIR);
1533 imx_uart_writel(sport, ubmr, UBMR);
1534 imx_uart_writel(sport, uts, IMX21_UTS);
1535 }
1536
1537 static void
1538 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1539 struct ktermios *old)
1540 {
1541 struct imx_port *sport = (struct imx_port *)port;
1542 unsigned long flags;
1543 u32 ucr2, old_ucr1, old_ucr2, ufcr;
1544 unsigned int baud, quot;
1545 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1546 unsigned long div;
1547 unsigned long num, denom;
1548 uint64_t tdiv64;
1549
1550 /*
1551 * We only support CS7 and CS8.
1552 */
1553 while ((termios->c_cflag & CSIZE) != CS7 &&
1554 (termios->c_cflag & CSIZE) != CS8) {
1555 termios->c_cflag &= ~CSIZE;
1556 termios->c_cflag |= old_csize;
1557 old_csize = CS8;
1558 }
1559
1560 del_timer_sync(&sport->timer);
1561
1562 /*
1563 * Ask the core to calculate the divisor for us.
1564 */
1565 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1566 quot = uart_get_divisor(port, baud);
1567
1568 spin_lock_irqsave(&sport->port.lock, flags);
1569
1570 if ((termios->c_cflag & CSIZE) == CS8)
1571 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1572 else
1573 ucr2 = UCR2_SRST | UCR2_IRTS;
1574
1575 if (termios->c_cflag & CRTSCTS) {
1576 if (sport->have_rtscts) {
1577 ucr2 &= ~UCR2_IRTS;
1578
1579 if (port->rs485.flags & SER_RS485_ENABLED) {
1580 /*
1581 * RTS is mandatory for rs485 operation, so keep
1582 * it under manual control and keep transmitter
1583 * disabled.
1584 */
1585 if (port->rs485.flags &
1586 SER_RS485_RTS_AFTER_SEND)
1587 imx_uart_rts_active(sport, &ucr2);
1588 else
1589 imx_uart_rts_inactive(sport, &ucr2);
1590 } else {
1591 imx_uart_rts_auto(sport, &ucr2);
1592 }
1593 } else {
1594 termios->c_cflag &= ~CRTSCTS;
1595 }
1596 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1597 /* disable transmitter */
1598 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1599 imx_uart_rts_active(sport, &ucr2);
1600 else
1601 imx_uart_rts_inactive(sport, &ucr2);
1602 }
1603
1604
1605 if (termios->c_cflag & CSTOPB)
1606 ucr2 |= UCR2_STPB;
1607 if (termios->c_cflag & PARENB) {
1608 ucr2 |= UCR2_PREN;
1609 if (termios->c_cflag & PARODD)
1610 ucr2 |= UCR2_PROE;
1611 }
1612
1613 sport->port.read_status_mask = 0;
1614 if (termios->c_iflag & INPCK)
1615 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1616 if (termios->c_iflag & (BRKINT | PARMRK))
1617 sport->port.read_status_mask |= URXD_BRK;
1618
1619 /*
1620 * Characters to ignore
1621 */
1622 sport->port.ignore_status_mask = 0;
1623 if (termios->c_iflag & IGNPAR)
1624 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1625 if (termios->c_iflag & IGNBRK) {
1626 sport->port.ignore_status_mask |= URXD_BRK;
1627 /*
1628 * If we're ignoring parity and break indicators,
1629 * ignore overruns too (for real raw support).
1630 */
1631 if (termios->c_iflag & IGNPAR)
1632 sport->port.ignore_status_mask |= URXD_OVRRUN;
1633 }
1634
1635 if ((termios->c_cflag & CREAD) == 0)
1636 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1637
1638 /*
1639 * Update the per-port timeout.
1640 */
1641 uart_update_timeout(port, termios->c_cflag, baud);
1642
1643 /*
1644 * disable interrupts and drain transmitter
1645 */
1646 old_ucr1 = imx_uart_readl(sport, UCR1);
1647 imx_uart_writel(sport,
1648 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1649 UCR1);
1650 old_ucr2 = imx_uart_readl(sport, UCR2);
1651 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1652
1653 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
1654 barrier();
1655
1656 /* then, disable everything */
1657 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2);
1658 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1659
1660 /* custom-baudrate handling */
1661 div = sport->port.uartclk / (baud * 16);
1662 if (baud == 38400 && quot != div)
1663 baud = sport->port.uartclk / (quot * 16);
1664
1665 div = sport->port.uartclk / (baud * 16);
1666 if (div > 7)
1667 div = 7;
1668 if (!div)
1669 div = 1;
1670
1671 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1672 1 << 16, 1 << 16, &num, &denom);
1673
1674 tdiv64 = sport->port.uartclk;
1675 tdiv64 *= num;
1676 do_div(tdiv64, denom * 16 * div);
1677 tty_termios_encode_baud_rate(termios,
1678 (speed_t)tdiv64, (speed_t)tdiv64);
1679
1680 num -= 1;
1681 denom -= 1;
1682
1683 ufcr = imx_uart_readl(sport, UFCR);
1684 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1685 imx_uart_writel(sport, ufcr, UFCR);
1686
1687 imx_uart_writel(sport, num, UBIR);
1688 imx_uart_writel(sport, denom, UBMR);
1689
1690 if (!imx_uart_is_imx1(sport))
1691 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1692 IMX21_ONEMS);
1693
1694 imx_uart_writel(sport, old_ucr1, UCR1);
1695
1696 /* set the parity, stop bits and data size */
1697 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2);
1698
1699 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1700 imx_uart_enable_ms(&sport->port);
1701
1702 spin_unlock_irqrestore(&sport->port.lock, flags);
1703 }
1704
1705 static const char *imx_uart_type(struct uart_port *port)
1706 {
1707 struct imx_port *sport = (struct imx_port *)port;
1708
1709 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1710 }
1711
1712 /*
1713 * Configure/autoconfigure the port.
1714 */
1715 static void imx_uart_config_port(struct uart_port *port, int flags)
1716 {
1717 struct imx_port *sport = (struct imx_port *)port;
1718
1719 if (flags & UART_CONFIG_TYPE)
1720 sport->port.type = PORT_IMX;
1721 }
1722
1723 /*
1724 * Verify the new serial_struct (for TIOCSSERIAL).
1725 * The only change we allow are to the flags and type, and
1726 * even then only between PORT_IMX and PORT_UNKNOWN
1727 */
1728 static int
1729 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1730 {
1731 struct imx_port *sport = (struct imx_port *)port;
1732 int ret = 0;
1733
1734 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1735 ret = -EINVAL;
1736 if (sport->port.irq != ser->irq)
1737 ret = -EINVAL;
1738 if (ser->io_type != UPIO_MEM)
1739 ret = -EINVAL;
1740 if (sport->port.uartclk / 16 != ser->baud_base)
1741 ret = -EINVAL;
1742 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1743 ret = -EINVAL;
1744 if (sport->port.iobase != ser->port)
1745 ret = -EINVAL;
1746 if (ser->hub6 != 0)
1747 ret = -EINVAL;
1748 return ret;
1749 }
1750
1751 #if defined(CONFIG_CONSOLE_POLL)
1752
1753 static int imx_uart_poll_init(struct uart_port *port)
1754 {
1755 struct imx_port *sport = (struct imx_port *)port;
1756 unsigned long flags;
1757 u32 ucr1, ucr2;
1758 int retval;
1759
1760 retval = clk_prepare_enable(sport->clk_ipg);
1761 if (retval)
1762 return retval;
1763 retval = clk_prepare_enable(sport->clk_per);
1764 if (retval)
1765 clk_disable_unprepare(sport->clk_ipg);
1766
1767 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1768
1769 spin_lock_irqsave(&sport->port.lock, flags);
1770
1771 /*
1772 * Be careful about the order of enabling bits here. First enable the
1773 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1774 * This prevents that a character that already sits in the RX fifo is
1775 * triggering an irq but the try to fetch it from there results in an
1776 * exception because UARTEN or RXEN is still off.
1777 */
1778 ucr1 = imx_uart_readl(sport, UCR1);
1779 ucr2 = imx_uart_readl(sport, UCR2);
1780
1781 if (imx_uart_is_imx1(sport))
1782 ucr1 |= IMX1_UCR1_UARTCLKEN;
1783
1784 ucr1 |= UCR1_UARTEN;
1785 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1786
1787 ucr2 |= UCR2_RXEN;
1788 ucr2 &= ~UCR2_ATEN;
1789
1790 imx_uart_writel(sport, ucr1, UCR1);
1791 imx_uart_writel(sport, ucr2, UCR2);
1792
1793 /* now enable irqs */
1794 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1795 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1796
1797 spin_unlock_irqrestore(&sport->port.lock, flags);
1798
1799 return 0;
1800 }
1801
1802 static int imx_uart_poll_get_char(struct uart_port *port)
1803 {
1804 struct imx_port *sport = (struct imx_port *)port;
1805 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1806 return NO_POLL_CHAR;
1807
1808 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1809 }
1810
1811 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1812 {
1813 struct imx_port *sport = (struct imx_port *)port;
1814 unsigned int status;
1815
1816 /* drain */
1817 do {
1818 status = imx_uart_readl(sport, USR1);
1819 } while (~status & USR1_TRDY);
1820
1821 /* write */
1822 imx_uart_writel(sport, c, URTX0);
1823
1824 /* flush */
1825 do {
1826 status = imx_uart_readl(sport, USR2);
1827 } while (~status & USR2_TXDC);
1828 }
1829 #endif
1830
1831 /* called with port.lock taken and irqs off or from .probe without locking */
1832 static int imx_uart_rs485_config(struct uart_port *port,
1833 struct serial_rs485 *rs485conf)
1834 {
1835 struct imx_port *sport = (struct imx_port *)port;
1836 u32 ucr2;
1837
1838 /* unimplemented */
1839 rs485conf->delay_rts_before_send = 0;
1840 rs485conf->delay_rts_after_send = 0;
1841
1842 /* RTS is required to control the transmitter */
1843 if (!sport->have_rtscts && !sport->have_rtsgpio)
1844 rs485conf->flags &= ~SER_RS485_ENABLED;
1845
1846 if (rs485conf->flags & SER_RS485_ENABLED) {
1847 /* Enable receiver if low-active RTS signal is requested */
1848 if (sport->have_rtscts && !sport->have_rtsgpio &&
1849 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1850 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1851
1852 /* disable transmitter */
1853 ucr2 = imx_uart_readl(sport, UCR2);
1854 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1855 imx_uart_rts_active(sport, &ucr2);
1856 else
1857 imx_uart_rts_inactive(sport, &ucr2);
1858 imx_uart_writel(sport, ucr2, UCR2);
1859 }
1860
1861 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1862 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1863 rs485conf->flags & SER_RS485_RX_DURING_TX)
1864 imx_uart_start_rx(port);
1865
1866 port->rs485 = *rs485conf;
1867
1868 return 0;
1869 }
1870
1871 static const struct uart_ops imx_uart_pops = {
1872 .tx_empty = imx_uart_tx_empty,
1873 .set_mctrl = imx_uart_set_mctrl,
1874 .get_mctrl = imx_uart_get_mctrl,
1875 .stop_tx = imx_uart_stop_tx,
1876 .start_tx = imx_uart_start_tx,
1877 .stop_rx = imx_uart_stop_rx,
1878 .enable_ms = imx_uart_enable_ms,
1879 .break_ctl = imx_uart_break_ctl,
1880 .startup = imx_uart_startup,
1881 .shutdown = imx_uart_shutdown,
1882 .flush_buffer = imx_uart_flush_buffer,
1883 .set_termios = imx_uart_set_termios,
1884 .type = imx_uart_type,
1885 .config_port = imx_uart_config_port,
1886 .verify_port = imx_uart_verify_port,
1887 #if defined(CONFIG_CONSOLE_POLL)
1888 .poll_init = imx_uart_poll_init,
1889 .poll_get_char = imx_uart_poll_get_char,
1890 .poll_put_char = imx_uart_poll_put_char,
1891 #endif
1892 };
1893
1894 static struct imx_port *imx_uart_ports[UART_NR];
1895
1896 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1897 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1898 {
1899 struct imx_port *sport = (struct imx_port *)port;
1900
1901 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1902 barrier();
1903
1904 imx_uart_writel(sport, ch, URTX0);
1905 }
1906
1907 /*
1908 * Interrupts are disabled on entering
1909 */
1910 static void
1911 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1912 {
1913 struct imx_port *sport = imx_uart_ports[co->index];
1914 struct imx_port_ucrs old_ucr;
1915 unsigned int ucr1;
1916 unsigned long flags = 0;
1917 int locked = 1;
1918 int retval;
1919
1920 retval = clk_enable(sport->clk_per);
1921 if (retval)
1922 return;
1923 retval = clk_enable(sport->clk_ipg);
1924 if (retval) {
1925 clk_disable(sport->clk_per);
1926 return;
1927 }
1928
1929 if (sport->port.sysrq)
1930 locked = 0;
1931 else if (oops_in_progress)
1932 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1933 else
1934 spin_lock_irqsave(&sport->port.lock, flags);
1935
1936 /*
1937 * First, save UCR1/2/3 and then disable interrupts
1938 */
1939 imx_uart_ucrs_save(sport, &old_ucr);
1940 ucr1 = old_ucr.ucr1;
1941
1942 if (imx_uart_is_imx1(sport))
1943 ucr1 |= IMX1_UCR1_UARTCLKEN;
1944 ucr1 |= UCR1_UARTEN;
1945 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1946
1947 imx_uart_writel(sport, ucr1, UCR1);
1948
1949 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1950
1951 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1952
1953 /*
1954 * Finally, wait for transmitter to become empty
1955 * and restore UCR1/2/3
1956 */
1957 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1958
1959 imx_uart_ucrs_restore(sport, &old_ucr);
1960
1961 if (locked)
1962 spin_unlock_irqrestore(&sport->port.lock, flags);
1963
1964 clk_disable(sport->clk_ipg);
1965 clk_disable(sport->clk_per);
1966 }
1967
1968 /*
1969 * If the port was already initialised (eg, by a boot loader),
1970 * try to determine the current setup.
1971 */
1972 static void __init
1973 imx_uart_console_get_options(struct imx_port *sport, int *baud,
1974 int *parity, int *bits)
1975 {
1976
1977 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1978 /* ok, the port was enabled */
1979 unsigned int ucr2, ubir, ubmr, uartclk;
1980 unsigned int baud_raw;
1981 unsigned int ucfr_rfdiv;
1982
1983 ucr2 = imx_uart_readl(sport, UCR2);
1984
1985 *parity = 'n';
1986 if (ucr2 & UCR2_PREN) {
1987 if (ucr2 & UCR2_PROE)
1988 *parity = 'o';
1989 else
1990 *parity = 'e';
1991 }
1992
1993 if (ucr2 & UCR2_WS)
1994 *bits = 8;
1995 else
1996 *bits = 7;
1997
1998 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
1999 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2000
2001 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2002 if (ucfr_rfdiv == 6)
2003 ucfr_rfdiv = 7;
2004 else
2005 ucfr_rfdiv = 6 - ucfr_rfdiv;
2006
2007 uartclk = clk_get_rate(sport->clk_per);
2008 uartclk /= ucfr_rfdiv;
2009
2010 { /*
2011 * The next code provides exact computation of
2012 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2013 * without need of float support or long long division,
2014 * which would be required to prevent 32bit arithmetic overflow
2015 */
2016 unsigned int mul = ubir + 1;
2017 unsigned int div = 16 * (ubmr + 1);
2018 unsigned int rem = uartclk % div;
2019
2020 baud_raw = (uartclk / div) * mul;
2021 baud_raw += (rem * mul + div / 2) / div;
2022 *baud = (baud_raw + 50) / 100 * 100;
2023 }
2024
2025 if (*baud != baud_raw)
2026 pr_info("Console IMX rounded baud rate from %d to %d\n",
2027 baud_raw, *baud);
2028 }
2029 }
2030
2031 static int __init
2032 imx_uart_console_setup(struct console *co, char *options)
2033 {
2034 struct imx_port *sport;
2035 int baud = 9600;
2036 int bits = 8;
2037 int parity = 'n';
2038 int flow = 'n';
2039 int retval;
2040
2041 /*
2042 * Check whether an invalid uart number has been specified, and
2043 * if so, search for the first available port that does have
2044 * console support.
2045 */
2046 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2047 co->index = 0;
2048 sport = imx_uart_ports[co->index];
2049 if (sport == NULL)
2050 return -ENODEV;
2051
2052 /* For setting the registers, we only need to enable the ipg clock. */
2053 retval = clk_prepare_enable(sport->clk_ipg);
2054 if (retval)
2055 goto error_console;
2056
2057 if (options)
2058 uart_parse_options(options, &baud, &parity, &bits, &flow);
2059 else
2060 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2061
2062 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2063
2064 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2065
2066 clk_disable(sport->clk_ipg);
2067 if (retval) {
2068 clk_unprepare(sport->clk_ipg);
2069 goto error_console;
2070 }
2071
2072 retval = clk_prepare(sport->clk_per);
2073 if (retval)
2074 clk_unprepare(sport->clk_ipg);
2075
2076 error_console:
2077 return retval;
2078 }
2079
2080 static struct uart_driver imx_uart_uart_driver;
2081 static struct console imx_uart_console = {
2082 .name = DEV_NAME,
2083 .write = imx_uart_console_write,
2084 .device = uart_console_device,
2085 .setup = imx_uart_console_setup,
2086 .flags = CON_PRINTBUFFER,
2087 .index = -1,
2088 .data = &imx_uart_uart_driver,
2089 };
2090
2091 #define IMX_CONSOLE &imx_uart_console
2092
2093 #ifdef CONFIG_OF
2094 static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2095 {
2096 struct imx_port *sport = (struct imx_port *)port;
2097
2098 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2099 cpu_relax();
2100
2101 imx_uart_writel(sport, ch, URTX0);
2102 }
2103
2104 static void imx_uart_console_early_write(struct console *con, const char *s,
2105 unsigned count)
2106 {
2107 struct earlycon_device *dev = con->data;
2108
2109 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2110 }
2111
2112 static int __init
2113 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2114 {
2115 if (!dev->port.membase)
2116 return -ENODEV;
2117
2118 dev->con->write = imx_uart_console_early_write;
2119
2120 return 0;
2121 }
2122 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2123 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2124 #endif
2125
2126 #else
2127 #define IMX_CONSOLE NULL
2128 #endif
2129
2130 static struct uart_driver imx_uart_uart_driver = {
2131 .owner = THIS_MODULE,
2132 .driver_name = DRIVER_NAME,
2133 .dev_name = DEV_NAME,
2134 .major = SERIAL_IMX_MAJOR,
2135 .minor = MINOR_START,
2136 .nr = ARRAY_SIZE(imx_uart_ports),
2137 .cons = IMX_CONSOLE,
2138 };
2139
2140 #ifdef CONFIG_OF
2141 /*
2142 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2143 * could successfully get all information from dt or a negative errno.
2144 */
2145 static int imx_uart_probe_dt(struct imx_port *sport,
2146 struct platform_device *pdev)
2147 {
2148 struct device_node *np = pdev->dev.of_node;
2149 int ret;
2150
2151 sport->devdata = of_device_get_match_data(&pdev->dev);
2152 if (!sport->devdata)
2153 /* no device tree device */
2154 return 1;
2155
2156 ret = of_alias_get_id(np, "serial");
2157 if (ret < 0) {
2158 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2159 return ret;
2160 }
2161 sport->port.line = ret;
2162
2163 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2164 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2165 sport->have_rtscts = 1;
2166
2167 if (of_get_property(np, "fsl,dte-mode", NULL))
2168 sport->dte_mode = 1;
2169
2170 if (of_get_property(np, "rts-gpios", NULL))
2171 sport->have_rtsgpio = 1;
2172
2173 return 0;
2174 }
2175 #else
2176 static inline int imx_uart_probe_dt(struct imx_port *sport,
2177 struct platform_device *pdev)
2178 {
2179 return 1;
2180 }
2181 #endif
2182
2183 static void imx_uart_probe_pdata(struct imx_port *sport,
2184 struct platform_device *pdev)
2185 {
2186 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2187
2188 sport->port.line = pdev->id;
2189 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2190
2191 if (!pdata)
2192 return;
2193
2194 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2195 sport->have_rtscts = 1;
2196 }
2197
2198 static int imx_uart_probe(struct platform_device *pdev)
2199 {
2200 struct imx_port *sport;
2201 void __iomem *base;
2202 int ret = 0;
2203 u32 ucr1;
2204 struct resource *res;
2205 int txirq, rxirq, rtsirq;
2206
2207 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2208 if (!sport)
2209 return -ENOMEM;
2210
2211 ret = imx_uart_probe_dt(sport, pdev);
2212 if (ret > 0)
2213 imx_uart_probe_pdata(sport, pdev);
2214 else if (ret < 0)
2215 return ret;
2216
2217 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2218 dev_err(&pdev->dev, "serial%d out of range\n",
2219 sport->port.line);
2220 return -EINVAL;
2221 }
2222
2223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2224 base = devm_ioremap_resource(&pdev->dev, res);
2225 if (IS_ERR(base))
2226 return PTR_ERR(base);
2227
2228 rxirq = platform_get_irq(pdev, 0);
2229 txirq = platform_get_irq(pdev, 1);
2230 rtsirq = platform_get_irq(pdev, 2);
2231
2232 sport->port.dev = &pdev->dev;
2233 sport->port.mapbase = res->start;
2234 sport->port.membase = base;
2235 sport->port.type = PORT_IMX,
2236 sport->port.iotype = UPIO_MEM;
2237 sport->port.irq = rxirq;
2238 sport->port.fifosize = 32;
2239 sport->port.ops = &imx_uart_pops;
2240 sport->port.rs485_config = imx_uart_rs485_config;
2241 sport->port.flags = UPF_BOOT_AUTOCONF;
2242 timer_setup(&sport->timer, imx_uart_timeout, 0);
2243
2244 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2245 if (IS_ERR(sport->gpios))
2246 return PTR_ERR(sport->gpios);
2247
2248 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2249 if (IS_ERR(sport->clk_ipg)) {
2250 ret = PTR_ERR(sport->clk_ipg);
2251 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2252 return ret;
2253 }
2254
2255 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2256 if (IS_ERR(sport->clk_per)) {
2257 ret = PTR_ERR(sport->clk_per);
2258 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2259 return ret;
2260 }
2261
2262 sport->port.uartclk = clk_get_rate(sport->clk_per);
2263
2264 /* For register access, we only need to enable the ipg clock. */
2265 ret = clk_prepare_enable(sport->clk_ipg);
2266 if (ret) {
2267 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2268 return ret;
2269 }
2270
2271 /* initialize shadow register values */
2272 sport->ucr1 = readl(sport->port.membase + UCR1);
2273 sport->ucr2 = readl(sport->port.membase + UCR2);
2274 sport->ucr3 = readl(sport->port.membase + UCR3);
2275 sport->ucr4 = readl(sport->port.membase + UCR4);
2276 sport->ufcr = readl(sport->port.membase + UFCR);
2277
2278 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2279
2280 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2281 (!sport->have_rtscts && !sport->have_rtsgpio))
2282 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2283
2284 /*
2285 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2286 * signal cannot be set low during transmission in case the
2287 * receiver is off (limitation of the i.MX UART IP).
2288 */
2289 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2290 sport->have_rtscts && !sport->have_rtsgpio &&
2291 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2292 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2293 dev_err(&pdev->dev,
2294 "low-active RTS not possible when receiver is off, enabling receiver\n");
2295
2296 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2297
2298 /* Disable interrupts before requesting them */
2299 ucr1 = imx_uart_readl(sport, UCR1);
2300 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2301 UCR1_TXMPTYEN | UCR1_RTSDEN);
2302 imx_uart_writel(sport, ucr1, UCR1);
2303
2304 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2305 /*
2306 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2307 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2308 * and DCD (when they are outputs) or enables the respective
2309 * irqs. So set this bit early, i.e. before requesting irqs.
2310 */
2311 u32 ufcr = imx_uart_readl(sport, UFCR);
2312 if (!(ufcr & UFCR_DCEDTE))
2313 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2314
2315 /*
2316 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2317 * enabled later because they cannot be cleared
2318 * (confirmed on i.MX25) which makes them unusable.
2319 */
2320 imx_uart_writel(sport,
2321 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2322 UCR3);
2323
2324 } else {
2325 u32 ucr3 = UCR3_DSR;
2326 u32 ufcr = imx_uart_readl(sport, UFCR);
2327 if (ufcr & UFCR_DCEDTE)
2328 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2329
2330 if (!imx_uart_is_imx1(sport))
2331 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2332 imx_uart_writel(sport, ucr3, UCR3);
2333 }
2334
2335 clk_disable_unprepare(sport->clk_ipg);
2336
2337 /*
2338 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2339 * chips only have one interrupt.
2340 */
2341 if (txirq > 0) {
2342 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2343 dev_name(&pdev->dev), sport);
2344 if (ret) {
2345 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2346 ret);
2347 return ret;
2348 }
2349
2350 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2351 dev_name(&pdev->dev), sport);
2352 if (ret) {
2353 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2354 ret);
2355 return ret;
2356 }
2357
2358 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2359 dev_name(&pdev->dev), sport);
2360 if (ret) {
2361 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2362 ret);
2363 return ret;
2364 }
2365 } else {
2366 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2367 dev_name(&pdev->dev), sport);
2368 if (ret) {
2369 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2370 return ret;
2371 }
2372 }
2373
2374 imx_uart_ports[sport->port.line] = sport;
2375
2376 platform_set_drvdata(pdev, sport);
2377
2378 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2379 }
2380
2381 static int imx_uart_remove(struct platform_device *pdev)
2382 {
2383 struct imx_port *sport = platform_get_drvdata(pdev);
2384
2385 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2386 }
2387
2388 static void imx_uart_restore_context(struct imx_port *sport)
2389 {
2390 if (!sport->context_saved)
2391 return;
2392
2393 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2394 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2395 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2396 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2397 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2398 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2399 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2400 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2401 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2402 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2403 sport->context_saved = false;
2404 }
2405
2406 static void imx_uart_save_context(struct imx_port *sport)
2407 {
2408 /* Save necessary regs */
2409 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2410 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2411 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2412 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2413 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2414 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2415 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2416 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2417 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2418 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2419 sport->context_saved = true;
2420 }
2421
2422 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2423 {
2424 u32 ucr3;
2425
2426 ucr3 = imx_uart_readl(sport, UCR3);
2427 if (on) {
2428 imx_uart_writel(sport, USR1_AWAKE, USR1);
2429 ucr3 |= UCR3_AWAKEN;
2430 } else {
2431 ucr3 &= ~UCR3_AWAKEN;
2432 }
2433 imx_uart_writel(sport, ucr3, UCR3);
2434
2435 if (sport->have_rtscts) {
2436 u32 ucr1 = imx_uart_readl(sport, UCR1);
2437 if (on)
2438 ucr1 |= UCR1_RTSDEN;
2439 else
2440 ucr1 &= ~UCR1_RTSDEN;
2441 imx_uart_writel(sport, ucr1, UCR1);
2442 }
2443 }
2444
2445 static int imx_uart_suspend_noirq(struct device *dev)
2446 {
2447 struct imx_port *sport = dev_get_drvdata(dev);
2448
2449 imx_uart_save_context(sport);
2450
2451 clk_disable(sport->clk_ipg);
2452
2453 return 0;
2454 }
2455
2456 static int imx_uart_resume_noirq(struct device *dev)
2457 {
2458 struct imx_port *sport = dev_get_drvdata(dev);
2459 int ret;
2460
2461 ret = clk_enable(sport->clk_ipg);
2462 if (ret)
2463 return ret;
2464
2465 imx_uart_restore_context(sport);
2466
2467 return 0;
2468 }
2469
2470 static int imx_uart_suspend(struct device *dev)
2471 {
2472 struct imx_port *sport = dev_get_drvdata(dev);
2473 int ret;
2474
2475 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2476 disable_irq(sport->port.irq);
2477
2478 ret = clk_prepare_enable(sport->clk_ipg);
2479 if (ret)
2480 return ret;
2481
2482 /* enable wakeup from i.MX UART */
2483 imx_uart_enable_wakeup(sport, true);
2484
2485 return 0;
2486 }
2487
2488 static int imx_uart_resume(struct device *dev)
2489 {
2490 struct imx_port *sport = dev_get_drvdata(dev);
2491
2492 /* disable wakeup from i.MX UART */
2493 imx_uart_enable_wakeup(sport, false);
2494
2495 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2496 enable_irq(sport->port.irq);
2497
2498 clk_disable_unprepare(sport->clk_ipg);
2499
2500 return 0;
2501 }
2502
2503 static int imx_uart_freeze(struct device *dev)
2504 {
2505 struct imx_port *sport = dev_get_drvdata(dev);
2506
2507 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2508
2509 return clk_prepare_enable(sport->clk_ipg);
2510 }
2511
2512 static int imx_uart_thaw(struct device *dev)
2513 {
2514 struct imx_port *sport = dev_get_drvdata(dev);
2515
2516 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2517
2518 clk_disable_unprepare(sport->clk_ipg);
2519
2520 return 0;
2521 }
2522
2523 static const struct dev_pm_ops imx_uart_pm_ops = {
2524 .suspend_noirq = imx_uart_suspend_noirq,
2525 .resume_noirq = imx_uart_resume_noirq,
2526 .freeze_noirq = imx_uart_suspend_noirq,
2527 .restore_noirq = imx_uart_resume_noirq,
2528 .suspend = imx_uart_suspend,
2529 .resume = imx_uart_resume,
2530 .freeze = imx_uart_freeze,
2531 .thaw = imx_uart_thaw,
2532 .restore = imx_uart_thaw,
2533 };
2534
2535 static struct platform_driver imx_uart_platform_driver = {
2536 .probe = imx_uart_probe,
2537 .remove = imx_uart_remove,
2538
2539 .id_table = imx_uart_devtype,
2540 .driver = {
2541 .name = "imx-uart",
2542 .of_match_table = imx_uart_dt_ids,
2543 .pm = &imx_uart_pm_ops,
2544 },
2545 };
2546
2547 static int __init imx_uart_init(void)
2548 {
2549 int ret = uart_register_driver(&imx_uart_uart_driver);
2550
2551 if (ret)
2552 return ret;
2553
2554 ret = platform_driver_register(&imx_uart_platform_driver);
2555 if (ret != 0)
2556 uart_unregister_driver(&imx_uart_uart_driver);
2557
2558 return ret;
2559 }
2560
2561 static void __exit imx_uart_exit(void)
2562 {
2563 platform_driver_unregister(&imx_uart_platform_driver);
2564 uart_unregister_driver(&imx_uart_uart_driver);
2565 }
2566
2567 module_init(imx_uart_init);
2568 module_exit(imx_uart_exit);
2569
2570 MODULE_AUTHOR("Sascha Hauer");
2571 MODULE_DESCRIPTION("IMX generic serial port driver");
2572 MODULE_LICENSE("GPL");
2573 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support