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Linux 4.19.133
[linux/fpc-iii.git] / drivers / tty / serial / pch_uart.c
blobe5ff30544bd0d47364bd4ec3cd1c0c1590d7a931
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6 #define SUPPORT_SYSRQ
7 #endif
8 #include <linux/kernel.h>
9 #include <linux/serial_reg.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/console.h>
14 #include <linux/serial_core.h>
15 #include <linux/tty.h>
16 #include <linux/tty_flip.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/dmi.h>
20 #include <linux/nmi.h>
21 #include <linux/delay.h>
22 #include <linux/of.h>
23
24 #include <linux/debugfs.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pch_dma.h>
27
28 enum {
29 PCH_UART_HANDLED_RX_INT_SHIFT,
30 PCH_UART_HANDLED_TX_INT_SHIFT,
31 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
32 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
33 PCH_UART_HANDLED_MS_INT_SHIFT,
34 PCH_UART_HANDLED_LS_INT_SHIFT,
35 };
36
37 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
38
39 /* Set the max number of UART port
40 * Intel EG20T PCH: 4 port
41 * LAPIS Semiconductor ML7213 IOH: 3 port
42 * LAPIS Semiconductor ML7223 IOH: 2 port
43 */
44 #define PCH_UART_NR 4
45
46 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
47 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
48 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
49 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
50 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
51 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
52 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
53
54 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
55
56 #define PCH_UART_RBR 0x00
57 #define PCH_UART_THR 0x00
58
59 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
60 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
61 #define PCH_UART_IER_ERBFI 0x00000001
62 #define PCH_UART_IER_ETBEI 0x00000002
63 #define PCH_UART_IER_ELSI 0x00000004
64 #define PCH_UART_IER_EDSSI 0x00000008
65
66 #define PCH_UART_IIR_IP 0x00000001
67 #define PCH_UART_IIR_IID 0x00000006
68 #define PCH_UART_IIR_MSI 0x00000000
69 #define PCH_UART_IIR_TRI 0x00000002
70 #define PCH_UART_IIR_RRI 0x00000004
71 #define PCH_UART_IIR_REI 0x00000006
72 #define PCH_UART_IIR_TOI 0x00000008
73 #define PCH_UART_IIR_FIFO256 0x00000020
74 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
75 #define PCH_UART_IIR_FE 0x000000C0
76
77 #define PCH_UART_FCR_FIFOE 0x00000001
78 #define PCH_UART_FCR_RFR 0x00000002
79 #define PCH_UART_FCR_TFR 0x00000004
80 #define PCH_UART_FCR_DMS 0x00000008
81 #define PCH_UART_FCR_FIFO256 0x00000020
82 #define PCH_UART_FCR_RFTL 0x000000C0
83
84 #define PCH_UART_FCR_RFTL1 0x00000000
85 #define PCH_UART_FCR_RFTL64 0x00000040
86 #define PCH_UART_FCR_RFTL128 0x00000080
87 #define PCH_UART_FCR_RFTL224 0x000000C0
88 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
89 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
90 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
91 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
92 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
93 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
94 #define PCH_UART_FCR_RFTL_SHIFT 6
95
96 #define PCH_UART_LCR_WLS 0x00000003
97 #define PCH_UART_LCR_STB 0x00000004
98 #define PCH_UART_LCR_PEN 0x00000008
99 #define PCH_UART_LCR_EPS 0x00000010
100 #define PCH_UART_LCR_SP 0x00000020
101 #define PCH_UART_LCR_SB 0x00000040
102 #define PCH_UART_LCR_DLAB 0x00000080
103 #define PCH_UART_LCR_NP 0x00000000
104 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
105 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
106 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
107 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
108 PCH_UART_LCR_SP)
109
110 #define PCH_UART_LCR_5BIT 0x00000000
111 #define PCH_UART_LCR_6BIT 0x00000001
112 #define PCH_UART_LCR_7BIT 0x00000002
113 #define PCH_UART_LCR_8BIT 0x00000003
114
115 #define PCH_UART_MCR_DTR 0x00000001
116 #define PCH_UART_MCR_RTS 0x00000002
117 #define PCH_UART_MCR_OUT 0x0000000C
118 #define PCH_UART_MCR_LOOP 0x00000010
119 #define PCH_UART_MCR_AFE 0x00000020
120
121 #define PCH_UART_LSR_DR 0x00000001
122 #define PCH_UART_LSR_ERR (1<<7)
123
124 #define PCH_UART_MSR_DCTS 0x00000001
125 #define PCH_UART_MSR_DDSR 0x00000002
126 #define PCH_UART_MSR_TERI 0x00000004
127 #define PCH_UART_MSR_DDCD 0x00000008
128 #define PCH_UART_MSR_CTS 0x00000010
129 #define PCH_UART_MSR_DSR 0x00000020
130 #define PCH_UART_MSR_RI 0x00000040
131 #define PCH_UART_MSR_DCD 0x00000080
132 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
133 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
134
135 #define PCH_UART_DLL 0x00
136 #define PCH_UART_DLM 0x01
137
138 #define PCH_UART_BRCSR 0x0E
139
140 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
141 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
142 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
143 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
144 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
145
146 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
147 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
148 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
149 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
150 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
151 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
152 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
153 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
154 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
155 #define PCH_UART_HAL_STB1 0
156 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
157
158 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
159 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
160 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
161 PCH_UART_HAL_CLR_RX_FIFO)
162
163 #define PCH_UART_HAL_DMA_MODE0 0
164 #define PCH_UART_HAL_FIFO_DIS 0
165 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
166 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
167 PCH_UART_FCR_FIFO256)
168 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
169 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
170 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
171 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
172 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
173 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
174 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
175 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
176 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
177 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
178 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
179 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
180 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
181 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
182
183 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
184 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
185 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
186 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
187 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
188
189 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
190 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
191 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
192 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
193 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
194
195 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
196
197 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
198 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
199 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
200 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
201 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
202 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
203
204 struct pch_uart_buffer {
205 unsigned char *buf;
206 int size;
207 };
208
209 struct eg20t_port {
210 struct uart_port port;
211 int port_type;
212 void __iomem *membase;
213 resource_size_t mapbase;
214 unsigned int iobase;
215 struct pci_dev *pdev;
216 int fifo_size;
217 unsigned int uartclk;
218 int start_tx;
219 int start_rx;
220 int tx_empty;
221 int trigger;
222 int trigger_level;
223 struct pch_uart_buffer rxbuf;
224 unsigned int dmsr;
225 unsigned int fcr;
226 unsigned int mcr;
227 unsigned int use_dma;
228 struct dma_async_tx_descriptor *desc_tx;
229 struct dma_async_tx_descriptor *desc_rx;
230 struct pch_dma_slave param_tx;
231 struct pch_dma_slave param_rx;
232 struct dma_chan *chan_tx;
233 struct dma_chan *chan_rx;
234 struct scatterlist *sg_tx_p;
235 int nent;
236 int orig_nent;
237 struct scatterlist sg_rx;
238 int tx_dma_use;
239 void *rx_buf_virt;
240 dma_addr_t rx_buf_dma;
241
242 struct dentry *debugfs;
243 #define IRQ_NAME_SIZE 17
244 char irq_name[IRQ_NAME_SIZE];
245
246 /* protect the eg20t_port private structure and io access to membase */
247 spinlock_t lock;
248 };
249
250 /**
251 * struct pch_uart_driver_data - private data structure for UART-DMA
252 * @port_type: The type of UART port
253 * @line_no: UART port line number (0, 1, 2...)
254 */
255 struct pch_uart_driver_data {
256 int port_type;
257 int line_no;
258 };
259
260 enum pch_uart_num_t {
261 pch_et20t_uart0 = 0,
262 pch_et20t_uart1,
263 pch_et20t_uart2,
264 pch_et20t_uart3,
265 pch_ml7213_uart0,
266 pch_ml7213_uart1,
267 pch_ml7213_uart2,
268 pch_ml7223_uart0,
269 pch_ml7223_uart1,
270 pch_ml7831_uart0,
271 pch_ml7831_uart1,
272 };
273
274 static struct pch_uart_driver_data drv_dat[] = {
275 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
276 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
277 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
278 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
279 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
280 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
281 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
282 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
283 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
284 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
285 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
286 };
287
288 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
289 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
290 #endif
291 static unsigned int default_baud = 9600;
292 static unsigned int user_uartclk = 0;
293 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
294 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
295 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
296 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
297
298 #ifdef CONFIG_DEBUG_FS
299
300 #define PCH_REGS_BUFSIZE 1024
301
302
303 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
304 size_t count, loff_t *ppos)
305 {
306 struct eg20t_port *priv = file->private_data;
307 char *buf;
308 u32 len = 0;
309 ssize_t ret;
310 unsigned char lcr;
311
312 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
313 if (!buf)
314 return 0;
315
316 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
317 "PCH EG20T port[%d] regs:\n", priv->port.line);
318
319 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
320 "=================================\n");
321 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
322 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
323 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
324 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
325 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
326 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
328 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
330 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
332 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334 "BRCSR: \t0x%02x\n",
335 ioread8(priv->membase + PCH_UART_BRCSR));
336
337 lcr = ioread8(priv->membase + UART_LCR);
338 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
343 iowrite8(lcr, priv->membase + UART_LCR);
344
345 if (len > PCH_REGS_BUFSIZE)
346 len = PCH_REGS_BUFSIZE;
347
348 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
349 kfree(buf);
350 return ret;
351 }
352
353 static const struct file_operations port_regs_ops = {
354 .owner = THIS_MODULE,
355 .open = simple_open,
356 .read = port_show_regs,
357 .llseek = default_llseek,
358 };
359 #endif /* CONFIG_DEBUG_FS */
360
361 static const struct dmi_system_id pch_uart_dmi_table[] = {
362 {
363 .ident = "CM-iTC",
364 {
365 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
366 },
367 (void *)CMITC_UARTCLK,
368 },
369 {
370 .ident = "FRI2",
371 {
372 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
373 },
374 (void *)FRI2_64_UARTCLK,
375 },
376 {
377 .ident = "Fish River Island II",
378 {
379 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
380 },
381 (void *)FRI2_48_UARTCLK,
382 },
383 {
384 .ident = "COMe-mTT",
385 {
386 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
387 },
388 (void *)NTC1_UARTCLK,
389 },
390 {
391 .ident = "nanoETXexpress-TT",
392 {
393 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
394 },
395 (void *)NTC1_UARTCLK,
396 },
397 {
398 .ident = "MinnowBoard",
399 {
400 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
401 },
402 (void *)MINNOW_UARTCLK,
403 },
404 { }
405 };
406
407 /* Return UART clock, checking for board specific clocks. */
408 static unsigned int pch_uart_get_uartclk(void)
409 {
410 const struct dmi_system_id *d;
411
412 if (user_uartclk)
413 return user_uartclk;
414
415 d = dmi_first_match(pch_uart_dmi_table);
416 if (d)
417 return (unsigned long)d->driver_data;
418
419 return DEFAULT_UARTCLK;
420 }
421
422 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
423 unsigned int flag)
424 {
425 u8 ier = ioread8(priv->membase + UART_IER);
426 ier |= flag & PCH_UART_IER_MASK;
427 iowrite8(ier, priv->membase + UART_IER);
428 }
429
430 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
431 unsigned int flag)
432 {
433 u8 ier = ioread8(priv->membase + UART_IER);
434 ier &= ~(flag & PCH_UART_IER_MASK);
435 iowrite8(ier, priv->membase + UART_IER);
436 }
437
438 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
439 unsigned int parity, unsigned int bits,
440 unsigned int stb)
441 {
442 unsigned int dll, dlm, lcr;
443 int div;
444
445 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
446 if (div < 0 || USHRT_MAX <= div) {
447 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
448 return -EINVAL;
449 }
450
451 dll = (unsigned int)div & 0x00FFU;
452 dlm = ((unsigned int)div >> 8) & 0x00FFU;
453
454 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
455 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
456 return -EINVAL;
457 }
458
459 if (bits & ~PCH_UART_LCR_WLS) {
460 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
461 return -EINVAL;
462 }
463
464 if (stb & ~PCH_UART_LCR_STB) {
465 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
466 return -EINVAL;
467 }
468
469 lcr = parity;
470 lcr |= bits;
471 lcr |= stb;
472
473 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
474 __func__, baud, div, lcr, jiffies);
475 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
476 iowrite8(dll, priv->membase + PCH_UART_DLL);
477 iowrite8(dlm, priv->membase + PCH_UART_DLM);
478 iowrite8(lcr, priv->membase + UART_LCR);
479
480 return 0;
481 }
482
483 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
484 unsigned int flag)
485 {
486 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
487 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
488 __func__, flag);
489 return -EINVAL;
490 }
491
492 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
493 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
494 priv->membase + UART_FCR);
495 iowrite8(priv->fcr, priv->membase + UART_FCR);
496
497 return 0;
498 }
499
500 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
501 unsigned int dmamode,
502 unsigned int fifo_size, unsigned int trigger)
503 {
504 u8 fcr;
505
506 if (dmamode & ~PCH_UART_FCR_DMS) {
507 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
508 __func__, dmamode);
509 return -EINVAL;
510 }
511
512 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
513 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
514 __func__, fifo_size);
515 return -EINVAL;
516 }
517
518 if (trigger & ~PCH_UART_FCR_RFTL) {
519 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
520 __func__, trigger);
521 return -EINVAL;
522 }
523
524 switch (priv->fifo_size) {
525 case 256:
526 priv->trigger_level =
527 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
528 break;
529 case 64:
530 priv->trigger_level =
531 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
532 break;
533 case 16:
534 priv->trigger_level =
535 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
536 break;
537 default:
538 priv->trigger_level =
539 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
540 break;
541 }
542 fcr =
543 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
544 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
545 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
546 priv->membase + UART_FCR);
547 iowrite8(fcr, priv->membase + UART_FCR);
548 priv->fcr = fcr;
549
550 return 0;
551 }
552
553 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
554 {
555 unsigned int msr = ioread8(priv->membase + UART_MSR);
556 priv->dmsr = msr & PCH_UART_MSR_DELTA;
557 return (u8)msr;
558 }
559
560 static void pch_uart_hal_write(struct eg20t_port *priv,
561 const unsigned char *buf, int tx_size)
562 {
563 int i;
564 unsigned int thr;
565
566 for (i = 0; i < tx_size;) {
567 thr = buf[i++];
568 iowrite8(thr, priv->membase + PCH_UART_THR);
569 }
570 }
571
572 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
573 int rx_size)
574 {
575 int i;
576 u8 rbr, lsr;
577 struct uart_port *port = &priv->port;
578
579 lsr = ioread8(priv->membase + UART_LSR);
580 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
581 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
582 lsr = ioread8(priv->membase + UART_LSR)) {
583 rbr = ioread8(priv->membase + PCH_UART_RBR);
584
585 if (lsr & UART_LSR_BI) {
586 port->icount.brk++;
587 if (uart_handle_break(port))
588 continue;
589 }
590 #ifdef SUPPORT_SYSRQ
591 if (port->sysrq) {
592 if (uart_handle_sysrq_char(port, rbr))
593 continue;
594 }
595 #endif
596
597 buf[i++] = rbr;
598 }
599 return i;
600 }
601
602 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
603 {
604 return ioread8(priv->membase + UART_IIR) &\
605 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
606 }
607
608 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
609 {
610 return ioread8(priv->membase + UART_LSR);
611 }
612
613 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
614 {
615 unsigned int lcr;
616
617 lcr = ioread8(priv->membase + UART_LCR);
618 if (on)
619 lcr |= PCH_UART_LCR_SB;
620 else
621 lcr &= ~PCH_UART_LCR_SB;
622
623 iowrite8(lcr, priv->membase + UART_LCR);
624 }
625
626 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
627 int size)
628 {
629 struct uart_port *port = &priv->port;
630 struct tty_port *tport = &port->state->port;
631
632 tty_insert_flip_string(tport, buf, size);
633 tty_flip_buffer_push(tport);
634
635 return 0;
636 }
637
638 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
639 {
640 int ret = 0;
641 struct uart_port *port = &priv->port;
642
643 if (port->x_char) {
644 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
645 __func__, port->x_char, jiffies);
646 buf[0] = port->x_char;
647 port->x_char = 0;
648 ret = 1;
649 }
650
651 return ret;
652 }
653
654 static int dma_push_rx(struct eg20t_port *priv, int size)
655 {
656 int room;
657 struct uart_port *port = &priv->port;
658 struct tty_port *tport = &port->state->port;
659
660 room = tty_buffer_request_room(tport, size);
661
662 if (room < size)
663 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
664 size - room);
665 if (!room)
666 return 0;
667
668 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
669
670 port->icount.rx += room;
671
672 return room;
673 }
674
675 static void pch_free_dma(struct uart_port *port)
676 {
677 struct eg20t_port *priv;
678 priv = container_of(port, struct eg20t_port, port);
679
680 if (priv->chan_tx) {
681 dma_release_channel(priv->chan_tx);
682 priv->chan_tx = NULL;
683 }
684 if (priv->chan_rx) {
685 dma_release_channel(priv->chan_rx);
686 priv->chan_rx = NULL;
687 }
688
689 if (priv->rx_buf_dma) {
690 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
691 priv->rx_buf_dma);
692 priv->rx_buf_virt = NULL;
693 priv->rx_buf_dma = 0;
694 }
695
696 return;
697 }
698
699 static bool filter(struct dma_chan *chan, void *slave)
700 {
701 struct pch_dma_slave *param = slave;
702
703 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
704 chan->device->dev)) {
705 chan->private = param;
706 return true;
707 } else {
708 return false;
709 }
710 }
711
712 static void pch_request_dma(struct uart_port *port)
713 {
714 dma_cap_mask_t mask;
715 struct dma_chan *chan;
716 struct pci_dev *dma_dev;
717 struct pch_dma_slave *param;
718 struct eg20t_port *priv =
719 container_of(port, struct eg20t_port, port);
720 dma_cap_zero(mask);
721 dma_cap_set(DMA_SLAVE, mask);
722
723 /* Get DMA's dev information */
724 dma_dev = pci_get_slot(priv->pdev->bus,
725 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
726
727 /* Set Tx DMA */
728 param = &priv->param_tx;
729 param->dma_dev = &dma_dev->dev;
730 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
731
732 param->tx_reg = port->mapbase + UART_TX;
733 chan = dma_request_channel(mask, filter, param);
734 if (!chan) {
735 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
736 __func__);
737 return;
738 }
739 priv->chan_tx = chan;
740
741 /* Set Rx DMA */
742 param = &priv->param_rx;
743 param->dma_dev = &dma_dev->dev;
744 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
745
746 param->rx_reg = port->mapbase + UART_RX;
747 chan = dma_request_channel(mask, filter, param);
748 if (!chan) {
749 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
750 __func__);
751 dma_release_channel(priv->chan_tx);
752 priv->chan_tx = NULL;
753 return;
754 }
755
756 /* Get Consistent memory for DMA */
757 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
758 &priv->rx_buf_dma, GFP_KERNEL);
759 priv->chan_rx = chan;
760 }
761
762 static void pch_dma_rx_complete(void *arg)
763 {
764 struct eg20t_port *priv = arg;
765 struct uart_port *port = &priv->port;
766 int count;
767
768 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
769 count = dma_push_rx(priv, priv->trigger_level);
770 if (count)
771 tty_flip_buffer_push(&port->state->port);
772 async_tx_ack(priv->desc_rx);
773 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
774 PCH_UART_HAL_RX_ERR_INT);
775 }
776
777 static void pch_dma_tx_complete(void *arg)
778 {
779 struct eg20t_port *priv = arg;
780 struct uart_port *port = &priv->port;
781 struct circ_buf *xmit = &port->state->xmit;
782 struct scatterlist *sg = priv->sg_tx_p;
783 int i;
784
785 for (i = 0; i < priv->nent; i++, sg++) {
786 xmit->tail += sg_dma_len(sg);
787 port->icount.tx += sg_dma_len(sg);
788 }
789 xmit->tail &= UART_XMIT_SIZE - 1;
790 async_tx_ack(priv->desc_tx);
791 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
792 priv->tx_dma_use = 0;
793 priv->nent = 0;
794 priv->orig_nent = 0;
795 kfree(priv->sg_tx_p);
796 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
797 }
798
799 static int pop_tx(struct eg20t_port *priv, int size)
800 {
801 int count = 0;
802 struct uart_port *port = &priv->port;
803 struct circ_buf *xmit = &port->state->xmit;
804
805 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
806 goto pop_tx_end;
807
808 do {
809 int cnt_to_end =
810 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
811 int sz = min(size - count, cnt_to_end);
812 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
813 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
814 count += sz;
815 } while (!uart_circ_empty(xmit) && count < size);
816
817 pop_tx_end:
818 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
819 count, size - count, jiffies);
820
821 return count;
822 }
823
824 static int handle_rx_to(struct eg20t_port *priv)
825 {
826 struct pch_uart_buffer *buf;
827 int rx_size;
828 int ret;
829 if (!priv->start_rx) {
830 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
831 PCH_UART_HAL_RX_ERR_INT);
832 return 0;
833 }
834 buf = &priv->rxbuf;
835 do {
836 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
837 ret = push_rx(priv, buf->buf, rx_size);
838 if (ret)
839 return 0;
840 } while (rx_size == buf->size);
841
842 return PCH_UART_HANDLED_RX_INT;
843 }
844
845 static int handle_rx(struct eg20t_port *priv)
846 {
847 return handle_rx_to(priv);
848 }
849
850 static int dma_handle_rx(struct eg20t_port *priv)
851 {
852 struct uart_port *port = &priv->port;
853 struct dma_async_tx_descriptor *desc;
854 struct scatterlist *sg;
855
856 priv = container_of(port, struct eg20t_port, port);
857 sg = &priv->sg_rx;
858
859 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
860
861 sg_dma_len(sg) = priv->trigger_level;
862
863 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
864 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
865
866 sg_dma_address(sg) = priv->rx_buf_dma;
867
868 desc = dmaengine_prep_slave_sg(priv->chan_rx,
869 sg, 1, DMA_DEV_TO_MEM,
870 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
871
872 if (!desc)
873 return 0;
874
875 priv->desc_rx = desc;
876 desc->callback = pch_dma_rx_complete;
877 desc->callback_param = priv;
878 desc->tx_submit(desc);
879 dma_async_issue_pending(priv->chan_rx);
880
881 return PCH_UART_HANDLED_RX_INT;
882 }
883
884 static unsigned int handle_tx(struct eg20t_port *priv)
885 {
886 struct uart_port *port = &priv->port;
887 struct circ_buf *xmit = &port->state->xmit;
888 int fifo_size;
889 int tx_size;
890 int size;
891 int tx_empty;
892
893 if (!priv->start_tx) {
894 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
895 __func__, jiffies);
896 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
897 priv->tx_empty = 1;
898 return 0;
899 }
900
901 fifo_size = max(priv->fifo_size, 1);
902 tx_empty = 1;
903 if (pop_tx_x(priv, xmit->buf)) {
904 pch_uart_hal_write(priv, xmit->buf, 1);
905 port->icount.tx++;
906 tx_empty = 0;
907 fifo_size--;
908 }
909 size = min(xmit->head - xmit->tail, fifo_size);
910 if (size < 0)
911 size = fifo_size;
912
913 tx_size = pop_tx(priv, size);
914 if (tx_size > 0) {
915 port->icount.tx += tx_size;
916 tx_empty = 0;
917 }
918
919 priv->tx_empty = tx_empty;
920
921 if (tx_empty) {
922 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
923 uart_write_wakeup(port);
924 }
925
926 return PCH_UART_HANDLED_TX_INT;
927 }
928
929 static unsigned int dma_handle_tx(struct eg20t_port *priv)
930 {
931 struct uart_port *port = &priv->port;
932 struct circ_buf *xmit = &port->state->xmit;
933 struct scatterlist *sg;
934 int nent;
935 int fifo_size;
936 int tx_empty;
937 struct dma_async_tx_descriptor *desc;
938 int num;
939 int i;
940 int bytes;
941 int size;
942 int rem;
943
944 if (!priv->start_tx) {
945 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
946 __func__, jiffies);
947 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
948 priv->tx_empty = 1;
949 return 0;
950 }
951
952 if (priv->tx_dma_use) {
953 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
954 __func__, jiffies);
955 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
956 priv->tx_empty = 1;
957 return 0;
958 }
959
960 fifo_size = max(priv->fifo_size, 1);
961 tx_empty = 1;
962 if (pop_tx_x(priv, xmit->buf)) {
963 pch_uart_hal_write(priv, xmit->buf, 1);
964 port->icount.tx++;
965 tx_empty = 0;
966 fifo_size--;
967 }
968
969 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
970 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
971 xmit->tail, UART_XMIT_SIZE));
972 if (!bytes) {
973 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
974 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
975 uart_write_wakeup(port);
976 return 0;
977 }
978
979 if (bytes > fifo_size) {
980 num = bytes / fifo_size + 1;
981 size = fifo_size;
982 rem = bytes % fifo_size;
983 } else {
984 num = 1;
985 size = bytes;
986 rem = bytes;
987 }
988
989 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
990 __func__, num, size, rem);
991
992 priv->tx_dma_use = 1;
993
994 priv->sg_tx_p = kcalloc(num, sizeof(struct scatterlist), GFP_ATOMIC);
995 if (!priv->sg_tx_p) {
996 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
997 return 0;
998 }
999
1000 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1001 sg = priv->sg_tx_p;
1002
1003 for (i = 0; i < num; i++, sg++) {
1004 if (i == (num - 1))
1005 sg_set_page(sg, virt_to_page(xmit->buf),
1006 rem, fifo_size * i);
1007 else
1008 sg_set_page(sg, virt_to_page(xmit->buf),
1009 size, fifo_size * i);
1010 }
1011
1012 sg = priv->sg_tx_p;
1013 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1014 if (!nent) {
1015 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1016 return 0;
1017 }
1018 priv->orig_nent = num;
1019 priv->nent = nent;
1020
1021 for (i = 0; i < nent; i++, sg++) {
1022 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1023 fifo_size * i;
1024 sg_dma_address(sg) = (sg_dma_address(sg) &
1025 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1026 if (i == (nent - 1))
1027 sg_dma_len(sg) = rem;
1028 else
1029 sg_dma_len(sg) = size;
1030 }
1031
1032 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1033 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1034 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1035 if (!desc) {
1036 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1037 __func__);
1038 return 0;
1039 }
1040 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1041 priv->desc_tx = desc;
1042 desc->callback = pch_dma_tx_complete;
1043 desc->callback_param = priv;
1044
1045 desc->tx_submit(desc);
1046
1047 dma_async_issue_pending(priv->chan_tx);
1048
1049 return PCH_UART_HANDLED_TX_INT;
1050 }
1051
1052 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1053 {
1054 struct uart_port *port = &priv->port;
1055 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1056 char *error_msg[5] = {};
1057 int i = 0;
1058
1059 if (lsr & PCH_UART_LSR_ERR)
1060 error_msg[i++] = "Error data in FIFO\n";
1061
1062 if (lsr & UART_LSR_FE) {
1063 port->icount.frame++;
1064 error_msg[i++] = " Framing Error\n";
1065 }
1066
1067 if (lsr & UART_LSR_PE) {
1068 port->icount.parity++;
1069 error_msg[i++] = " Parity Error\n";
1070 }
1071
1072 if (lsr & UART_LSR_OE) {
1073 port->icount.overrun++;
1074 error_msg[i++] = " Overrun Error\n";
1075 }
1076
1077 if (tty == NULL) {
1078 for (i = 0; error_msg[i] != NULL; i++)
1079 dev_err(&priv->pdev->dev, error_msg[i]);
1080 } else {
1081 tty_kref_put(tty);
1082 }
1083 }
1084
1085 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1086 {
1087 struct eg20t_port *priv = dev_id;
1088 unsigned int handled;
1089 u8 lsr;
1090 int ret = 0;
1091 unsigned char iid;
1092 unsigned long flags;
1093 int next = 1;
1094 u8 msr;
1095
1096 spin_lock_irqsave(&priv->lock, flags);
1097 handled = 0;
1098 while (next) {
1099 iid = pch_uart_hal_get_iid(priv);
1100 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1101 break;
1102 switch (iid) {
1103 case PCH_UART_IID_RLS: /* Receiver Line Status */
1104 lsr = pch_uart_hal_get_line_status(priv);
1105 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1106 UART_LSR_PE | UART_LSR_OE)) {
1107 pch_uart_err_ir(priv, lsr);
1108 ret = PCH_UART_HANDLED_RX_ERR_INT;
1109 } else {
1110 ret = PCH_UART_HANDLED_LS_INT;
1111 }
1112 break;
1113 case PCH_UART_IID_RDR: /* Received Data Ready */
1114 if (priv->use_dma) {
1115 pch_uart_hal_disable_interrupt(priv,
1116 PCH_UART_HAL_RX_INT |
1117 PCH_UART_HAL_RX_ERR_INT);
1118 ret = dma_handle_rx(priv);
1119 if (!ret)
1120 pch_uart_hal_enable_interrupt(priv,
1121 PCH_UART_HAL_RX_INT |
1122 PCH_UART_HAL_RX_ERR_INT);
1123 } else {
1124 ret = handle_rx(priv);
1125 }
1126 break;
1127 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1128 (FIFO Timeout) */
1129 ret = handle_rx_to(priv);
1130 break;
1131 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1132 Empty */
1133 if (priv->use_dma)
1134 ret = dma_handle_tx(priv);
1135 else
1136 ret = handle_tx(priv);
1137 break;
1138 case PCH_UART_IID_MS: /* Modem Status */
1139 msr = pch_uart_hal_get_modem(priv);
1140 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1141 means final interrupt */
1142 if ((msr & UART_MSR_ANY_DELTA) == 0)
1143 break;
1144 ret |= PCH_UART_HANDLED_MS_INT;
1145 break;
1146 default: /* Never junp to this label */
1147 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1148 iid, jiffies);
1149 ret = -1;
1150 next = 0;
1151 break;
1152 }
1153 handled |= (unsigned int)ret;
1154 }
1155
1156 spin_unlock_irqrestore(&priv->lock, flags);
1157 return IRQ_RETVAL(handled);
1158 }
1159
1160 /* This function tests whether the transmitter fifo and shifter for the port
1161 described by 'port' is empty. */
1162 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1163 {
1164 struct eg20t_port *priv;
1165
1166 priv = container_of(port, struct eg20t_port, port);
1167 if (priv->tx_empty)
1168 return TIOCSER_TEMT;
1169 else
1170 return 0;
1171 }
1172
1173 /* Returns the current state of modem control inputs. */
1174 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1175 {
1176 struct eg20t_port *priv;
1177 u8 modem;
1178 unsigned int ret = 0;
1179
1180 priv = container_of(port, struct eg20t_port, port);
1181 modem = pch_uart_hal_get_modem(priv);
1182
1183 if (modem & UART_MSR_DCD)
1184 ret |= TIOCM_CAR;
1185
1186 if (modem & UART_MSR_RI)
1187 ret |= TIOCM_RNG;
1188
1189 if (modem & UART_MSR_DSR)
1190 ret |= TIOCM_DSR;
1191
1192 if (modem & UART_MSR_CTS)
1193 ret |= TIOCM_CTS;
1194
1195 return ret;
1196 }
1197
1198 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1199 {
1200 u32 mcr = 0;
1201 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1202
1203 if (mctrl & TIOCM_DTR)
1204 mcr |= UART_MCR_DTR;
1205 if (mctrl & TIOCM_RTS)
1206 mcr |= UART_MCR_RTS;
1207 if (mctrl & TIOCM_LOOP)
1208 mcr |= UART_MCR_LOOP;
1209
1210 if (priv->mcr & UART_MCR_AFE)
1211 mcr |= UART_MCR_AFE;
1212
1213 if (mctrl)
1214 iowrite8(mcr, priv->membase + UART_MCR);
1215 }
1216
1217 static void pch_uart_stop_tx(struct uart_port *port)
1218 {
1219 struct eg20t_port *priv;
1220 priv = container_of(port, struct eg20t_port, port);
1221 priv->start_tx = 0;
1222 priv->tx_dma_use = 0;
1223 }
1224
1225 static void pch_uart_start_tx(struct uart_port *port)
1226 {
1227 struct eg20t_port *priv;
1228
1229 priv = container_of(port, struct eg20t_port, port);
1230
1231 if (priv->use_dma) {
1232 if (priv->tx_dma_use) {
1233 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1234 __func__);
1235 return;
1236 }
1237 }
1238
1239 priv->start_tx = 1;
1240 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1241 }
1242
1243 static void pch_uart_stop_rx(struct uart_port *port)
1244 {
1245 struct eg20t_port *priv;
1246 priv = container_of(port, struct eg20t_port, port);
1247 priv->start_rx = 0;
1248 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1249 PCH_UART_HAL_RX_ERR_INT);
1250 }
1251
1252 /* Enable the modem status interrupts. */
1253 static void pch_uart_enable_ms(struct uart_port *port)
1254 {
1255 struct eg20t_port *priv;
1256 priv = container_of(port, struct eg20t_port, port);
1257 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1258 }
1259
1260 /* Control the transmission of a break signal. */
1261 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1262 {
1263 struct eg20t_port *priv;
1264 unsigned long flags;
1265
1266 priv = container_of(port, struct eg20t_port, port);
1267 spin_lock_irqsave(&priv->lock, flags);
1268 pch_uart_hal_set_break(priv, ctl);
1269 spin_unlock_irqrestore(&priv->lock, flags);
1270 }
1271
1272 /* Grab any interrupt resources and initialise any low level driver state. */
1273 static int pch_uart_startup(struct uart_port *port)
1274 {
1275 struct eg20t_port *priv;
1276 int ret;
1277 int fifo_size;
1278 int trigger_level;
1279
1280 priv = container_of(port, struct eg20t_port, port);
1281 priv->tx_empty = 1;
1282
1283 if (port->uartclk)
1284 priv->uartclk = port->uartclk;
1285 else
1286 port->uartclk = priv->uartclk;
1287
1288 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1289 ret = pch_uart_hal_set_line(priv, default_baud,
1290 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1291 PCH_UART_HAL_STB1);
1292 if (ret)
1293 return ret;
1294
1295 switch (priv->fifo_size) {
1296 case 256:
1297 fifo_size = PCH_UART_HAL_FIFO256;
1298 break;
1299 case 64:
1300 fifo_size = PCH_UART_HAL_FIFO64;
1301 break;
1302 case 16:
1303 fifo_size = PCH_UART_HAL_FIFO16;
1304 break;
1305 case 1:
1306 default:
1307 fifo_size = PCH_UART_HAL_FIFO_DIS;
1308 break;
1309 }
1310
1311 switch (priv->trigger) {
1312 case PCH_UART_HAL_TRIGGER1:
1313 trigger_level = 1;
1314 break;
1315 case PCH_UART_HAL_TRIGGER_L:
1316 trigger_level = priv->fifo_size / 4;
1317 break;
1318 case PCH_UART_HAL_TRIGGER_M:
1319 trigger_level = priv->fifo_size / 2;
1320 break;
1321 case PCH_UART_HAL_TRIGGER_H:
1322 default:
1323 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1324 break;
1325 }
1326
1327 priv->trigger_level = trigger_level;
1328 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1329 fifo_size, priv->trigger);
1330 if (ret < 0)
1331 return ret;
1332
1333 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1334 priv->irq_name, priv);
1335 if (ret < 0)
1336 return ret;
1337
1338 if (priv->use_dma)
1339 pch_request_dma(port);
1340
1341 priv->start_rx = 1;
1342 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1343 PCH_UART_HAL_RX_ERR_INT);
1344 uart_update_timeout(port, CS8, default_baud);
1345
1346 return 0;
1347 }
1348
1349 static void pch_uart_shutdown(struct uart_port *port)
1350 {
1351 struct eg20t_port *priv;
1352 int ret;
1353
1354 priv = container_of(port, struct eg20t_port, port);
1355 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1356 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1357 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1358 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1359 if (ret)
1360 dev_err(priv->port.dev,
1361 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1362
1363 pch_free_dma(port);
1364
1365 free_irq(priv->port.irq, priv);
1366 }
1367
1368 /* Change the port parameters, including word length, parity, stop
1369 *bits. Update read_status_mask and ignore_status_mask to indicate
1370 *the types of events we are interested in receiving. */
1371 static void pch_uart_set_termios(struct uart_port *port,
1372 struct ktermios *termios, struct ktermios *old)
1373 {
1374 int rtn;
1375 unsigned int baud, parity, bits, stb;
1376 struct eg20t_port *priv;
1377 unsigned long flags;
1378
1379 priv = container_of(port, struct eg20t_port, port);
1380 switch (termios->c_cflag & CSIZE) {
1381 case CS5:
1382 bits = PCH_UART_HAL_5BIT;
1383 break;
1384 case CS6:
1385 bits = PCH_UART_HAL_6BIT;
1386 break;
1387 case CS7:
1388 bits = PCH_UART_HAL_7BIT;
1389 break;
1390 default: /* CS8 */
1391 bits = PCH_UART_HAL_8BIT;
1392 break;
1393 }
1394 if (termios->c_cflag & CSTOPB)
1395 stb = PCH_UART_HAL_STB2;
1396 else
1397 stb = PCH_UART_HAL_STB1;
1398
1399 if (termios->c_cflag & PARENB) {
1400 if (termios->c_cflag & PARODD)
1401 parity = PCH_UART_HAL_PARITY_ODD;
1402 else
1403 parity = PCH_UART_HAL_PARITY_EVEN;
1404
1405 } else
1406 parity = PCH_UART_HAL_PARITY_NONE;
1407
1408 /* Only UART0 has auto hardware flow function */
1409 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1410 priv->mcr |= UART_MCR_AFE;
1411 else
1412 priv->mcr &= ~UART_MCR_AFE;
1413
1414 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1415
1416 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1417
1418 spin_lock_irqsave(&priv->lock, flags);
1419 spin_lock(&port->lock);
1420
1421 uart_update_timeout(port, termios->c_cflag, baud);
1422 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1423 if (rtn)
1424 goto out;
1425
1426 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1427 /* Don't rewrite B0 */
1428 if (tty_termios_baud_rate(termios))
1429 tty_termios_encode_baud_rate(termios, baud, baud);
1430
1431 out:
1432 spin_unlock(&port->lock);
1433 spin_unlock_irqrestore(&priv->lock, flags);
1434 }
1435
1436 static const char *pch_uart_type(struct uart_port *port)
1437 {
1438 return KBUILD_MODNAME;
1439 }
1440
1441 static void pch_uart_release_port(struct uart_port *port)
1442 {
1443 struct eg20t_port *priv;
1444
1445 priv = container_of(port, struct eg20t_port, port);
1446 pci_iounmap(priv->pdev, priv->membase);
1447 pci_release_regions(priv->pdev);
1448 }
1449
1450 static int pch_uart_request_port(struct uart_port *port)
1451 {
1452 struct eg20t_port *priv;
1453 int ret;
1454 void __iomem *membase;
1455
1456 priv = container_of(port, struct eg20t_port, port);
1457 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1458 if (ret < 0)
1459 return -EBUSY;
1460
1461 membase = pci_iomap(priv->pdev, 1, 0);
1462 if (!membase) {
1463 pci_release_regions(priv->pdev);
1464 return -EBUSY;
1465 }
1466 priv->membase = port->membase = membase;
1467
1468 return 0;
1469 }
1470
1471 static void pch_uart_config_port(struct uart_port *port, int type)
1472 {
1473 struct eg20t_port *priv;
1474
1475 priv = container_of(port, struct eg20t_port, port);
1476 if (type & UART_CONFIG_TYPE) {
1477 port->type = priv->port_type;
1478 pch_uart_request_port(port);
1479 }
1480 }
1481
1482 static int pch_uart_verify_port(struct uart_port *port,
1483 struct serial_struct *serinfo)
1484 {
1485 struct eg20t_port *priv;
1486
1487 priv = container_of(port, struct eg20t_port, port);
1488 if (serinfo->flags & UPF_LOW_LATENCY) {
1489 dev_info(priv->port.dev,
1490 "PCH UART : Use PIO Mode (without DMA)\n");
1491 priv->use_dma = 0;
1492 serinfo->flags &= ~UPF_LOW_LATENCY;
1493 } else {
1494 #ifndef CONFIG_PCH_DMA
1495 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1496 __func__);
1497 return -EOPNOTSUPP;
1498 #endif
1499 if (!priv->use_dma) {
1500 pch_request_dma(port);
1501 if (priv->chan_rx)
1502 priv->use_dma = 1;
1503 }
1504 dev_info(priv->port.dev, "PCH UART: %s\n",
1505 priv->use_dma ?
1506 "Use DMA Mode" : "No DMA");
1507 }
1508
1509 return 0;
1510 }
1511
1512 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1513 /*
1514 * Wait for transmitter & holding register to empty
1515 */
1516 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1517 {
1518 unsigned int status, tmout = 10000;
1519
1520 /* Wait up to 10ms for the character(s) to be sent. */
1521 for (;;) {
1522 status = ioread8(up->membase + UART_LSR);
1523
1524 if ((status & bits) == bits)
1525 break;
1526 if (--tmout == 0)
1527 break;
1528 udelay(1);
1529 }
1530
1531 /* Wait up to 1s for flow control if necessary */
1532 if (up->port.flags & UPF_CONS_FLOW) {
1533 unsigned int tmout;
1534 for (tmout = 1000000; tmout; tmout--) {
1535 unsigned int msr = ioread8(up->membase + UART_MSR);
1536 if (msr & UART_MSR_CTS)
1537 break;
1538 udelay(1);
1539 touch_nmi_watchdog();
1540 }
1541 }
1542 }
1543 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1544
1545 #ifdef CONFIG_CONSOLE_POLL
1546 /*
1547 * Console polling routines for communicate via uart while
1548 * in an interrupt or debug context.
1549 */
1550 static int pch_uart_get_poll_char(struct uart_port *port)
1551 {
1552 struct eg20t_port *priv =
1553 container_of(port, struct eg20t_port, port);
1554 u8 lsr = ioread8(priv->membase + UART_LSR);
1555
1556 if (!(lsr & UART_LSR_DR))
1557 return NO_POLL_CHAR;
1558
1559 return ioread8(priv->membase + PCH_UART_RBR);
1560 }
1561
1562
1563 static void pch_uart_put_poll_char(struct uart_port *port,
1564 unsigned char c)
1565 {
1566 unsigned int ier;
1567 struct eg20t_port *priv =
1568 container_of(port, struct eg20t_port, port);
1569
1570 /*
1571 * First save the IER then disable the interrupts
1572 */
1573 ier = ioread8(priv->membase + UART_IER);
1574 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1575
1576 wait_for_xmitr(priv, UART_LSR_THRE);
1577 /*
1578 * Send the character out.
1579 */
1580 iowrite8(c, priv->membase + PCH_UART_THR);
1581
1582 /*
1583 * Finally, wait for transmitter to become empty
1584 * and restore the IER
1585 */
1586 wait_for_xmitr(priv, BOTH_EMPTY);
1587 iowrite8(ier, priv->membase + UART_IER);
1588 }
1589 #endif /* CONFIG_CONSOLE_POLL */
1590
1591 static const struct uart_ops pch_uart_ops = {
1592 .tx_empty = pch_uart_tx_empty,
1593 .set_mctrl = pch_uart_set_mctrl,
1594 .get_mctrl = pch_uart_get_mctrl,
1595 .stop_tx = pch_uart_stop_tx,
1596 .start_tx = pch_uart_start_tx,
1597 .stop_rx = pch_uart_stop_rx,
1598 .enable_ms = pch_uart_enable_ms,
1599 .break_ctl = pch_uart_break_ctl,
1600 .startup = pch_uart_startup,
1601 .shutdown = pch_uart_shutdown,
1602 .set_termios = pch_uart_set_termios,
1603 /* .pm = pch_uart_pm, Not supported yet */
1604 .type = pch_uart_type,
1605 .release_port = pch_uart_release_port,
1606 .request_port = pch_uart_request_port,
1607 .config_port = pch_uart_config_port,
1608 .verify_port = pch_uart_verify_port,
1609 #ifdef CONFIG_CONSOLE_POLL
1610 .poll_get_char = pch_uart_get_poll_char,
1611 .poll_put_char = pch_uart_put_poll_char,
1612 #endif
1613 };
1614
1615 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1616
1617 static void pch_console_putchar(struct uart_port *port, int ch)
1618 {
1619 struct eg20t_port *priv =
1620 container_of(port, struct eg20t_port, port);
1621
1622 wait_for_xmitr(priv, UART_LSR_THRE);
1623 iowrite8(ch, priv->membase + PCH_UART_THR);
1624 }
1625
1626 /*
1627 * Print a string to the serial port trying not to disturb
1628 * any possible real use of the port...
1629 *
1630 * The console_lock must be held when we get here.
1631 */
1632 static void
1633 pch_console_write(struct console *co, const char *s, unsigned int count)
1634 {
1635 struct eg20t_port *priv;
1636 unsigned long flags;
1637 int priv_locked = 1;
1638 int port_locked = 1;
1639 u8 ier;
1640
1641 priv = pch_uart_ports[co->index];
1642
1643 touch_nmi_watchdog();
1644
1645 local_irq_save(flags);
1646 if (priv->port.sysrq) {
1647 /* call to uart_handle_sysrq_char already took the priv lock */
1648 priv_locked = 0;
1649 /* serial8250_handle_port() already took the port lock */
1650 port_locked = 0;
1651 } else if (oops_in_progress) {
1652 priv_locked = spin_trylock(&priv->lock);
1653 port_locked = spin_trylock(&priv->port.lock);
1654 } else {
1655 spin_lock(&priv->lock);
1656 spin_lock(&priv->port.lock);
1657 }
1658
1659 /*
1660 * First save the IER then disable the interrupts
1661 */
1662 ier = ioread8(priv->membase + UART_IER);
1663
1664 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1665
1666 uart_console_write(&priv->port, s, count, pch_console_putchar);
1667
1668 /*
1669 * Finally, wait for transmitter to become empty
1670 * and restore the IER
1671 */
1672 wait_for_xmitr(priv, BOTH_EMPTY);
1673 iowrite8(ier, priv->membase + UART_IER);
1674
1675 if (port_locked)
1676 spin_unlock(&priv->port.lock);
1677 if (priv_locked)
1678 spin_unlock(&priv->lock);
1679 local_irq_restore(flags);
1680 }
1681
1682 static int __init pch_console_setup(struct console *co, char *options)
1683 {
1684 struct uart_port *port;
1685 int baud = default_baud;
1686 int bits = 8;
1687 int parity = 'n';
1688 int flow = 'n';
1689
1690 /*
1691 * Check whether an invalid uart number has been specified, and
1692 * if so, search for the first available port that does have
1693 * console support.
1694 */
1695 if (co->index >= PCH_UART_NR)
1696 co->index = 0;
1697 port = &pch_uart_ports[co->index]->port;
1698
1699 if (!port || (!port->iobase && !port->membase))
1700 return -ENODEV;
1701
1702 port->uartclk = pch_uart_get_uartclk();
1703
1704 if (options)
1705 uart_parse_options(options, &baud, &parity, &bits, &flow);
1706
1707 return uart_set_options(port, co, baud, parity, bits, flow);
1708 }
1709
1710 static struct uart_driver pch_uart_driver;
1711
1712 static struct console pch_console = {
1713 .name = PCH_UART_DRIVER_DEVICE,
1714 .write = pch_console_write,
1715 .device = uart_console_device,
1716 .setup = pch_console_setup,
1717 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1718 .index = -1,
1719 .data = &pch_uart_driver,
1720 };
1721
1722 #define PCH_CONSOLE (&pch_console)
1723 #else
1724 #define PCH_CONSOLE NULL
1725 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1726
1727 static struct uart_driver pch_uart_driver = {
1728 .owner = THIS_MODULE,
1729 .driver_name = KBUILD_MODNAME,
1730 .dev_name = PCH_UART_DRIVER_DEVICE,
1731 .major = 0,
1732 .minor = 0,
1733 .nr = PCH_UART_NR,
1734 .cons = PCH_CONSOLE,
1735 };
1736
1737 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1738 const struct pci_device_id *id)
1739 {
1740 struct eg20t_port *priv;
1741 int ret;
1742 unsigned int iobase;
1743 unsigned int mapbase;
1744 unsigned char *rxbuf;
1745 int fifosize;
1746 int port_type;
1747 struct pch_uart_driver_data *board;
1748 #ifdef CONFIG_DEBUG_FS
1749 char name[32]; /* for debugfs file name */
1750 #endif
1751
1752 board = &drv_dat[id->driver_data];
1753 port_type = board->port_type;
1754
1755 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1756 if (priv == NULL)
1757 goto init_port_alloc_err;
1758
1759 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1760 if (!rxbuf)
1761 goto init_port_free_txbuf;
1762
1763 switch (port_type) {
1764 case PORT_PCH_8LINE:
1765 fifosize = 256; /* EG20T/ML7213: UART0 */
1766 break;
1767 case PORT_PCH_2LINE:
1768 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1769 break;
1770 default:
1771 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1772 goto init_port_hal_free;
1773 }
1774
1775 pci_enable_msi(pdev);
1776 pci_set_master(pdev);
1777
1778 spin_lock_init(&priv->lock);
1779
1780 iobase = pci_resource_start(pdev, 0);
1781 mapbase = pci_resource_start(pdev, 1);
1782 priv->mapbase = mapbase;
1783 priv->iobase = iobase;
1784 priv->pdev = pdev;
1785 priv->tx_empty = 1;
1786 priv->rxbuf.buf = rxbuf;
1787 priv->rxbuf.size = PAGE_SIZE;
1788
1789 priv->fifo_size = fifosize;
1790 priv->uartclk = pch_uart_get_uartclk();
1791 priv->port_type = port_type;
1792 priv->port.dev = &pdev->dev;
1793 priv->port.iobase = iobase;
1794 priv->port.membase = NULL;
1795 priv->port.mapbase = mapbase;
1796 priv->port.irq = pdev->irq;
1797 priv->port.iotype = UPIO_PORT;
1798 priv->port.ops = &pch_uart_ops;
1799 priv->port.flags = UPF_BOOT_AUTOCONF;
1800 priv->port.fifosize = fifosize;
1801 priv->port.line = board->line_no;
1802 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1803
1804 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1805 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1806 priv->port.line);
1807
1808 spin_lock_init(&priv->port.lock);
1809
1810 pci_set_drvdata(pdev, priv);
1811 priv->trigger_level = 1;
1812 priv->fcr = 0;
1813
1814 if (pdev->dev.of_node)
1815 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1816 , &user_uartclk);
1817
1818 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1819 pch_uart_ports[board->line_no] = priv;
1820 #endif
1821 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1822 if (ret < 0)
1823 goto init_port_hal_free;
1824
1825 #ifdef CONFIG_DEBUG_FS
1826 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1827 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1828 NULL, priv, &port_regs_ops);
1829 #endif
1830
1831 return priv;
1832
1833 init_port_hal_free:
1834 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1835 pch_uart_ports[board->line_no] = NULL;
1836 #endif
1837 free_page((unsigned long)rxbuf);
1838 init_port_free_txbuf:
1839 kfree(priv);
1840 init_port_alloc_err:
1841
1842 return NULL;
1843 }
1844
1845 static void pch_uart_exit_port(struct eg20t_port *priv)
1846 {
1847
1848 #ifdef CONFIG_DEBUG_FS
1849 debugfs_remove(priv->debugfs);
1850 #endif
1851 uart_remove_one_port(&pch_uart_driver, &priv->port);
1852 free_page((unsigned long)priv->rxbuf.buf);
1853 }
1854
1855 static void pch_uart_pci_remove(struct pci_dev *pdev)
1856 {
1857 struct eg20t_port *priv = pci_get_drvdata(pdev);
1858
1859 pci_disable_msi(pdev);
1860
1861 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1862 pch_uart_ports[priv->port.line] = NULL;
1863 #endif
1864 pch_uart_exit_port(priv);
1865 pci_disable_device(pdev);
1866 kfree(priv);
1867 return;
1868 }
1869 #ifdef CONFIG_PM
1870 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1871 {
1872 struct eg20t_port *priv = pci_get_drvdata(pdev);
1873
1874 uart_suspend_port(&pch_uart_driver, &priv->port);
1875
1876 pci_save_state(pdev);
1877 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1878 return 0;
1879 }
1880
1881 static int pch_uart_pci_resume(struct pci_dev *pdev)
1882 {
1883 struct eg20t_port *priv = pci_get_drvdata(pdev);
1884 int ret;
1885
1886 pci_set_power_state(pdev, PCI_D0);
1887 pci_restore_state(pdev);
1888
1889 ret = pci_enable_device(pdev);
1890 if (ret) {
1891 dev_err(&pdev->dev,
1892 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1893 return ret;
1894 }
1895
1896 uart_resume_port(&pch_uart_driver, &priv->port);
1897
1898 return 0;
1899 }
1900 #else
1901 #define pch_uart_pci_suspend NULL
1902 #define pch_uart_pci_resume NULL
1903 #endif
1904
1905 static const struct pci_device_id pch_uart_pci_id[] = {
1906 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1907 .driver_data = pch_et20t_uart0},
1908 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1909 .driver_data = pch_et20t_uart1},
1910 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1911 .driver_data = pch_et20t_uart2},
1912 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1913 .driver_data = pch_et20t_uart3},
1914 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1915 .driver_data = pch_ml7213_uart0},
1916 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1917 .driver_data = pch_ml7213_uart1},
1918 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1919 .driver_data = pch_ml7213_uart2},
1920 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1921 .driver_data = pch_ml7223_uart0},
1922 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1923 .driver_data = pch_ml7223_uart1},
1924 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1925 .driver_data = pch_ml7831_uart0},
1926 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1927 .driver_data = pch_ml7831_uart1},
1928 {0,},
1929 };
1930
1931 static int pch_uart_pci_probe(struct pci_dev *pdev,
1932 const struct pci_device_id *id)
1933 {
1934 int ret;
1935 struct eg20t_port *priv;
1936
1937 ret = pci_enable_device(pdev);
1938 if (ret < 0)
1939 goto probe_error;
1940
1941 priv = pch_uart_init_port(pdev, id);
1942 if (!priv) {
1943 ret = -EBUSY;
1944 goto probe_disable_device;
1945 }
1946 pci_set_drvdata(pdev, priv);
1947
1948 return ret;
1949
1950 probe_disable_device:
1951 pci_disable_msi(pdev);
1952 pci_disable_device(pdev);
1953 probe_error:
1954 return ret;
1955 }
1956
1957 static struct pci_driver pch_uart_pci_driver = {
1958 .name = "pch_uart",
1959 .id_table = pch_uart_pci_id,
1960 .probe = pch_uart_pci_probe,
1961 .remove = pch_uart_pci_remove,
1962 .suspend = pch_uart_pci_suspend,
1963 .resume = pch_uart_pci_resume,
1964 };
1965
1966 static int __init pch_uart_module_init(void)
1967 {
1968 int ret;
1969
1970 /* register as UART driver */
1971 ret = uart_register_driver(&pch_uart_driver);
1972 if (ret < 0)
1973 return ret;
1974
1975 /* register as PCI driver */
1976 ret = pci_register_driver(&pch_uart_pci_driver);
1977 if (ret < 0)
1978 uart_unregister_driver(&pch_uart_driver);
1979
1980 return ret;
1981 }
1982 module_init(pch_uart_module_init);
1983
1984 static void __exit pch_uart_module_exit(void)
1985 {
1986 pci_unregister_driver(&pch_uart_pci_driver);
1987 uart_unregister_driver(&pch_uart_driver);
1988 }
1989 module_exit(pch_uart_module_exit);
1990
1991 MODULE_LICENSE("GPL v2");
1992 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1993 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1994
1995 module_param(default_baud, uint, S_IRUGO);
1996 MODULE_PARM_DESC(default_baud,
1997 "Default BAUD for initial driver state and console (default 9600)");
1998 module_param(user_uartclk, uint, S_IRUGO);
1999 MODULE_PARM_DESC(user_uartclk,
2000 "Override UART default or board specific UART clock");
Linux with added FPC-III support