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Linux 4.19.133
[linux/fpc-iii.git] / drivers / tty / serial / sh-sci.c
blob8aaa7900927a83393ab0d5b903eadc276c83c26e
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #undef DEBUG
23
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
39 #include <linux/mm.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #include "serial_mctrl_gpio.h"
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 };
74
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
81 enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 SCI_NUM_CLKS
87 };
88
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
105 struct plat_sci_reg {
106 u8 offset, size;
107 };
108
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
117 };
118
119 struct sci_port {
120 struct uart_port port;
121
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
128
129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
132
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
135
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
138
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
148 void *rx_buf[2];
149 size_t buf_len_rx;
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
153 #endif
154 unsigned int rx_frame;
155 int rx_trigger;
156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
158 u16 hscif_tot;
159
160 bool has_rtscts;
161 bool autorts;
162 };
163
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
169
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
172 {
173 return container_of(uart, struct sci_port, port);
174 }
175
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 },
197
198 /*
199 * Common definitions for legacy IrDA ports.
200 */
201 [SCIx_IRDA_REGTYPE] = {
202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 },
268
269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
292 },
293
294 /*
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321 /*
322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 },
359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
414 },
415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
489 .fifosize = 64,
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 },
496 };
497
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499
500 /*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
507 {
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518 }
519
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
521 {
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530 }
531
532 static void sci_port_enable(struct sci_port *sci_port)
533 {
534 unsigned int i;
535
536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546 }
547
548 static void sci_port_disable(struct sci_port *sci_port)
549 {
550 unsigned int i;
551
552 if (!sci_port->port.dev)
553 return;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559 }
560
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 {
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 }
572
573 static void sci_start_tx(struct uart_port *port)
574 {
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594 #endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601 }
602
603 static void sci_stop_tx(struct uart_port *port)
604 {
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616 }
617
618 static void sci_start_rx(struct uart_port *port)
619 {
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628 }
629
630 static void sci_stop_rx(struct uart_port *port)
631 {
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642 }
643
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645 {
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658 }
659
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
665 {
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683 /* Dummy read */
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688 }
689 #endif
690
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692 {
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701 }
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
704
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706 {
707 struct sci_port *s = to_sci_port(port);
708
709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
742
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
752 }
753 }
754
755 static int sci_txfill(struct uart_port *port)
756 {
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
763 return serial_port_in(port, SCTFDR) & fifo_mask;
764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
767 return serial_port_in(port, SCFDR) >> 8;
768
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
770 }
771
772 static int sci_txroom(struct uart_port *port)
773 {
774 return port->fifosize - sci_txfill(port);
775 }
776
777 static int sci_rxfill(struct uart_port *port)
778 {
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
785 return serial_port_in(port, SCRFDR) & fifo_mask;
786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
789 return serial_port_in(port, SCFDR) & fifo_mask;
790
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
792 }
793
794 /* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
798 static void sci_transmit_chars(struct uart_port *port)
799 {
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
803 unsigned short ctrl;
804 int count;
805
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
810 ctrl &= ~SCSCR_TIE;
811 else
812 ctrl |= SCSCR_TIE;
813 serial_port_out(port, SCSCR, ctrl);
814 return;
815 }
816
817 count = sci_txroom(port);
818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
832 serial_port_out(port, SCxTDR, c);
833
834 port->icount.tx++;
835 } while (--count > 0);
836
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit))
842 sci_stop_tx(port);
843
844 }
845
846 /* On SH3, SCIF may read end-of-break as a space->mark char */
847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
848
849 static void sci_receive_chars(struct uart_port *port)
850 {
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
854 unsigned char flag;
855
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
861 /* Don't copy more bytes than there is room for in the buffer */
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
863
864 /* If for any reason we can't copy more data, we're done! */
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c))
871 count = 0;
872 else
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
874 } else {
875 for (i = 0; i < count; i++) {
876 char c;
877
878 if (port->type == PORT_SCIF ||
879 port->type == PORT_HSCIF) {
880 status = serial_port_in(port, SCxSR);
881 c = serial_port_in(port, SCxRDR);
882 } else {
883 c = serial_port_in(port, SCxRDR);
884 status = serial_port_in(port, SCxSR);
885 }
886 if (uart_handle_sysrq_char(port, c)) {
887 count--; i--;
888 continue;
889 }
890
891 /* Store data and status */
892 if (status & SCxSR_FER(port)) {
893 flag = TTY_FRAME;
894 port->icount.frame++;
895 dev_notice(port->dev, "frame error\n");
896 } else if (status & SCxSR_PER(port)) {
897 flag = TTY_PARITY;
898 port->icount.parity++;
899 dev_notice(port->dev, "parity error\n");
900 } else
901 flag = TTY_NORMAL;
902
903 tty_insert_flip_char(tport, c, flag);
904 }
905 }
906
907 serial_port_in(port, SCxSR); /* dummy read */
908 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
909
910 copied += count;
911 port->icount.rx += count;
912 }
913
914 if (copied) {
915 /* Tell the rest of the system the news. New characters! */
916 tty_flip_buffer_push(tport);
917 } else {
918 /* TTY buffers full; read from RX reg to prevent lockup */
919 serial_port_in(port, SCxRDR);
920 serial_port_in(port, SCxSR); /* dummy read */
921 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
922 }
923 }
924
925 static int sci_handle_errors(struct uart_port *port)
926 {
927 int copied = 0;
928 unsigned short status = serial_port_in(port, SCxSR);
929 struct tty_port *tport = &port->state->port;
930 struct sci_port *s = to_sci_port(port);
931
932 /* Handle overruns */
933 if (status & s->params->overrun_mask) {
934 port->icount.overrun++;
935
936 /* overrun error */
937 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
938 copied++;
939
940 dev_notice(port->dev, "overrun error\n");
941 }
942
943 if (status & SCxSR_FER(port)) {
944 /* frame error */
945 port->icount.frame++;
946
947 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
948 copied++;
949
950 dev_notice(port->dev, "frame error\n");
951 }
952
953 if (status & SCxSR_PER(port)) {
954 /* parity error */
955 port->icount.parity++;
956
957 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
958 copied++;
959
960 dev_notice(port->dev, "parity error\n");
961 }
962
963 if (copied)
964 tty_flip_buffer_push(tport);
965
966 return copied;
967 }
968
969 static int sci_handle_fifo_overrun(struct uart_port *port)
970 {
971 struct tty_port *tport = &port->state->port;
972 struct sci_port *s = to_sci_port(port);
973 const struct plat_sci_reg *reg;
974 int copied = 0;
975 u16 status;
976
977 reg = sci_getreg(port, s->params->overrun_reg);
978 if (!reg->size)
979 return 0;
980
981 status = serial_port_in(port, s->params->overrun_reg);
982 if (status & s->params->overrun_mask) {
983 status &= ~s->params->overrun_mask;
984 serial_port_out(port, s->params->overrun_reg, status);
985
986 port->icount.overrun++;
987
988 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
989 tty_flip_buffer_push(tport);
990
991 dev_dbg(port->dev, "overrun error\n");
992 copied++;
993 }
994
995 return copied;
996 }
997
998 static int sci_handle_breaks(struct uart_port *port)
999 {
1000 int copied = 0;
1001 unsigned short status = serial_port_in(port, SCxSR);
1002 struct tty_port *tport = &port->state->port;
1003
1004 if (uart_handle_break(port))
1005 return 0;
1006
1007 if (status & SCxSR_BRK(port)) {
1008 port->icount.brk++;
1009
1010 /* Notify of BREAK */
1011 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1012 copied++;
1013
1014 dev_dbg(port->dev, "BREAK detected\n");
1015 }
1016
1017 if (copied)
1018 tty_flip_buffer_push(tport);
1019
1020 copied += sci_handle_fifo_overrun(port);
1021
1022 return copied;
1023 }
1024
1025 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1026 {
1027 unsigned int bits;
1028
1029 if (rx_trig < 1)
1030 rx_trig = 1;
1031 if (rx_trig >= port->fifosize)
1032 rx_trig = port->fifosize;
1033
1034 /* HSCIF can be set to an arbitrary level. */
1035 if (sci_getreg(port, HSRTRGR)->size) {
1036 serial_port_out(port, HSRTRGR, rx_trig);
1037 return rx_trig;
1038 }
1039
1040 switch (port->type) {
1041 case PORT_SCIF:
1042 if (rx_trig < 4) {
1043 bits = 0;
1044 rx_trig = 1;
1045 } else if (rx_trig < 8) {
1046 bits = SCFCR_RTRG0;
1047 rx_trig = 4;
1048 } else if (rx_trig < 14) {
1049 bits = SCFCR_RTRG1;
1050 rx_trig = 8;
1051 } else {
1052 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1053 rx_trig = 14;
1054 }
1055 break;
1056 case PORT_SCIFA:
1057 case PORT_SCIFB:
1058 if (rx_trig < 16) {
1059 bits = 0;
1060 rx_trig = 1;
1061 } else if (rx_trig < 32) {
1062 bits = SCFCR_RTRG0;
1063 rx_trig = 16;
1064 } else if (rx_trig < 48) {
1065 bits = SCFCR_RTRG1;
1066 rx_trig = 32;
1067 } else {
1068 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1069 rx_trig = 48;
1070 }
1071 break;
1072 default:
1073 WARN(1, "unknown FIFO configuration");
1074 return 1;
1075 }
1076
1077 serial_port_out(port, SCFCR,
1078 (serial_port_in(port, SCFCR) &
1079 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1080
1081 return rx_trig;
1082 }
1083
1084 static int scif_rtrg_enabled(struct uart_port *port)
1085 {
1086 if (sci_getreg(port, HSRTRGR)->size)
1087 return serial_port_in(port, HSRTRGR) != 0;
1088 else
1089 return (serial_port_in(port, SCFCR) &
1090 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1091 }
1092
1093 static void rx_fifo_timer_fn(struct timer_list *t)
1094 {
1095 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1096 struct uart_port *port = &s->port;
1097
1098 dev_dbg(port->dev, "Rx timed out\n");
1099 scif_set_rtrg(port, 1);
1100 }
1101
1102 static ssize_t rx_trigger_show(struct device *dev,
1103 struct device_attribute *attr,
1104 char *buf)
1105 {
1106 struct uart_port *port = dev_get_drvdata(dev);
1107 struct sci_port *sci = to_sci_port(port);
1108
1109 return sprintf(buf, "%d\n", sci->rx_trigger);
1110 }
1111
1112 static ssize_t rx_trigger_store(struct device *dev,
1113 struct device_attribute *attr,
1114 const char *buf,
1115 size_t count)
1116 {
1117 struct uart_port *port = dev_get_drvdata(dev);
1118 struct sci_port *sci = to_sci_port(port);
1119 int ret;
1120 long r;
1121
1122 ret = kstrtol(buf, 0, &r);
1123 if (ret)
1124 return ret;
1125
1126 sci->rx_trigger = scif_set_rtrg(port, r);
1127 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1128 scif_set_rtrg(port, 1);
1129
1130 return count;
1131 }
1132
1133 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1134
1135 static ssize_t rx_fifo_timeout_show(struct device *dev,
1136 struct device_attribute *attr,
1137 char *buf)
1138 {
1139 struct uart_port *port = dev_get_drvdata(dev);
1140 struct sci_port *sci = to_sci_port(port);
1141 int v;
1142
1143 if (port->type == PORT_HSCIF)
1144 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1145 else
1146 v = sci->rx_fifo_timeout;
1147
1148 return sprintf(buf, "%d\n", v);
1149 }
1150
1151 static ssize_t rx_fifo_timeout_store(struct device *dev,
1152 struct device_attribute *attr,
1153 const char *buf,
1154 size_t count)
1155 {
1156 struct uart_port *port = dev_get_drvdata(dev);
1157 struct sci_port *sci = to_sci_port(port);
1158 int ret;
1159 long r;
1160
1161 ret = kstrtol(buf, 0, &r);
1162 if (ret)
1163 return ret;
1164
1165 if (port->type == PORT_HSCIF) {
1166 if (r < 0 || r > 3)
1167 return -EINVAL;
1168 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1169 } else {
1170 sci->rx_fifo_timeout = r;
1171 scif_set_rtrg(port, 1);
1172 if (r > 0)
1173 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1174 }
1175
1176 return count;
1177 }
1178
1179 static DEVICE_ATTR_RW(rx_fifo_timeout);
1180
1181
1182 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1183 static void sci_dma_tx_complete(void *arg)
1184 {
1185 struct sci_port *s = arg;
1186 struct uart_port *port = &s->port;
1187 struct circ_buf *xmit = &port->state->xmit;
1188 unsigned long flags;
1189
1190 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1191
1192 spin_lock_irqsave(&port->lock, flags);
1193
1194 xmit->tail += s->tx_dma_len;
1195 xmit->tail &= UART_XMIT_SIZE - 1;
1196
1197 port->icount.tx += s->tx_dma_len;
1198
1199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1200 uart_write_wakeup(port);
1201
1202 if (!uart_circ_empty(xmit)) {
1203 s->cookie_tx = 0;
1204 schedule_work(&s->work_tx);
1205 } else {
1206 s->cookie_tx = -EINVAL;
1207 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1208 u16 ctrl = serial_port_in(port, SCSCR);
1209 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1210 }
1211 }
1212
1213 spin_unlock_irqrestore(&port->lock, flags);
1214 }
1215
1216 /* Locking: called with port lock held */
1217 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1218 {
1219 struct uart_port *port = &s->port;
1220 struct tty_port *tport = &port->state->port;
1221 int copied;
1222
1223 copied = tty_insert_flip_string(tport, buf, count);
1224 if (copied < count)
1225 port->icount.buf_overrun++;
1226
1227 port->icount.rx += copied;
1228
1229 return copied;
1230 }
1231
1232 static int sci_dma_rx_find_active(struct sci_port *s)
1233 {
1234 unsigned int i;
1235
1236 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1237 if (s->active_rx == s->cookie_rx[i])
1238 return i;
1239
1240 return -1;
1241 }
1242
1243 static void sci_rx_dma_release(struct sci_port *s)
1244 {
1245 struct dma_chan *chan = s->chan_rx_saved;
1246
1247 s->chan_rx_saved = s->chan_rx = NULL;
1248 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1249 dmaengine_terminate_sync(chan);
1250 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1251 sg_dma_address(&s->sg_rx[0]));
1252 dma_release_channel(chan);
1253 }
1254
1255 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1256 {
1257 long sec = usec / 1000000;
1258 long nsec = (usec % 1000000) * 1000;
1259 ktime_t t = ktime_set(sec, nsec);
1260
1261 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1262 }
1263
1264 static void sci_dma_rx_complete(void *arg)
1265 {
1266 struct sci_port *s = arg;
1267 struct dma_chan *chan = s->chan_rx;
1268 struct uart_port *port = &s->port;
1269 struct dma_async_tx_descriptor *desc;
1270 unsigned long flags;
1271 int active, count = 0;
1272
1273 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1274 s->active_rx);
1275
1276 spin_lock_irqsave(&port->lock, flags);
1277
1278 active = sci_dma_rx_find_active(s);
1279 if (active >= 0)
1280 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1281
1282 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1283
1284 if (count)
1285 tty_flip_buffer_push(&port->state->port);
1286
1287 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1288 DMA_DEV_TO_MEM,
1289 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1290 if (!desc)
1291 goto fail;
1292
1293 desc->callback = sci_dma_rx_complete;
1294 desc->callback_param = s;
1295 s->cookie_rx[active] = dmaengine_submit(desc);
1296 if (dma_submit_error(s->cookie_rx[active]))
1297 goto fail;
1298
1299 s->active_rx = s->cookie_rx[!active];
1300
1301 dma_async_issue_pending(chan);
1302
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1305 __func__, s->cookie_rx[active], active, s->active_rx);
1306 return;
1307
1308 fail:
1309 spin_unlock_irqrestore(&port->lock, flags);
1310 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1311 /* Switch to PIO */
1312 spin_lock_irqsave(&port->lock, flags);
1313 s->chan_rx = NULL;
1314 sci_start_rx(port);
1315 spin_unlock_irqrestore(&port->lock, flags);
1316 }
1317
1318 static void sci_tx_dma_release(struct sci_port *s)
1319 {
1320 struct dma_chan *chan = s->chan_tx_saved;
1321
1322 cancel_work_sync(&s->work_tx);
1323 s->chan_tx_saved = s->chan_tx = NULL;
1324 s->cookie_tx = -EINVAL;
1325 dmaengine_terminate_sync(chan);
1326 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1327 DMA_TO_DEVICE);
1328 dma_release_channel(chan);
1329 }
1330
1331 static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
1332 {
1333 struct dma_chan *chan = s->chan_rx;
1334 struct uart_port *port = &s->port;
1335 unsigned long flags;
1336 int i;
1337
1338 for (i = 0; i < 2; i++) {
1339 struct scatterlist *sg = &s->sg_rx[i];
1340 struct dma_async_tx_descriptor *desc;
1341
1342 desc = dmaengine_prep_slave_sg(chan,
1343 sg, 1, DMA_DEV_TO_MEM,
1344 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1345 if (!desc)
1346 goto fail;
1347
1348 desc->callback = sci_dma_rx_complete;
1349 desc->callback_param = s;
1350 s->cookie_rx[i] = dmaengine_submit(desc);
1351 if (dma_submit_error(s->cookie_rx[i]))
1352 goto fail;
1353
1354 }
1355
1356 s->active_rx = s->cookie_rx[0];
1357
1358 dma_async_issue_pending(chan);
1359 return 0;
1360
1361 fail:
1362 /* Switch to PIO */
1363 if (!port_lock_held)
1364 spin_lock_irqsave(&port->lock, flags);
1365 if (i)
1366 dmaengine_terminate_async(chan);
1367 for (i = 0; i < 2; i++)
1368 s->cookie_rx[i] = -EINVAL;
1369 s->active_rx = 0;
1370 s->chan_rx = NULL;
1371 sci_start_rx(port);
1372 if (!port_lock_held)
1373 spin_unlock_irqrestore(&port->lock, flags);
1374 return -EAGAIN;
1375 }
1376
1377 static void work_fn_tx(struct work_struct *work)
1378 {
1379 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1380 struct dma_async_tx_descriptor *desc;
1381 struct dma_chan *chan = s->chan_tx;
1382 struct uart_port *port = &s->port;
1383 struct circ_buf *xmit = &port->state->xmit;
1384 unsigned long flags;
1385 dma_addr_t buf;
1386 int head, tail;
1387
1388 /*
1389 * DMA is idle now.
1390 * Port xmit buffer is already mapped, and it is one page... Just adjust
1391 * offsets and lengths. Since it is a circular buffer, we have to
1392 * transmit till the end, and then the rest. Take the port lock to get a
1393 * consistent xmit buffer state.
1394 */
1395 spin_lock_irq(&port->lock);
1396 head = xmit->head;
1397 tail = xmit->tail;
1398 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1399 s->tx_dma_len = min_t(unsigned int,
1400 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1401 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1402 if (!s->tx_dma_len) {
1403 /* Transmit buffer has been flushed */
1404 spin_unlock_irq(&port->lock);
1405 return;
1406 }
1407
1408 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1409 DMA_MEM_TO_DEV,
1410 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1411 if (!desc) {
1412 spin_unlock_irq(&port->lock);
1413 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1414 goto switch_to_pio;
1415 }
1416
1417 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1418 DMA_TO_DEVICE);
1419
1420 desc->callback = sci_dma_tx_complete;
1421 desc->callback_param = s;
1422 s->cookie_tx = dmaengine_submit(desc);
1423 if (dma_submit_error(s->cookie_tx)) {
1424 spin_unlock_irq(&port->lock);
1425 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1426 goto switch_to_pio;
1427 }
1428
1429 spin_unlock_irq(&port->lock);
1430 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1431 __func__, xmit->buf, tail, head, s->cookie_tx);
1432
1433 dma_async_issue_pending(chan);
1434 return;
1435
1436 switch_to_pio:
1437 spin_lock_irqsave(&port->lock, flags);
1438 s->chan_tx = NULL;
1439 sci_start_tx(port);
1440 spin_unlock_irqrestore(&port->lock, flags);
1441 return;
1442 }
1443
1444 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1445 {
1446 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1447 struct dma_chan *chan = s->chan_rx;
1448 struct uart_port *port = &s->port;
1449 struct dma_tx_state state;
1450 enum dma_status status;
1451 unsigned long flags;
1452 unsigned int read;
1453 int active, count;
1454 u16 scr;
1455
1456 dev_dbg(port->dev, "DMA Rx timed out\n");
1457
1458 spin_lock_irqsave(&port->lock, flags);
1459
1460 active = sci_dma_rx_find_active(s);
1461 if (active < 0) {
1462 spin_unlock_irqrestore(&port->lock, flags);
1463 return HRTIMER_NORESTART;
1464 }
1465
1466 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1467 if (status == DMA_COMPLETE) {
1468 spin_unlock_irqrestore(&port->lock, flags);
1469 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1470 s->active_rx, active);
1471
1472 /* Let packet complete handler take care of the packet */
1473 return HRTIMER_NORESTART;
1474 }
1475
1476 dmaengine_pause(chan);
1477
1478 /*
1479 * sometimes DMA transfer doesn't stop even if it is stopped and
1480 * data keeps on coming until transaction is complete so check
1481 * for DMA_COMPLETE again
1482 * Let packet complete handler take care of the packet
1483 */
1484 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1485 if (status == DMA_COMPLETE) {
1486 spin_unlock_irqrestore(&port->lock, flags);
1487 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1488 return HRTIMER_NORESTART;
1489 }
1490
1491 /* Handle incomplete DMA receive */
1492 dmaengine_terminate_async(s->chan_rx);
1493 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1494
1495 if (read) {
1496 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1497 if (count)
1498 tty_flip_buffer_push(&port->state->port);
1499 }
1500
1501 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1502 sci_submit_rx(s, true);
1503
1504 /* Direct new serial port interrupts back to CPU */
1505 scr = serial_port_in(port, SCSCR);
1506 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1507 scr &= ~SCSCR_RDRQE;
1508 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1509 }
1510 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1511
1512 spin_unlock_irqrestore(&port->lock, flags);
1513
1514 return HRTIMER_NORESTART;
1515 }
1516
1517 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1518 enum dma_transfer_direction dir)
1519 {
1520 struct dma_chan *chan;
1521 struct dma_slave_config cfg;
1522 int ret;
1523
1524 chan = dma_request_slave_channel(port->dev,
1525 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1526 if (!chan) {
1527 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1528 return NULL;
1529 }
1530
1531 memset(&cfg, 0, sizeof(cfg));
1532 cfg.direction = dir;
1533 if (dir == DMA_MEM_TO_DEV) {
1534 cfg.dst_addr = port->mapbase +
1535 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1537 } else {
1538 cfg.src_addr = port->mapbase +
1539 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1540 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1541 }
1542
1543 ret = dmaengine_slave_config(chan, &cfg);
1544 if (ret) {
1545 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1546 dma_release_channel(chan);
1547 return NULL;
1548 }
1549
1550 return chan;
1551 }
1552
1553 static void sci_request_dma(struct uart_port *port)
1554 {
1555 struct sci_port *s = to_sci_port(port);
1556 struct dma_chan *chan;
1557
1558 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1559
1560 /*
1561 * DMA on console may interfere with Kernel log messages which use
1562 * plain putchar(). So, simply don't use it with a console.
1563 */
1564 if (uart_console(port))
1565 return;
1566
1567 if (!port->dev->of_node)
1568 return;
1569
1570 s->cookie_tx = -EINVAL;
1571
1572 /*
1573 * Don't request a dma channel if no channel was specified
1574 * in the device tree.
1575 */
1576 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1577 return;
1578
1579 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1580 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1581 if (chan) {
1582 /* UART circular tx buffer is an aligned page. */
1583 s->tx_dma_addr = dma_map_single(chan->device->dev,
1584 port->state->xmit.buf,
1585 UART_XMIT_SIZE,
1586 DMA_TO_DEVICE);
1587 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1588 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1589 dma_release_channel(chan);
1590 } else {
1591 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1592 __func__, UART_XMIT_SIZE,
1593 port->state->xmit.buf, &s->tx_dma_addr);
1594
1595 INIT_WORK(&s->work_tx, work_fn_tx);
1596 s->chan_tx_saved = s->chan_tx = chan;
1597 }
1598 }
1599
1600 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1601 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1602 if (chan) {
1603 unsigned int i;
1604 dma_addr_t dma;
1605 void *buf;
1606
1607 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1608 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1609 &dma, GFP_KERNEL);
1610 if (!buf) {
1611 dev_warn(port->dev,
1612 "Failed to allocate Rx dma buffer, using PIO\n");
1613 dma_release_channel(chan);
1614 return;
1615 }
1616
1617 for (i = 0; i < 2; i++) {
1618 struct scatterlist *sg = &s->sg_rx[i];
1619
1620 sg_init_table(sg, 1);
1621 s->rx_buf[i] = buf;
1622 sg_dma_address(sg) = dma;
1623 sg_dma_len(sg) = s->buf_len_rx;
1624
1625 buf += s->buf_len_rx;
1626 dma += s->buf_len_rx;
1627 }
1628
1629 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1630 s->rx_timer.function = rx_timer_fn;
1631
1632 s->chan_rx_saved = s->chan_rx = chan;
1633
1634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1635 sci_submit_rx(s, false);
1636 }
1637 }
1638
1639 static void sci_free_dma(struct uart_port *port)
1640 {
1641 struct sci_port *s = to_sci_port(port);
1642
1643 if (s->chan_tx_saved)
1644 sci_tx_dma_release(s);
1645 if (s->chan_rx_saved)
1646 sci_rx_dma_release(s);
1647 }
1648
1649 static void sci_flush_buffer(struct uart_port *port)
1650 {
1651 struct sci_port *s = to_sci_port(port);
1652
1653 /*
1654 * In uart_flush_buffer(), the xmit circular buffer has just been
1655 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1656 * pending transfers
1657 */
1658 s->tx_dma_len = 0;
1659 if (s->chan_tx) {
1660 dmaengine_terminate_async(s->chan_tx);
1661 s->cookie_tx = -EINVAL;
1662 }
1663 }
1664 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1665 static inline void sci_request_dma(struct uart_port *port)
1666 {
1667 }
1668
1669 static inline void sci_free_dma(struct uart_port *port)
1670 {
1671 }
1672
1673 #define sci_flush_buffer NULL
1674 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1675
1676 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1677 {
1678 struct uart_port *port = ptr;
1679 struct sci_port *s = to_sci_port(port);
1680
1681 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1682 if (s->chan_rx) {
1683 u16 scr = serial_port_in(port, SCSCR);
1684 u16 ssr = serial_port_in(port, SCxSR);
1685
1686 /* Disable future Rx interrupts */
1687 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1688 disable_irq_nosync(irq);
1689 scr |= SCSCR_RDRQE;
1690 } else {
1691 if (sci_submit_rx(s, false) < 0)
1692 goto handle_pio;
1693
1694 scr &= ~SCSCR_RIE;
1695 }
1696 serial_port_out(port, SCSCR, scr);
1697 /* Clear current interrupt */
1698 serial_port_out(port, SCxSR,
1699 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1700 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1701 jiffies, s->rx_timeout);
1702 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1703
1704 return IRQ_HANDLED;
1705 }
1706
1707 handle_pio:
1708 #endif
1709
1710 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1711 if (!scif_rtrg_enabled(port))
1712 scif_set_rtrg(port, s->rx_trigger);
1713
1714 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1715 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1716 }
1717
1718 /* I think sci_receive_chars has to be called irrespective
1719 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1720 * to be disabled?
1721 */
1722 sci_receive_chars(ptr);
1723
1724 return IRQ_HANDLED;
1725 }
1726
1727 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1728 {
1729 struct uart_port *port = ptr;
1730 unsigned long flags;
1731
1732 spin_lock_irqsave(&port->lock, flags);
1733 sci_transmit_chars(port);
1734 spin_unlock_irqrestore(&port->lock, flags);
1735
1736 return IRQ_HANDLED;
1737 }
1738
1739 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1740 {
1741 struct uart_port *port = ptr;
1742
1743 /* Handle BREAKs */
1744 sci_handle_breaks(port);
1745 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1746
1747 return IRQ_HANDLED;
1748 }
1749
1750 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1751 {
1752 struct uart_port *port = ptr;
1753 struct sci_port *s = to_sci_port(port);
1754
1755 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1756 /* Break and Error interrupts are muxed */
1757 unsigned short ssr_status = serial_port_in(port, SCxSR);
1758
1759 /* Break Interrupt */
1760 if (ssr_status & SCxSR_BRK(port))
1761 sci_br_interrupt(irq, ptr);
1762
1763 /* Break only? */
1764 if (!(ssr_status & SCxSR_ERRORS(port)))
1765 return IRQ_HANDLED;
1766 }
1767
1768 /* Handle errors */
1769 if (port->type == PORT_SCI) {
1770 if (sci_handle_errors(port)) {
1771 /* discard character in rx buffer */
1772 serial_port_in(port, SCxSR);
1773 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1774 }
1775 } else {
1776 sci_handle_fifo_overrun(port);
1777 if (!s->chan_rx)
1778 sci_receive_chars(ptr);
1779 }
1780
1781 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1782
1783 /* Kick the transmission */
1784 if (!s->chan_tx)
1785 sci_tx_interrupt(irq, ptr);
1786
1787 return IRQ_HANDLED;
1788 }
1789
1790 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1791 {
1792 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1793 struct uart_port *port = ptr;
1794 struct sci_port *s = to_sci_port(port);
1795 irqreturn_t ret = IRQ_NONE;
1796
1797 ssr_status = serial_port_in(port, SCxSR);
1798 scr_status = serial_port_in(port, SCSCR);
1799 if (s->params->overrun_reg == SCxSR)
1800 orer_status = ssr_status;
1801 else if (sci_getreg(port, s->params->overrun_reg)->size)
1802 orer_status = serial_port_in(port, s->params->overrun_reg);
1803
1804 err_enabled = scr_status & port_rx_irq_mask(port);
1805
1806 /* Tx Interrupt */
1807 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1808 !s->chan_tx)
1809 ret = sci_tx_interrupt(irq, ptr);
1810
1811 /*
1812 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1813 * DR flags
1814 */
1815 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1816 (scr_status & SCSCR_RIE))
1817 ret = sci_rx_interrupt(irq, ptr);
1818
1819 /* Error Interrupt */
1820 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1821 ret = sci_er_interrupt(irq, ptr);
1822
1823 /* Break Interrupt */
1824 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1825 ret = sci_br_interrupt(irq, ptr);
1826
1827 /* Overrun Interrupt */
1828 if (orer_status & s->params->overrun_mask) {
1829 sci_handle_fifo_overrun(port);
1830 ret = IRQ_HANDLED;
1831 }
1832
1833 return ret;
1834 }
1835
1836 static const struct sci_irq_desc {
1837 const char *desc;
1838 irq_handler_t handler;
1839 } sci_irq_desc[] = {
1840 /*
1841 * Split out handlers, the default case.
1842 */
1843 [SCIx_ERI_IRQ] = {
1844 .desc = "rx err",
1845 .handler = sci_er_interrupt,
1846 },
1847
1848 [SCIx_RXI_IRQ] = {
1849 .desc = "rx full",
1850 .handler = sci_rx_interrupt,
1851 },
1852
1853 [SCIx_TXI_IRQ] = {
1854 .desc = "tx empty",
1855 .handler = sci_tx_interrupt,
1856 },
1857
1858 [SCIx_BRI_IRQ] = {
1859 .desc = "break",
1860 .handler = sci_br_interrupt,
1861 },
1862
1863 [SCIx_DRI_IRQ] = {
1864 .desc = "rx ready",
1865 .handler = sci_rx_interrupt,
1866 },
1867
1868 [SCIx_TEI_IRQ] = {
1869 .desc = "tx end",
1870 .handler = sci_tx_interrupt,
1871 },
1872
1873 /*
1874 * Special muxed handler.
1875 */
1876 [SCIx_MUX_IRQ] = {
1877 .desc = "mux",
1878 .handler = sci_mpxed_interrupt,
1879 },
1880 };
1881
1882 static int sci_request_irq(struct sci_port *port)
1883 {
1884 struct uart_port *up = &port->port;
1885 int i, j, w, ret = 0;
1886
1887 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1888 const struct sci_irq_desc *desc;
1889 int irq;
1890
1891 /* Check if already registered (muxed) */
1892 for (w = 0; w < i; w++)
1893 if (port->irqs[w] == port->irqs[i])
1894 w = i + 1;
1895 if (w > i)
1896 continue;
1897
1898 if (SCIx_IRQ_IS_MUXED(port)) {
1899 i = SCIx_MUX_IRQ;
1900 irq = up->irq;
1901 } else {
1902 irq = port->irqs[i];
1903
1904 /*
1905 * Certain port types won't support all of the
1906 * available interrupt sources.
1907 */
1908 if (unlikely(irq < 0))
1909 continue;
1910 }
1911
1912 desc = sci_irq_desc + i;
1913 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1914 dev_name(up->dev), desc->desc);
1915 if (!port->irqstr[j]) {
1916 ret = -ENOMEM;
1917 goto out_nomem;
1918 }
1919
1920 ret = request_irq(irq, desc->handler, up->irqflags,
1921 port->irqstr[j], port);
1922 if (unlikely(ret)) {
1923 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1924 goto out_noirq;
1925 }
1926 }
1927
1928 return 0;
1929
1930 out_noirq:
1931 while (--i >= 0)
1932 free_irq(port->irqs[i], port);
1933
1934 out_nomem:
1935 while (--j >= 0)
1936 kfree(port->irqstr[j]);
1937
1938 return ret;
1939 }
1940
1941 static void sci_free_irq(struct sci_port *port)
1942 {
1943 int i, j;
1944
1945 /*
1946 * Intentionally in reverse order so we iterate over the muxed
1947 * IRQ first.
1948 */
1949 for (i = 0; i < SCIx_NR_IRQS; i++) {
1950 int irq = port->irqs[i];
1951
1952 /*
1953 * Certain port types won't support all of the available
1954 * interrupt sources.
1955 */
1956 if (unlikely(irq < 0))
1957 continue;
1958
1959 /* Check if already freed (irq was muxed) */
1960 for (j = 0; j < i; j++)
1961 if (port->irqs[j] == irq)
1962 j = i + 1;
1963 if (j > i)
1964 continue;
1965
1966 free_irq(port->irqs[i], port);
1967 kfree(port->irqstr[i]);
1968
1969 if (SCIx_IRQ_IS_MUXED(port)) {
1970 /* If there's only one IRQ, we're done. */
1971 return;
1972 }
1973 }
1974 }
1975
1976 static unsigned int sci_tx_empty(struct uart_port *port)
1977 {
1978 unsigned short status = serial_port_in(port, SCxSR);
1979 unsigned short in_tx_fifo = sci_txfill(port);
1980
1981 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1982 }
1983
1984 static void sci_set_rts(struct uart_port *port, bool state)
1985 {
1986 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1987 u16 data = serial_port_in(port, SCPDR);
1988
1989 /* Active low */
1990 if (state)
1991 data &= ~SCPDR_RTSD;
1992 else
1993 data |= SCPDR_RTSD;
1994 serial_port_out(port, SCPDR, data);
1995
1996 /* RTS# is output */
1997 serial_port_out(port, SCPCR,
1998 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1999 } else if (sci_getreg(port, SCSPTR)->size) {
2000 u16 ctrl = serial_port_in(port, SCSPTR);
2001
2002 /* Active low */
2003 if (state)
2004 ctrl &= ~SCSPTR_RTSDT;
2005 else
2006 ctrl |= SCSPTR_RTSDT;
2007 serial_port_out(port, SCSPTR, ctrl);
2008 }
2009 }
2010
2011 static bool sci_get_cts(struct uart_port *port)
2012 {
2013 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2014 /* Active low */
2015 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2016 } else if (sci_getreg(port, SCSPTR)->size) {
2017 /* Active low */
2018 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2019 }
2020
2021 return true;
2022 }
2023
2024 /*
2025 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2026 * CTS/RTS is supported in hardware by at least one port and controlled
2027 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2028 * handled via the ->init_pins() op, which is a bit of a one-way street,
2029 * lacking any ability to defer pin control -- this will later be
2030 * converted over to the GPIO framework).
2031 *
2032 * Other modes (such as loopback) are supported generically on certain
2033 * port types, but not others. For these it's sufficient to test for the
2034 * existence of the support register and simply ignore the port type.
2035 */
2036 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2037 {
2038 struct sci_port *s = to_sci_port(port);
2039
2040 if (mctrl & TIOCM_LOOP) {
2041 const struct plat_sci_reg *reg;
2042
2043 /*
2044 * Standard loopback mode for SCFCR ports.
2045 */
2046 reg = sci_getreg(port, SCFCR);
2047 if (reg->size)
2048 serial_port_out(port, SCFCR,
2049 serial_port_in(port, SCFCR) |
2050 SCFCR_LOOP);
2051 }
2052
2053 mctrl_gpio_set(s->gpios, mctrl);
2054
2055 if (!s->has_rtscts)
2056 return;
2057
2058 if (!(mctrl & TIOCM_RTS)) {
2059 /* Disable Auto RTS */
2060 serial_port_out(port, SCFCR,
2061 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2062
2063 /* Clear RTS */
2064 sci_set_rts(port, 0);
2065 } else if (s->autorts) {
2066 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2067 /* Enable RTS# pin function */
2068 serial_port_out(port, SCPCR,
2069 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2070 }
2071
2072 /* Enable Auto RTS */
2073 serial_port_out(port, SCFCR,
2074 serial_port_in(port, SCFCR) | SCFCR_MCE);
2075 } else {
2076 /* Set RTS */
2077 sci_set_rts(port, 1);
2078 }
2079 }
2080
2081 static unsigned int sci_get_mctrl(struct uart_port *port)
2082 {
2083 struct sci_port *s = to_sci_port(port);
2084 struct mctrl_gpios *gpios = s->gpios;
2085 unsigned int mctrl = 0;
2086
2087 mctrl_gpio_get(gpios, &mctrl);
2088
2089 /*
2090 * CTS/RTS is handled in hardware when supported, while nothing
2091 * else is wired up.
2092 */
2093 if (s->autorts) {
2094 if (sci_get_cts(port))
2095 mctrl |= TIOCM_CTS;
2096 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2097 mctrl |= TIOCM_CTS;
2098 }
2099 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2100 mctrl |= TIOCM_DSR;
2101 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2102 mctrl |= TIOCM_CAR;
2103
2104 return mctrl;
2105 }
2106
2107 static void sci_enable_ms(struct uart_port *port)
2108 {
2109 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2110 }
2111
2112 static void sci_break_ctl(struct uart_port *port, int break_state)
2113 {
2114 unsigned short scscr, scsptr;
2115 unsigned long flags;
2116
2117 /* check wheter the port has SCSPTR */
2118 if (!sci_getreg(port, SCSPTR)->size) {
2119 /*
2120 * Not supported by hardware. Most parts couple break and rx
2121 * interrupts together, with break detection always enabled.
2122 */
2123 return;
2124 }
2125
2126 spin_lock_irqsave(&port->lock, flags);
2127 scsptr = serial_port_in(port, SCSPTR);
2128 scscr = serial_port_in(port, SCSCR);
2129
2130 if (break_state == -1) {
2131 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2132 scscr &= ~SCSCR_TE;
2133 } else {
2134 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2135 scscr |= SCSCR_TE;
2136 }
2137
2138 serial_port_out(port, SCSPTR, scsptr);
2139 serial_port_out(port, SCSCR, scscr);
2140 spin_unlock_irqrestore(&port->lock, flags);
2141 }
2142
2143 static int sci_startup(struct uart_port *port)
2144 {
2145 struct sci_port *s = to_sci_port(port);
2146 int ret;
2147
2148 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2149
2150 sci_request_dma(port);
2151
2152 ret = sci_request_irq(s);
2153 if (unlikely(ret < 0)) {
2154 sci_free_dma(port);
2155 return ret;
2156 }
2157
2158 return 0;
2159 }
2160
2161 static void sci_shutdown(struct uart_port *port)
2162 {
2163 struct sci_port *s = to_sci_port(port);
2164 unsigned long flags;
2165 u16 scr;
2166
2167 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2168
2169 s->autorts = false;
2170 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2171
2172 spin_lock_irqsave(&port->lock, flags);
2173 sci_stop_rx(port);
2174 sci_stop_tx(port);
2175 /*
2176 * Stop RX and TX, disable related interrupts, keep clock source
2177 * and HSCIF TOT bits
2178 */
2179 scr = serial_port_in(port, SCSCR);
2180 serial_port_out(port, SCSCR, scr &
2181 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2182 spin_unlock_irqrestore(&port->lock, flags);
2183
2184 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2185 if (s->chan_rx_saved) {
2186 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2187 port->line);
2188 hrtimer_cancel(&s->rx_timer);
2189 }
2190 #endif
2191
2192 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2193 del_timer_sync(&s->rx_fifo_timer);
2194 sci_free_irq(s);
2195 sci_free_dma(port);
2196 }
2197
2198 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2199 unsigned int *srr)
2200 {
2201 unsigned long freq = s->clk_rates[SCI_SCK];
2202 int err, min_err = INT_MAX;
2203 unsigned int sr;
2204
2205 if (s->port.type != PORT_HSCIF)
2206 freq *= 2;
2207
2208 for_each_sr(sr, s) {
2209 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2210 if (abs(err) >= abs(min_err))
2211 continue;
2212
2213 min_err = err;
2214 *srr = sr - 1;
2215
2216 if (!err)
2217 break;
2218 }
2219
2220 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2221 *srr + 1);
2222 return min_err;
2223 }
2224
2225 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2226 unsigned long freq, unsigned int *dlr,
2227 unsigned int *srr)
2228 {
2229 int err, min_err = INT_MAX;
2230 unsigned int sr, dl;
2231
2232 if (s->port.type != PORT_HSCIF)
2233 freq *= 2;
2234
2235 for_each_sr(sr, s) {
2236 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2237 dl = clamp(dl, 1U, 65535U);
2238
2239 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2240 if (abs(err) >= abs(min_err))
2241 continue;
2242
2243 min_err = err;
2244 *dlr = dl;
2245 *srr = sr - 1;
2246
2247 if (!err)
2248 break;
2249 }
2250
2251 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2252 min_err, *dlr, *srr + 1);
2253 return min_err;
2254 }
2255
2256 /* calculate sample rate, BRR, and clock select */
2257 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2258 unsigned int *brr, unsigned int *srr,
2259 unsigned int *cks)
2260 {
2261 unsigned long freq = s->clk_rates[SCI_FCK];
2262 unsigned int sr, br, prediv, scrate, c;
2263 int err, min_err = INT_MAX;
2264
2265 if (s->port.type != PORT_HSCIF)
2266 freq *= 2;
2267
2268 /*
2269 * Find the combination of sample rate and clock select with the
2270 * smallest deviation from the desired baud rate.
2271 * Prefer high sample rates to maximise the receive margin.
2272 *
2273 * M: Receive margin (%)
2274 * N: Ratio of bit rate to clock (N = sampling rate)
2275 * D: Clock duty (D = 0 to 1.0)
2276 * L: Frame length (L = 9 to 12)
2277 * F: Absolute value of clock frequency deviation
2278 *
2279 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2280 * (|D - 0.5| / N * (1 + F))|
2281 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2282 */
2283 for_each_sr(sr, s) {
2284 for (c = 0; c <= 3; c++) {
2285 /* integerized formulas from HSCIF documentation */
2286 prediv = sr * (1 << (2 * c + 1));
2287
2288 /*
2289 * We need to calculate:
2290 *
2291 * br = freq / (prediv * bps) clamped to [1..256]
2292 * err = freq / (br * prediv) - bps
2293 *
2294 * Watch out for overflow when calculating the desired
2295 * sampling clock rate!
2296 */
2297 if (bps > UINT_MAX / prediv)
2298 break;
2299
2300 scrate = prediv * bps;
2301 br = DIV_ROUND_CLOSEST(freq, scrate);
2302 br = clamp(br, 1U, 256U);
2303
2304 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2305 if (abs(err) >= abs(min_err))
2306 continue;
2307
2308 min_err = err;
2309 *brr = br - 1;
2310 *srr = sr - 1;
2311 *cks = c;
2312
2313 if (!err)
2314 goto found;
2315 }
2316 }
2317
2318 found:
2319 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2320 min_err, *brr, *srr + 1, *cks);
2321 return min_err;
2322 }
2323
2324 static void sci_reset(struct uart_port *port)
2325 {
2326 const struct plat_sci_reg *reg;
2327 unsigned int status;
2328 struct sci_port *s = to_sci_port(port);
2329
2330 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2331
2332 reg = sci_getreg(port, SCFCR);
2333 if (reg->size)
2334 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2335
2336 sci_clear_SCxSR(port,
2337 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2338 SCxSR_BREAK_CLEAR(port));
2339 if (sci_getreg(port, SCLSR)->size) {
2340 status = serial_port_in(port, SCLSR);
2341 status &= ~(SCLSR_TO | SCLSR_ORER);
2342 serial_port_out(port, SCLSR, status);
2343 }
2344
2345 if (s->rx_trigger > 1) {
2346 if (s->rx_fifo_timeout) {
2347 scif_set_rtrg(port, 1);
2348 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2349 } else {
2350 if (port->type == PORT_SCIFA ||
2351 port->type == PORT_SCIFB)
2352 scif_set_rtrg(port, 1);
2353 else
2354 scif_set_rtrg(port, s->rx_trigger);
2355 }
2356 }
2357 }
2358
2359 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2360 struct ktermios *old)
2361 {
2362 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2363 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2364 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2365 struct sci_port *s = to_sci_port(port);
2366 const struct plat_sci_reg *reg;
2367 int min_err = INT_MAX, err;
2368 unsigned long max_freq = 0;
2369 int best_clk = -1;
2370 unsigned long flags;
2371
2372 if ((termios->c_cflag & CSIZE) == CS7)
2373 smr_val |= SCSMR_CHR;
2374 if (termios->c_cflag & PARENB)
2375 smr_val |= SCSMR_PE;
2376 if (termios->c_cflag & PARODD)
2377 smr_val |= SCSMR_PE | SCSMR_ODD;
2378 if (termios->c_cflag & CSTOPB)
2379 smr_val |= SCSMR_STOP;
2380
2381 /*
2382 * earlyprintk comes here early on with port->uartclk set to zero.
2383 * the clock framework is not up and running at this point so here
2384 * we assume that 115200 is the maximum baud rate. please note that
2385 * the baud rate is not programmed during earlyprintk - it is assumed
2386 * that the previous boot loader has enabled required clocks and
2387 * setup the baud rate generator hardware for us already.
2388 */
2389 if (!port->uartclk) {
2390 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2391 goto done;
2392 }
2393
2394 for (i = 0; i < SCI_NUM_CLKS; i++)
2395 max_freq = max(max_freq, s->clk_rates[i]);
2396
2397 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2398 if (!baud)
2399 goto done;
2400
2401 /*
2402 * There can be multiple sources for the sampling clock. Find the one
2403 * that gives us the smallest deviation from the desired baud rate.
2404 */
2405
2406 /* Optional Undivided External Clock */
2407 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2408 port->type != PORT_SCIFB) {
2409 err = sci_sck_calc(s, baud, &srr1);
2410 if (abs(err) < abs(min_err)) {
2411 best_clk = SCI_SCK;
2412 scr_val = SCSCR_CKE1;
2413 sccks = SCCKS_CKS;
2414 min_err = err;
2415 srr = srr1;
2416 if (!err)
2417 goto done;
2418 }
2419 }
2420
2421 /* Optional BRG Frequency Divided External Clock */
2422 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2423 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2424 &srr1);
2425 if (abs(err) < abs(min_err)) {
2426 best_clk = SCI_SCIF_CLK;
2427 scr_val = SCSCR_CKE1;
2428 sccks = 0;
2429 min_err = err;
2430 dl = dl1;
2431 srr = srr1;
2432 if (!err)
2433 goto done;
2434 }
2435 }
2436
2437 /* Optional BRG Frequency Divided Internal Clock */
2438 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2439 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2440 &srr1);
2441 if (abs(err) < abs(min_err)) {
2442 best_clk = SCI_BRG_INT;
2443 scr_val = SCSCR_CKE1;
2444 sccks = SCCKS_XIN;
2445 min_err = err;
2446 dl = dl1;
2447 srr = srr1;
2448 if (!min_err)
2449 goto done;
2450 }
2451 }
2452
2453 /* Divided Functional Clock using standard Bit Rate Register */
2454 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2455 if (abs(err) < abs(min_err)) {
2456 best_clk = SCI_FCK;
2457 scr_val = 0;
2458 min_err = err;
2459 brr = brr1;
2460 srr = srr1;
2461 cks = cks1;
2462 }
2463
2464 done:
2465 if (best_clk >= 0)
2466 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2467 s->clks[best_clk], baud, min_err);
2468
2469 sci_port_enable(s);
2470
2471 /*
2472 * Program the optional External Baud Rate Generator (BRG) first.
2473 * It controls the mux to select (H)SCK or frequency divided clock.
2474 */
2475 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2476 serial_port_out(port, SCDL, dl);
2477 serial_port_out(port, SCCKS, sccks);
2478 }
2479
2480 spin_lock_irqsave(&port->lock, flags);
2481
2482 sci_reset(port);
2483
2484 uart_update_timeout(port, termios->c_cflag, baud);
2485
2486 /* byte size and parity */
2487 switch (termios->c_cflag & CSIZE) {
2488 case CS5:
2489 bits = 7;
2490 break;
2491 case CS6:
2492 bits = 8;
2493 break;
2494 case CS7:
2495 bits = 9;
2496 break;
2497 default:
2498 bits = 10;
2499 break;
2500 }
2501
2502 if (termios->c_cflag & CSTOPB)
2503 bits++;
2504 if (termios->c_cflag & PARENB)
2505 bits++;
2506
2507 if (best_clk >= 0) {
2508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2509 switch (srr + 1) {
2510 case 5: smr_val |= SCSMR_SRC_5; break;
2511 case 7: smr_val |= SCSMR_SRC_7; break;
2512 case 11: smr_val |= SCSMR_SRC_11; break;
2513 case 13: smr_val |= SCSMR_SRC_13; break;
2514 case 16: smr_val |= SCSMR_SRC_16; break;
2515 case 17: smr_val |= SCSMR_SRC_17; break;
2516 case 19: smr_val |= SCSMR_SRC_19; break;
2517 case 27: smr_val |= SCSMR_SRC_27; break;
2518 }
2519 smr_val |= cks;
2520 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2521 serial_port_out(port, SCSMR, smr_val);
2522 serial_port_out(port, SCBRR, brr);
2523 if (sci_getreg(port, HSSRR)->size) {
2524 unsigned int hssrr = srr | HSCIF_SRE;
2525 /* Calculate deviation from intended rate at the
2526 * center of the last stop bit in sampling clocks.
2527 */
2528 int last_stop = bits * 2 - 1;
2529 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2530 (int)(srr + 1),
2531 2 * (int)baud);
2532
2533 if (abs(deviation) >= 2) {
2534 /* At least two sampling clocks off at the
2535 * last stop bit; we can increase the error
2536 * margin by shifting the sampling point.
2537 */
2538 int shift = clamp(deviation / 2, -8, 7);
2539
2540 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2541 HSCIF_SRHP_MASK;
2542 hssrr |= HSCIF_SRDE;
2543 }
2544 serial_port_out(port, HSSRR, hssrr);
2545 }
2546
2547 /* Wait one bit interval */
2548 udelay((1000000 + (baud - 1)) / baud);
2549 } else {
2550 /* Don't touch the bit rate configuration */
2551 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2552 smr_val |= serial_port_in(port, SCSMR) &
2553 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2554 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2555 serial_port_out(port, SCSMR, smr_val);
2556 }
2557
2558 sci_init_pins(port, termios->c_cflag);
2559
2560 port->status &= ~UPSTAT_AUTOCTS;
2561 s->autorts = false;
2562 reg = sci_getreg(port, SCFCR);
2563 if (reg->size) {
2564 unsigned short ctrl = serial_port_in(port, SCFCR);
2565
2566 if ((port->flags & UPF_HARD_FLOW) &&
2567 (termios->c_cflag & CRTSCTS)) {
2568 /* There is no CTS interrupt to restart the hardware */
2569 port->status |= UPSTAT_AUTOCTS;
2570 /* MCE is enabled when RTS is raised */
2571 s->autorts = true;
2572 }
2573
2574 /*
2575 * As we've done a sci_reset() above, ensure we don't
2576 * interfere with the FIFOs while toggling MCE. As the
2577 * reset values could still be set, simply mask them out.
2578 */
2579 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2580
2581 serial_port_out(port, SCFCR, ctrl);
2582 }
2583 if (port->flags & UPF_HARD_FLOW) {
2584 /* Refresh (Auto) RTS */
2585 sci_set_mctrl(port, port->mctrl);
2586 }
2587
2588 scr_val |= SCSCR_RE | SCSCR_TE |
2589 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2590 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2591 if ((srr + 1 == 5) &&
2592 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2593 /*
2594 * In asynchronous mode, when the sampling rate is 1/5, first
2595 * received data may become invalid on some SCIFA and SCIFB.
2596 * To avoid this problem wait more than 1 serial data time (1
2597 * bit time x serial data number) after setting SCSCR.RE = 1.
2598 */
2599 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2600 }
2601
2602 /*
2603 * Calculate delay for 2 DMA buffers (4 FIFO).
2604 * See serial_core.c::uart_update_timeout().
2605 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2606 * function calculates 1 jiffie for the data plus 5 jiffies for the
2607 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2608 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2609 * value obtained by this formula is too small. Therefore, if the value
2610 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2611 */
2612 s->rx_frame = (10000 * bits) / (baud / 100);
2613 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2614 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2615 if (s->rx_timeout < 20)
2616 s->rx_timeout = 20;
2617 #endif
2618
2619 if ((termios->c_cflag & CREAD) != 0)
2620 sci_start_rx(port);
2621
2622 spin_unlock_irqrestore(&port->lock, flags);
2623
2624 sci_port_disable(s);
2625
2626 if (UART_ENABLE_MS(port, termios->c_cflag))
2627 sci_enable_ms(port);
2628 }
2629
2630 static void sci_pm(struct uart_port *port, unsigned int state,
2631 unsigned int oldstate)
2632 {
2633 struct sci_port *sci_port = to_sci_port(port);
2634
2635 switch (state) {
2636 case UART_PM_STATE_OFF:
2637 sci_port_disable(sci_port);
2638 break;
2639 default:
2640 sci_port_enable(sci_port);
2641 break;
2642 }
2643 }
2644
2645 static const char *sci_type(struct uart_port *port)
2646 {
2647 switch (port->type) {
2648 case PORT_IRDA:
2649 return "irda";
2650 case PORT_SCI:
2651 return "sci";
2652 case PORT_SCIF:
2653 return "scif";
2654 case PORT_SCIFA:
2655 return "scifa";
2656 case PORT_SCIFB:
2657 return "scifb";
2658 case PORT_HSCIF:
2659 return "hscif";
2660 }
2661
2662 return NULL;
2663 }
2664
2665 static int sci_remap_port(struct uart_port *port)
2666 {
2667 struct sci_port *sport = to_sci_port(port);
2668
2669 /*
2670 * Nothing to do if there's already an established membase.
2671 */
2672 if (port->membase)
2673 return 0;
2674
2675 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2676 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2677 if (unlikely(!port->membase)) {
2678 dev_err(port->dev, "can't remap port#%d\n", port->line);
2679 return -ENXIO;
2680 }
2681 } else {
2682 /*
2683 * For the simple (and majority of) cases where we don't
2684 * need to do any remapping, just cast the cookie
2685 * directly.
2686 */
2687 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2688 }
2689
2690 return 0;
2691 }
2692
2693 static void sci_release_port(struct uart_port *port)
2694 {
2695 struct sci_port *sport = to_sci_port(port);
2696
2697 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2698 iounmap(port->membase);
2699 port->membase = NULL;
2700 }
2701
2702 release_mem_region(port->mapbase, sport->reg_size);
2703 }
2704
2705 static int sci_request_port(struct uart_port *port)
2706 {
2707 struct resource *res;
2708 struct sci_port *sport = to_sci_port(port);
2709 int ret;
2710
2711 res = request_mem_region(port->mapbase, sport->reg_size,
2712 dev_name(port->dev));
2713 if (unlikely(res == NULL)) {
2714 dev_err(port->dev, "request_mem_region failed.");
2715 return -EBUSY;
2716 }
2717
2718 ret = sci_remap_port(port);
2719 if (unlikely(ret != 0)) {
2720 release_resource(res);
2721 return ret;
2722 }
2723
2724 return 0;
2725 }
2726
2727 static void sci_config_port(struct uart_port *port, int flags)
2728 {
2729 if (flags & UART_CONFIG_TYPE) {
2730 struct sci_port *sport = to_sci_port(port);
2731
2732 port->type = sport->cfg->type;
2733 sci_request_port(port);
2734 }
2735 }
2736
2737 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2738 {
2739 if (ser->baud_base < 2400)
2740 /* No paper tape reader for Mitch.. */
2741 return -EINVAL;
2742
2743 return 0;
2744 }
2745
2746 static const struct uart_ops sci_uart_ops = {
2747 .tx_empty = sci_tx_empty,
2748 .set_mctrl = sci_set_mctrl,
2749 .get_mctrl = sci_get_mctrl,
2750 .start_tx = sci_start_tx,
2751 .stop_tx = sci_stop_tx,
2752 .stop_rx = sci_stop_rx,
2753 .enable_ms = sci_enable_ms,
2754 .break_ctl = sci_break_ctl,
2755 .startup = sci_startup,
2756 .shutdown = sci_shutdown,
2757 .flush_buffer = sci_flush_buffer,
2758 .set_termios = sci_set_termios,
2759 .pm = sci_pm,
2760 .type = sci_type,
2761 .release_port = sci_release_port,
2762 .request_port = sci_request_port,
2763 .config_port = sci_config_port,
2764 .verify_port = sci_verify_port,
2765 #ifdef CONFIG_CONSOLE_POLL
2766 .poll_get_char = sci_poll_get_char,
2767 .poll_put_char = sci_poll_put_char,
2768 #endif
2769 };
2770
2771 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2772 {
2773 const char *clk_names[] = {
2774 [SCI_FCK] = "fck",
2775 [SCI_SCK] = "sck",
2776 [SCI_BRG_INT] = "brg_int",
2777 [SCI_SCIF_CLK] = "scif_clk",
2778 };
2779 struct clk *clk;
2780 unsigned int i;
2781
2782 if (sci_port->cfg->type == PORT_HSCIF)
2783 clk_names[SCI_SCK] = "hsck";
2784
2785 for (i = 0; i < SCI_NUM_CLKS; i++) {
2786 clk = devm_clk_get(dev, clk_names[i]);
2787 if (PTR_ERR(clk) == -EPROBE_DEFER)
2788 return -EPROBE_DEFER;
2789
2790 if (IS_ERR(clk) && i == SCI_FCK) {
2791 /*
2792 * "fck" used to be called "sci_ick", and we need to
2793 * maintain DT backward compatibility.
2794 */
2795 clk = devm_clk_get(dev, "sci_ick");
2796 if (PTR_ERR(clk) == -EPROBE_DEFER)
2797 return -EPROBE_DEFER;
2798
2799 if (!IS_ERR(clk))
2800 goto found;
2801
2802 /*
2803 * Not all SH platforms declare a clock lookup entry
2804 * for SCI devices, in which case we need to get the
2805 * global "peripheral_clk" clock.
2806 */
2807 clk = devm_clk_get(dev, "peripheral_clk");
2808 if (!IS_ERR(clk))
2809 goto found;
2810
2811 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2812 PTR_ERR(clk));
2813 return PTR_ERR(clk);
2814 }
2815
2816 found:
2817 if (IS_ERR(clk))
2818 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2819 PTR_ERR(clk));
2820 else
2821 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2822 clk, clk_get_rate(clk));
2823 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2824 }
2825 return 0;
2826 }
2827
2828 static const struct sci_port_params *
2829 sci_probe_regmap(const struct plat_sci_port *cfg)
2830 {
2831 unsigned int regtype;
2832
2833 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2834 return &sci_port_params[cfg->regtype];
2835
2836 switch (cfg->type) {
2837 case PORT_SCI:
2838 regtype = SCIx_SCI_REGTYPE;
2839 break;
2840 case PORT_IRDA:
2841 regtype = SCIx_IRDA_REGTYPE;
2842 break;
2843 case PORT_SCIFA:
2844 regtype = SCIx_SCIFA_REGTYPE;
2845 break;
2846 case PORT_SCIFB:
2847 regtype = SCIx_SCIFB_REGTYPE;
2848 break;
2849 case PORT_SCIF:
2850 /*
2851 * The SH-4 is a bit of a misnomer here, although that's
2852 * where this particular port layout originated. This
2853 * configuration (or some slight variation thereof)
2854 * remains the dominant model for all SCIFs.
2855 */
2856 regtype = SCIx_SH4_SCIF_REGTYPE;
2857 break;
2858 case PORT_HSCIF:
2859 regtype = SCIx_HSCIF_REGTYPE;
2860 break;
2861 default:
2862 pr_err("Can't probe register map for given port\n");
2863 return NULL;
2864 }
2865
2866 return &sci_port_params[regtype];
2867 }
2868
2869 static int sci_init_single(struct platform_device *dev,
2870 struct sci_port *sci_port, unsigned int index,
2871 const struct plat_sci_port *p, bool early)
2872 {
2873 struct uart_port *port = &sci_port->port;
2874 const struct resource *res;
2875 unsigned int i;
2876 int ret;
2877
2878 sci_port->cfg = p;
2879
2880 port->ops = &sci_uart_ops;
2881 port->iotype = UPIO_MEM;
2882 port->line = index;
2883
2884 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2885 if (res == NULL)
2886 return -ENOMEM;
2887
2888 port->mapbase = res->start;
2889 sci_port->reg_size = resource_size(res);
2890
2891 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2892 sci_port->irqs[i] = platform_get_irq(dev, i);
2893
2894 /* The SCI generates several interrupts. They can be muxed together or
2895 * connected to different interrupt lines. In the muxed case only one
2896 * interrupt resource is specified as there is only one interrupt ID.
2897 * In the non-muxed case, up to 6 interrupt signals might be generated
2898 * from the SCI, however those signals might have their own individual
2899 * interrupt ID numbers, or muxed together with another interrupt.
2900 */
2901 if (sci_port->irqs[0] < 0)
2902 return -ENXIO;
2903
2904 if (sci_port->irqs[1] < 0)
2905 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2906 sci_port->irqs[i] = sci_port->irqs[0];
2907
2908 sci_port->params = sci_probe_regmap(p);
2909 if (unlikely(sci_port->params == NULL))
2910 return -EINVAL;
2911
2912 switch (p->type) {
2913 case PORT_SCIFB:
2914 sci_port->rx_trigger = 48;
2915 break;
2916 case PORT_HSCIF:
2917 sci_port->rx_trigger = 64;
2918 break;
2919 case PORT_SCIFA:
2920 sci_port->rx_trigger = 32;
2921 break;
2922 case PORT_SCIF:
2923 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2924 /* RX triggering not implemented for this IP */
2925 sci_port->rx_trigger = 1;
2926 else
2927 sci_port->rx_trigger = 8;
2928 break;
2929 default:
2930 sci_port->rx_trigger = 1;
2931 break;
2932 }
2933
2934 sci_port->rx_fifo_timeout = 0;
2935 sci_port->hscif_tot = 0;
2936
2937 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2938 * match the SoC datasheet, this should be investigated. Let platform
2939 * data override the sampling rate for now.
2940 */
2941 sci_port->sampling_rate_mask = p->sampling_rate
2942 ? SCI_SR(p->sampling_rate)
2943 : sci_port->params->sampling_rate_mask;
2944
2945 if (!early) {
2946 ret = sci_init_clocks(sci_port, &dev->dev);
2947 if (ret < 0)
2948 return ret;
2949
2950 port->dev = &dev->dev;
2951
2952 pm_runtime_enable(&dev->dev);
2953 }
2954
2955 port->type = p->type;
2956 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2957 port->fifosize = sci_port->params->fifosize;
2958
2959 if (port->type == PORT_SCI) {
2960 if (sci_port->reg_size >= 0x20)
2961 port->regshift = 2;
2962 else
2963 port->regshift = 1;
2964 }
2965
2966 /*
2967 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2968 * for the multi-IRQ ports, which is where we are primarily
2969 * concerned with the shutdown path synchronization.
2970 *
2971 * For the muxed case there's nothing more to do.
2972 */
2973 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2974 port->irqflags = 0;
2975
2976 port->serial_in = sci_serial_in;
2977 port->serial_out = sci_serial_out;
2978
2979 return 0;
2980 }
2981
2982 static void sci_cleanup_single(struct sci_port *port)
2983 {
2984 pm_runtime_disable(port->port.dev);
2985 }
2986
2987 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2988 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2989 static void serial_console_putchar(struct uart_port *port, int ch)
2990 {
2991 sci_poll_put_char(port, ch);
2992 }
2993
2994 /*
2995 * Print a string to the serial port trying not to disturb
2996 * any possible real use of the port...
2997 */
2998 static void serial_console_write(struct console *co, const char *s,
2999 unsigned count)
3000 {
3001 struct sci_port *sci_port = &sci_ports[co->index];
3002 struct uart_port *port = &sci_port->port;
3003 unsigned short bits, ctrl, ctrl_temp;
3004 unsigned long flags;
3005 int locked = 1;
3006
3007 #if defined(SUPPORT_SYSRQ)
3008 if (port->sysrq)
3009 locked = 0;
3010 else
3011 #endif
3012 if (oops_in_progress)
3013 locked = spin_trylock_irqsave(&port->lock, flags);
3014 else
3015 spin_lock_irqsave(&port->lock, flags);
3016
3017 /* first save SCSCR then disable interrupts, keep clock source */
3018 ctrl = serial_port_in(port, SCSCR);
3019 ctrl_temp = SCSCR_RE | SCSCR_TE |
3020 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3021 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3022 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3023
3024 uart_console_write(port, s, count, serial_console_putchar);
3025
3026 /* wait until fifo is empty and last bit has been transmitted */
3027 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3028 while ((serial_port_in(port, SCxSR) & bits) != bits)
3029 cpu_relax();
3030
3031 /* restore the SCSCR */
3032 serial_port_out(port, SCSCR, ctrl);
3033
3034 if (locked)
3035 spin_unlock_irqrestore(&port->lock, flags);
3036 }
3037
3038 static int serial_console_setup(struct console *co, char *options)
3039 {
3040 struct sci_port *sci_port;
3041 struct uart_port *port;
3042 int baud = 115200;
3043 int bits = 8;
3044 int parity = 'n';
3045 int flow = 'n';
3046 int ret;
3047
3048 /*
3049 * Refuse to handle any bogus ports.
3050 */
3051 if (co->index < 0 || co->index >= SCI_NPORTS)
3052 return -ENODEV;
3053
3054 sci_port = &sci_ports[co->index];
3055 port = &sci_port->port;
3056
3057 /*
3058 * Refuse to handle uninitialized ports.
3059 */
3060 if (!port->ops)
3061 return -ENODEV;
3062
3063 ret = sci_remap_port(port);
3064 if (unlikely(ret != 0))
3065 return ret;
3066
3067 if (options)
3068 uart_parse_options(options, &baud, &parity, &bits, &flow);
3069
3070 return uart_set_options(port, co, baud, parity, bits, flow);
3071 }
3072
3073 static struct console serial_console = {
3074 .name = "ttySC",
3075 .device = uart_console_device,
3076 .write = serial_console_write,
3077 .setup = serial_console_setup,
3078 .flags = CON_PRINTBUFFER,
3079 .index = -1,
3080 .data = &sci_uart_driver,
3081 };
3082
3083 static struct console early_serial_console = {
3084 .name = "early_ttySC",
3085 .write = serial_console_write,
3086 .flags = CON_PRINTBUFFER,
3087 .index = -1,
3088 };
3089
3090 static char early_serial_buf[32];
3091
3092 static int sci_probe_earlyprintk(struct platform_device *pdev)
3093 {
3094 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3095
3096 if (early_serial_console.data)
3097 return -EEXIST;
3098
3099 early_serial_console.index = pdev->id;
3100
3101 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3102
3103 serial_console_setup(&early_serial_console, early_serial_buf);
3104
3105 if (!strstr(early_serial_buf, "keep"))
3106 early_serial_console.flags |= CON_BOOT;
3107
3108 register_console(&early_serial_console);
3109 return 0;
3110 }
3111
3112 #define SCI_CONSOLE (&serial_console)
3113
3114 #else
3115 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3116 {
3117 return -EINVAL;
3118 }
3119
3120 #define SCI_CONSOLE NULL
3121
3122 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3123
3124 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3125
3126 static DEFINE_MUTEX(sci_uart_registration_lock);
3127 static struct uart_driver sci_uart_driver = {
3128 .owner = THIS_MODULE,
3129 .driver_name = "sci",
3130 .dev_name = "ttySC",
3131 .major = SCI_MAJOR,
3132 .minor = SCI_MINOR_START,
3133 .nr = SCI_NPORTS,
3134 .cons = SCI_CONSOLE,
3135 };
3136
3137 static int sci_remove(struct platform_device *dev)
3138 {
3139 struct sci_port *port = platform_get_drvdata(dev);
3140 unsigned int type = port->port.type; /* uart_remove_... clears it */
3141
3142 sci_ports_in_use &= ~BIT(port->port.line);
3143 uart_remove_one_port(&sci_uart_driver, &port->port);
3144
3145 sci_cleanup_single(port);
3146
3147 if (port->port.fifosize > 1) {
3148 sysfs_remove_file(&dev->dev.kobj,
3149 &dev_attr_rx_fifo_trigger.attr);
3150 }
3151 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
3152 sysfs_remove_file(&dev->dev.kobj,
3153 &dev_attr_rx_fifo_timeout.attr);
3154 }
3155
3156 return 0;
3157 }
3158
3159
3160 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3161 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3162 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3163
3164 static const struct of_device_id of_sci_match[] = {
3165 /* SoC-specific types */
3166 {
3167 .compatible = "renesas,scif-r7s72100",
3168 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3169 },
3170 {
3171 .compatible = "renesas,scif-r7s9210",
3172 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3173 },
3174 /* Family-specific types */
3175 {
3176 .compatible = "renesas,rcar-gen1-scif",
3177 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3178 }, {
3179 .compatible = "renesas,rcar-gen2-scif",
3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3181 }, {
3182 .compatible = "renesas,rcar-gen3-scif",
3183 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3184 },
3185 /* Generic types */
3186 {
3187 .compatible = "renesas,scif",
3188 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3189 }, {
3190 .compatible = "renesas,scifa",
3191 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3192 }, {
3193 .compatible = "renesas,scifb",
3194 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3195 }, {
3196 .compatible = "renesas,hscif",
3197 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3198 }, {
3199 .compatible = "renesas,sci",
3200 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3201 }, {
3202 /* Terminator */
3203 },
3204 };
3205 MODULE_DEVICE_TABLE(of, of_sci_match);
3206
3207 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3208 unsigned int *dev_id)
3209 {
3210 struct device_node *np = pdev->dev.of_node;
3211 struct plat_sci_port *p;
3212 struct sci_port *sp;
3213 const void *data;
3214 int id;
3215
3216 if (!IS_ENABLED(CONFIG_OF) || !np)
3217 return NULL;
3218
3219 data = of_device_get_match_data(&pdev->dev);
3220
3221 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3222 if (!p)
3223 return NULL;
3224
3225 /* Get the line number from the aliases node. */
3226 id = of_alias_get_id(np, "serial");
3227 if (id < 0 && ~sci_ports_in_use)
3228 id = ffz(sci_ports_in_use);
3229 if (id < 0) {
3230 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3231 return NULL;
3232 }
3233 if (id >= ARRAY_SIZE(sci_ports)) {
3234 dev_err(&pdev->dev, "serial%d out of range\n", id);
3235 return NULL;
3236 }
3237
3238 sp = &sci_ports[id];
3239 *dev_id = id;
3240
3241 p->type = SCI_OF_TYPE(data);
3242 p->regtype = SCI_OF_REGTYPE(data);
3243
3244 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3245
3246 return p;
3247 }
3248
3249 static int sci_probe_single(struct platform_device *dev,
3250 unsigned int index,
3251 struct plat_sci_port *p,
3252 struct sci_port *sciport)
3253 {
3254 int ret;
3255
3256 /* Sanity check */
3257 if (unlikely(index >= SCI_NPORTS)) {
3258 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3259 index+1, SCI_NPORTS);
3260 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3261 return -EINVAL;
3262 }
3263 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3264 if (sci_ports_in_use & BIT(index))
3265 return -EBUSY;
3266
3267 mutex_lock(&sci_uart_registration_lock);
3268 if (!sci_uart_driver.state) {
3269 ret = uart_register_driver(&sci_uart_driver);
3270 if (ret) {
3271 mutex_unlock(&sci_uart_registration_lock);
3272 return ret;
3273 }
3274 }
3275 mutex_unlock(&sci_uart_registration_lock);
3276
3277 ret = sci_init_single(dev, sciport, index, p, false);
3278 if (ret)
3279 return ret;
3280
3281 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3282 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3283 return PTR_ERR(sciport->gpios);
3284
3285 if (sciport->has_rtscts) {
3286 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3287 UART_GPIO_CTS)) ||
3288 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3289 UART_GPIO_RTS))) {
3290 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3291 return -EINVAL;
3292 }
3293 sciport->port.flags |= UPF_HARD_FLOW;
3294 }
3295
3296 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3297 if (ret) {
3298 sci_cleanup_single(sciport);
3299 return ret;
3300 }
3301
3302 return 0;
3303 }
3304
3305 static int sci_probe(struct platform_device *dev)
3306 {
3307 struct plat_sci_port *p;
3308 struct sci_port *sp;
3309 unsigned int dev_id;
3310 int ret;
3311
3312 /*
3313 * If we've come here via earlyprintk initialization, head off to
3314 * the special early probe. We don't have sufficient device state
3315 * to make it beyond this yet.
3316 */
3317 if (is_early_platform_device(dev))
3318 return sci_probe_earlyprintk(dev);
3319
3320 if (dev->dev.of_node) {
3321 p = sci_parse_dt(dev, &dev_id);
3322 if (p == NULL)
3323 return -EINVAL;
3324 } else {
3325 p = dev->dev.platform_data;
3326 if (p == NULL) {
3327 dev_err(&dev->dev, "no platform data supplied\n");
3328 return -EINVAL;
3329 }
3330
3331 dev_id = dev->id;
3332 }
3333
3334 sp = &sci_ports[dev_id];
3335 platform_set_drvdata(dev, sp);
3336
3337 ret = sci_probe_single(dev, dev_id, p, sp);
3338 if (ret)
3339 return ret;
3340
3341 if (sp->port.fifosize > 1) {
3342 ret = sysfs_create_file(&dev->dev.kobj,
3343 &dev_attr_rx_fifo_trigger.attr);
3344 if (ret)
3345 return ret;
3346 }
3347 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3348 sp->port.type == PORT_HSCIF) {
3349 ret = sysfs_create_file(&dev->dev.kobj,
3350 &dev_attr_rx_fifo_timeout.attr);
3351 if (ret) {
3352 if (sp->port.fifosize > 1) {
3353 sysfs_remove_file(&dev->dev.kobj,
3354 &dev_attr_rx_fifo_trigger.attr);
3355 }
3356 return ret;
3357 }
3358 }
3359
3360 #ifdef CONFIG_SH_STANDARD_BIOS
3361 sh_bios_gdb_detach();
3362 #endif
3363
3364 sci_ports_in_use |= BIT(dev_id);
3365 return 0;
3366 }
3367
3368 static __maybe_unused int sci_suspend(struct device *dev)
3369 {
3370 struct sci_port *sport = dev_get_drvdata(dev);
3371
3372 if (sport)
3373 uart_suspend_port(&sci_uart_driver, &sport->port);
3374
3375 return 0;
3376 }
3377
3378 static __maybe_unused int sci_resume(struct device *dev)
3379 {
3380 struct sci_port *sport = dev_get_drvdata(dev);
3381
3382 if (sport)
3383 uart_resume_port(&sci_uart_driver, &sport->port);
3384
3385 return 0;
3386 }
3387
3388 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3389
3390 static struct platform_driver sci_driver = {
3391 .probe = sci_probe,
3392 .remove = sci_remove,
3393 .driver = {
3394 .name = "sh-sci",
3395 .pm = &sci_dev_pm_ops,
3396 .of_match_table = of_match_ptr(of_sci_match),
3397 },
3398 };
3399
3400 static int __init sci_init(void)
3401 {
3402 pr_info("%s\n", banner);
3403
3404 return platform_driver_register(&sci_driver);
3405 }
3406
3407 static void __exit sci_exit(void)
3408 {
3409 platform_driver_unregister(&sci_driver);
3410
3411 if (sci_uart_driver.state)
3412 uart_unregister_driver(&sci_uart_driver);
3413 }
3414
3415 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3416 early_platform_init_buffer("earlyprintk", &sci_driver,
3417 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3418 #endif
3419 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3420 static struct plat_sci_port port_cfg __initdata;
3421
3422 static int __init early_console_setup(struct earlycon_device *device,
3423 int type)
3424 {
3425 if (!device->port.membase)
3426 return -ENODEV;
3427
3428 device->port.serial_in = sci_serial_in;
3429 device->port.serial_out = sci_serial_out;
3430 device->port.type = type;
3431 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3432 port_cfg.type = type;
3433 sci_ports[0].cfg = &port_cfg;
3434 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3435 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3436 sci_serial_out(&sci_ports[0].port, SCSCR,
3437 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3438
3439 device->con->write = serial_console_write;
3440 return 0;
3441 }
3442 static int __init sci_early_console_setup(struct earlycon_device *device,
3443 const char *opt)
3444 {
3445 return early_console_setup(device, PORT_SCI);
3446 }
3447 static int __init scif_early_console_setup(struct earlycon_device *device,
3448 const char *opt)
3449 {
3450 return early_console_setup(device, PORT_SCIF);
3451 }
3452 static int __init scifa_early_console_setup(struct earlycon_device *device,
3453 const char *opt)
3454 {
3455 return early_console_setup(device, PORT_SCIFA);
3456 }
3457 static int __init scifb_early_console_setup(struct earlycon_device *device,
3458 const char *opt)
3459 {
3460 return early_console_setup(device, PORT_SCIFB);
3461 }
3462 static int __init hscif_early_console_setup(struct earlycon_device *device,
3463 const char *opt)
3464 {
3465 return early_console_setup(device, PORT_HSCIF);
3466 }
3467
3468 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3469 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3470 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3471 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3472 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3473 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3474
3475 module_init(sci_init);
3476 module_exit(sci_exit);
3477
3478 MODULE_LICENSE("GPL");
3479 MODULE_ALIAS("platform:sh-sci");
3480 MODULE_AUTHOR("Paul Mundt");
3481 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux with added FPC-III support