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Linux 4.19.133
[linux/fpc-iii.git] / drivers / tty / serial / stm32-usart.c
blobbce4ac1787add94c6e0ff7c1605f04c6f0ec9b8f
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/clk.h>
16 #include <linux/console.h>
17 #include <linux/delay.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pm_wakeirq.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/spinlock.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/tty.h>
36
37 #include "stm32-usart.h"
38
39 static void stm32_stop_tx(struct uart_port *port);
40 static void stm32_transmit_chars(struct uart_port *port);
41
42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
43 {
44 return container_of(port, struct stm32_port, port);
45 }
46
47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
48 {
49 u32 val;
50
51 val = readl_relaxed(port->membase + reg);
52 val |= bits;
53 writel_relaxed(val, port->membase + reg);
54 }
55
56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
57 {
58 u32 val;
59
60 val = readl_relaxed(port->membase + reg);
61 val &= ~bits;
62 writel_relaxed(val, port->membase + reg);
63 }
64
65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
66 u32 delay_DDE, u32 baud)
67 {
68 u32 rs485_deat_dedt;
69 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
70 bool over8;
71
72 *cr3 |= USART_CR3_DEM;
73 over8 = *cr1 & USART_CR1_OVER8;
74
75 if (over8)
76 rs485_deat_dedt = delay_ADE * baud * 8;
77 else
78 rs485_deat_dedt = delay_ADE * baud * 16;
79
80 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
81 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
82 rs485_deat_dedt_max : rs485_deat_dedt;
83 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
84 USART_CR1_DEAT_MASK;
85 *cr1 |= rs485_deat_dedt;
86
87 if (over8)
88 rs485_deat_dedt = delay_DDE * baud * 8;
89 else
90 rs485_deat_dedt = delay_DDE * baud * 16;
91
92 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
93 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
94 rs485_deat_dedt_max : rs485_deat_dedt;
95 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
96 USART_CR1_DEDT_MASK;
97 *cr1 |= rs485_deat_dedt;
98 }
99
100 static int stm32_config_rs485(struct uart_port *port,
101 struct serial_rs485 *rs485conf)
102 {
103 struct stm32_port *stm32_port = to_stm32_port(port);
104 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
105 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
106 u32 usartdiv, baud, cr1, cr3;
107 bool over8;
108
109 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
110
111 port->rs485 = *rs485conf;
112
113 rs485conf->flags |= SER_RS485_RX_DURING_TX;
114
115 if (rs485conf->flags & SER_RS485_ENABLED) {
116 cr1 = readl_relaxed(port->membase + ofs->cr1);
117 cr3 = readl_relaxed(port->membase + ofs->cr3);
118 usartdiv = readl_relaxed(port->membase + ofs->brr);
119 usartdiv = usartdiv & GENMASK(15, 0);
120 over8 = cr1 & USART_CR1_OVER8;
121
122 if (over8)
123 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
124 << USART_BRR_04_R_SHIFT;
125
126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
127 stm32_config_reg_rs485(&cr1, &cr3,
128 rs485conf->delay_rts_before_send,
129 rs485conf->delay_rts_after_send, baud);
130
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 cr3 &= ~USART_CR3_DEP;
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134 } else {
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 }
138
139 writel_relaxed(cr3, port->membase + ofs->cr3);
140 writel_relaxed(cr1, port->membase + ofs->cr1);
141 } else {
142 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
143 stm32_clr_bits(port, ofs->cr1,
144 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
145 }
146
147 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
148
149 return 0;
150 }
151
152 static int stm32_init_rs485(struct uart_port *port,
153 struct platform_device *pdev)
154 {
155 struct serial_rs485 *rs485conf = &port->rs485;
156
157 rs485conf->flags = 0;
158 rs485conf->delay_rts_before_send = 0;
159 rs485conf->delay_rts_after_send = 0;
160
161 if (!pdev->dev.of_node)
162 return -ENODEV;
163
164 uart_get_rs485_mode(&pdev->dev, rs485conf);
165
166 return 0;
167 }
168
169 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
170 bool threaded)
171 {
172 struct stm32_port *stm32_port = to_stm32_port(port);
173 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
174 enum dma_status status;
175 struct dma_tx_state state;
176
177 *sr = readl_relaxed(port->membase + ofs->isr);
178
179 if (threaded && stm32_port->rx_ch) {
180 status = dmaengine_tx_status(stm32_port->rx_ch,
181 stm32_port->rx_ch->cookie,
182 &state);
183 if ((status == DMA_IN_PROGRESS) &&
184 (*last_res != state.residue))
185 return 1;
186 else
187 return 0;
188 } else if (*sr & USART_SR_RXNE) {
189 return 1;
190 }
191 return 0;
192 }
193
194 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
195 int *last_res)
196 {
197 struct stm32_port *stm32_port = to_stm32_port(port);
198 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
199 unsigned long c;
200
201 if (stm32_port->rx_ch) {
202 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
203 if ((*last_res) == 0)
204 *last_res = RX_BUF_L;
205 } else {
206 c = readl_relaxed(port->membase + ofs->rdr);
207 /* apply RDR data mask */
208 c &= stm32_port->rdr_mask;
209 }
210
211 return c;
212 }
213
214 static void stm32_receive_chars(struct uart_port *port, bool threaded)
215 {
216 struct tty_port *tport = &port->state->port;
217 struct stm32_port *stm32_port = to_stm32_port(port);
218 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
219 unsigned long c;
220 u32 sr;
221 char flag;
222
223 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
224 pm_wakeup_event(tport->tty->dev, 0);
225
226 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
227 sr |= USART_SR_DUMMY_RX;
228 flag = TTY_NORMAL;
229
230 /*
231 * Status bits has to be cleared before reading the RDR:
232 * In FIFO mode, reading the RDR will pop the next data
233 * (if any) along with its status bits into the SR.
234 * Not doing so leads to misalignement between RDR and SR,
235 * and clear status bits of the next rx data.
236 *
237 * Clear errors flags for stm32f7 and stm32h7 compatible
238 * devices. On stm32f4 compatible devices, the error bit is
239 * cleared by the sequence [read SR - read DR].
240 */
241 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
242 writel_relaxed(sr & USART_SR_ERR_MASK,
243 port->membase + ofs->icr);
244
245 c = stm32_get_char(port, &sr, &stm32_port->last_res);
246 port->icount.rx++;
247 if (sr & USART_SR_ERR_MASK) {
248 if (sr & USART_SR_ORE) {
249 port->icount.overrun++;
250 } else if (sr & USART_SR_PE) {
251 port->icount.parity++;
252 } else if (sr & USART_SR_FE) {
253 /* Break detection if character is null */
254 if (!c) {
255 port->icount.brk++;
256 if (uart_handle_break(port))
257 continue;
258 } else {
259 port->icount.frame++;
260 }
261 }
262
263 sr &= port->read_status_mask;
264
265 if (sr & USART_SR_PE) {
266 flag = TTY_PARITY;
267 } else if (sr & USART_SR_FE) {
268 if (!c)
269 flag = TTY_BREAK;
270 else
271 flag = TTY_FRAME;
272 }
273 }
274
275 if (uart_handle_sysrq_char(port, c))
276 continue;
277 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
278 }
279
280 spin_unlock(&port->lock);
281 tty_flip_buffer_push(tport);
282 spin_lock(&port->lock);
283 }
284
285 static void stm32_tx_dma_complete(void *arg)
286 {
287 struct uart_port *port = arg;
288 struct stm32_port *stm32port = to_stm32_port(port);
289 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
290
291 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 stm32port->tx_dma_busy = false;
293
294 /* Let's see if we have pending data to send */
295 stm32_transmit_chars(port);
296 }
297
298 static void stm32_transmit_chars_pio(struct uart_port *port)
299 {
300 struct stm32_port *stm32_port = to_stm32_port(port);
301 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
302 struct circ_buf *xmit = &port->state->xmit;
303 unsigned int isr;
304 int ret;
305
306 if (stm32_port->tx_dma_busy) {
307 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
308 stm32_port->tx_dma_busy = false;
309 }
310
311 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
312 isr,
313 (isr & USART_SR_TXE),
314 10, 100000);
315
316 if (ret)
317 dev_err(port->dev, "tx empty not set\n");
318
319 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
320
321 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
322 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
323 port->icount.tx++;
324 }
325
326 static void stm32_transmit_chars_dma(struct uart_port *port)
327 {
328 struct stm32_port *stm32port = to_stm32_port(port);
329 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
330 struct circ_buf *xmit = &port->state->xmit;
331 struct dma_async_tx_descriptor *desc = NULL;
332 dma_cookie_t cookie;
333 unsigned int count, i;
334
335 if (stm32port->tx_dma_busy)
336 return;
337
338 stm32port->tx_dma_busy = true;
339
340 count = uart_circ_chars_pending(xmit);
341
342 if (count > TX_BUF_L)
343 count = TX_BUF_L;
344
345 if (xmit->tail < xmit->head) {
346 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
347 } else {
348 size_t one = UART_XMIT_SIZE - xmit->tail;
349 size_t two;
350
351 if (one > count)
352 one = count;
353 two = count - one;
354
355 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
356 if (two)
357 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
358 }
359
360 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
361 stm32port->tx_dma_buf,
362 count,
363 DMA_MEM_TO_DEV,
364 DMA_PREP_INTERRUPT);
365
366 if (!desc) {
367 for (i = count; i > 0; i--)
368 stm32_transmit_chars_pio(port);
369 return;
370 }
371
372 desc->callback = stm32_tx_dma_complete;
373 desc->callback_param = port;
374
375 /* Push current DMA TX transaction in the pending queue */
376 cookie = dmaengine_submit(desc);
377
378 /* Issue pending DMA TX requests */
379 dma_async_issue_pending(stm32port->tx_ch);
380
381 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
382
383 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
384 port->icount.tx += count;
385 }
386
387 static void stm32_transmit_chars(struct uart_port *port)
388 {
389 struct stm32_port *stm32_port = to_stm32_port(port);
390 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
391 struct circ_buf *xmit = &port->state->xmit;
392
393 if (port->x_char) {
394 if (stm32_port->tx_dma_busy)
395 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
396 writel_relaxed(port->x_char, port->membase + ofs->tdr);
397 port->x_char = 0;
398 port->icount.tx++;
399 if (stm32_port->tx_dma_busy)
400 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
401 return;
402 }
403
404 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
405 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
406 return;
407 }
408
409 if (ofs->icr == UNDEF_REG)
410 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
411 else
412 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
413
414 if (stm32_port->tx_ch)
415 stm32_transmit_chars_dma(port);
416 else
417 stm32_transmit_chars_pio(port);
418
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(port);
421
422 if (uart_circ_empty(xmit))
423 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
424 }
425
426 static irqreturn_t stm32_interrupt(int irq, void *ptr)
427 {
428 struct uart_port *port = ptr;
429 struct stm32_port *stm32_port = to_stm32_port(port);
430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
431 u32 sr;
432
433 spin_lock(&port->lock);
434
435 sr = readl_relaxed(port->membase + ofs->isr);
436
437 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
438 writel_relaxed(USART_ICR_WUCF,
439 port->membase + ofs->icr);
440
441 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
442 stm32_receive_chars(port, false);
443
444 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
445 stm32_transmit_chars(port);
446
447 spin_unlock(&port->lock);
448
449 if (stm32_port->rx_ch)
450 return IRQ_WAKE_THREAD;
451 else
452 return IRQ_HANDLED;
453 }
454
455 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
456 {
457 struct uart_port *port = ptr;
458 struct stm32_port *stm32_port = to_stm32_port(port);
459
460 spin_lock(&port->lock);
461
462 if (stm32_port->rx_ch)
463 stm32_receive_chars(port, true);
464
465 spin_unlock(&port->lock);
466
467 return IRQ_HANDLED;
468 }
469
470 static unsigned int stm32_tx_empty(struct uart_port *port)
471 {
472 struct stm32_port *stm32_port = to_stm32_port(port);
473 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
474
475 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
476 }
477
478 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
479 {
480 struct stm32_port *stm32_port = to_stm32_port(port);
481 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
482
483 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
484 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
485 else
486 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
487 }
488
489 static unsigned int stm32_get_mctrl(struct uart_port *port)
490 {
491 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
492 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
493 }
494
495 /* Transmit stop */
496 static void stm32_stop_tx(struct uart_port *port)
497 {
498 struct stm32_port *stm32_port = to_stm32_port(port);
499 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
500
501 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
502 }
503
504 /* There are probably characters waiting to be transmitted. */
505 static void stm32_start_tx(struct uart_port *port)
506 {
507 struct circ_buf *xmit = &port->state->xmit;
508
509 if (uart_circ_empty(xmit))
510 return;
511
512 stm32_transmit_chars(port);
513 }
514
515 /* Throttle the remote when input buffer is about to overflow. */
516 static void stm32_throttle(struct uart_port *port)
517 {
518 struct stm32_port *stm32_port = to_stm32_port(port);
519 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
520 unsigned long flags;
521
522 spin_lock_irqsave(&port->lock, flags);
523 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
524 spin_unlock_irqrestore(&port->lock, flags);
525 }
526
527 /* Unthrottle the remote, the input buffer can now accept data. */
528 static void stm32_unthrottle(struct uart_port *port)
529 {
530 struct stm32_port *stm32_port = to_stm32_port(port);
531 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
532 unsigned long flags;
533
534 spin_lock_irqsave(&port->lock, flags);
535 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
536 spin_unlock_irqrestore(&port->lock, flags);
537 }
538
539 /* Receive stop */
540 static void stm32_stop_rx(struct uart_port *port)
541 {
542 struct stm32_port *stm32_port = to_stm32_port(port);
543 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
544
545 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
546 }
547
548 /* Handle breaks - ignored by us */
549 static void stm32_break_ctl(struct uart_port *port, int break_state)
550 {
551 }
552
553 static int stm32_startup(struct uart_port *port)
554 {
555 struct stm32_port *stm32_port = to_stm32_port(port);
556 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
557 const char *name = to_platform_device(port->dev)->name;
558 u32 val;
559 int ret;
560
561 ret = request_threaded_irq(port->irq, stm32_interrupt,
562 stm32_threaded_interrupt,
563 IRQF_NO_SUSPEND, name, port);
564 if (ret)
565 return ret;
566
567 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
568 if (stm32_port->fifoen)
569 val |= USART_CR1_FIFOEN;
570 stm32_set_bits(port, ofs->cr1, val);
571
572 return 0;
573 }
574
575 static void stm32_shutdown(struct uart_port *port)
576 {
577 struct stm32_port *stm32_port = to_stm32_port(port);
578 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
579 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
580 u32 val, isr;
581 int ret;
582
583 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
584 val |= BIT(cfg->uart_enable_bit);
585 if (stm32_port->fifoen)
586 val |= USART_CR1_FIFOEN;
587
588 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
589 isr, (isr & USART_SR_TC),
590 10, 100000);
591
592 if (ret)
593 dev_err(port->dev, "transmission complete not set\n");
594
595 stm32_clr_bits(port, ofs->cr1, val);
596
597 free_irq(port->irq, port);
598 }
599
600 unsigned int stm32_get_databits(struct ktermios *termios)
601 {
602 unsigned int bits;
603
604 tcflag_t cflag = termios->c_cflag;
605
606 switch (cflag & CSIZE) {
607 /*
608 * CSIZE settings are not necessarily supported in hardware.
609 * CSIZE unsupported configurations are handled here to set word length
610 * to 8 bits word as default configuration and to print debug message.
611 */
612 case CS5:
613 bits = 5;
614 break;
615 case CS6:
616 bits = 6;
617 break;
618 case CS7:
619 bits = 7;
620 break;
621 /* default including CS8 */
622 default:
623 bits = 8;
624 break;
625 }
626
627 return bits;
628 }
629
630 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
631 struct ktermios *old)
632 {
633 struct stm32_port *stm32_port = to_stm32_port(port);
634 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
635 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
636 struct serial_rs485 *rs485conf = &port->rs485;
637 unsigned int baud, bits;
638 u32 usartdiv, mantissa, fraction, oversampling;
639 tcflag_t cflag = termios->c_cflag;
640 u32 cr1, cr2, cr3;
641 unsigned long flags;
642
643 if (!stm32_port->hw_flow_control)
644 cflag &= ~CRTSCTS;
645
646 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
647
648 spin_lock_irqsave(&port->lock, flags);
649
650 /* Stop serial port and reset value */
651 writel_relaxed(0, port->membase + ofs->cr1);
652
653 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
654
655 if (stm32_port->fifoen)
656 cr1 |= USART_CR1_FIFOEN;
657 cr2 = 0;
658 cr3 = 0;
659
660 if (cflag & CSTOPB)
661 cr2 |= USART_CR2_STOP_2B;
662
663 bits = stm32_get_databits(termios);
664 stm32_port->rdr_mask = (BIT(bits) - 1);
665
666 if (cflag & PARENB) {
667 bits++;
668 cr1 |= USART_CR1_PCE;
669 }
670
671 /*
672 * Word length configuration:
673 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
674 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
675 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
676 * M0 and M1 already cleared by cr1 initialization.
677 */
678 if (bits == 9)
679 cr1 |= USART_CR1_M0;
680 else if ((bits == 7) && cfg->has_7bits_data)
681 cr1 |= USART_CR1_M1;
682 else if (bits != 8)
683 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
684 , bits);
685
686 if (cflag & PARODD)
687 cr1 |= USART_CR1_PS;
688
689 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
690 if (cflag & CRTSCTS) {
691 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
692 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
693 }
694
695 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
696
697 /*
698 * The USART supports 16 or 8 times oversampling.
699 * By default we prefer 16 times oversampling, so that the receiver
700 * has a better tolerance to clock deviations.
701 * 8 times oversampling is only used to achieve higher speeds.
702 */
703 if (usartdiv < 16) {
704 oversampling = 8;
705 cr1 |= USART_CR1_OVER8;
706 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
707 } else {
708 oversampling = 16;
709 cr1 &= ~USART_CR1_OVER8;
710 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
711 }
712
713 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
714 fraction = usartdiv % oversampling;
715 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
716
717 uart_update_timeout(port, cflag, baud);
718
719 port->read_status_mask = USART_SR_ORE;
720 if (termios->c_iflag & INPCK)
721 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
722 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
723 port->read_status_mask |= USART_SR_FE;
724
725 /* Characters to ignore */
726 port->ignore_status_mask = 0;
727 if (termios->c_iflag & IGNPAR)
728 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
729 if (termios->c_iflag & IGNBRK) {
730 port->ignore_status_mask |= USART_SR_FE;
731 /*
732 * If we're ignoring parity and break indicators,
733 * ignore overruns too (for real raw support).
734 */
735 if (termios->c_iflag & IGNPAR)
736 port->ignore_status_mask |= USART_SR_ORE;
737 }
738
739 /* Ignore all characters if CREAD is not set */
740 if ((termios->c_cflag & CREAD) == 0)
741 port->ignore_status_mask |= USART_SR_DUMMY_RX;
742
743 if (stm32_port->rx_ch)
744 cr3 |= USART_CR3_DMAR;
745
746 if (rs485conf->flags & SER_RS485_ENABLED) {
747 stm32_config_reg_rs485(&cr1, &cr3,
748 rs485conf->delay_rts_before_send,
749 rs485conf->delay_rts_after_send, baud);
750 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
751 cr3 &= ~USART_CR3_DEP;
752 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
753 } else {
754 cr3 |= USART_CR3_DEP;
755 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
756 }
757
758 } else {
759 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
760 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
761 }
762
763 writel_relaxed(cr3, port->membase + ofs->cr3);
764 writel_relaxed(cr2, port->membase + ofs->cr2);
765 writel_relaxed(cr1, port->membase + ofs->cr1);
766
767 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
768 spin_unlock_irqrestore(&port->lock, flags);
769 }
770
771 static const char *stm32_type(struct uart_port *port)
772 {
773 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
774 }
775
776 static void stm32_release_port(struct uart_port *port)
777 {
778 }
779
780 static int stm32_request_port(struct uart_port *port)
781 {
782 return 0;
783 }
784
785 static void stm32_config_port(struct uart_port *port, int flags)
786 {
787 if (flags & UART_CONFIG_TYPE)
788 port->type = PORT_STM32;
789 }
790
791 static int
792 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
793 {
794 /* No user changeable parameters */
795 return -EINVAL;
796 }
797
798 static void stm32_pm(struct uart_port *port, unsigned int state,
799 unsigned int oldstate)
800 {
801 struct stm32_port *stm32port = container_of(port,
802 struct stm32_port, port);
803 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
804 struct stm32_usart_config *cfg = &stm32port->info->cfg;
805 unsigned long flags = 0;
806
807 switch (state) {
808 case UART_PM_STATE_ON:
809 clk_prepare_enable(stm32port->clk);
810 break;
811 case UART_PM_STATE_OFF:
812 spin_lock_irqsave(&port->lock, flags);
813 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
814 spin_unlock_irqrestore(&port->lock, flags);
815 clk_disable_unprepare(stm32port->clk);
816 break;
817 }
818 }
819
820 static const struct uart_ops stm32_uart_ops = {
821 .tx_empty = stm32_tx_empty,
822 .set_mctrl = stm32_set_mctrl,
823 .get_mctrl = stm32_get_mctrl,
824 .stop_tx = stm32_stop_tx,
825 .start_tx = stm32_start_tx,
826 .throttle = stm32_throttle,
827 .unthrottle = stm32_unthrottle,
828 .stop_rx = stm32_stop_rx,
829 .break_ctl = stm32_break_ctl,
830 .startup = stm32_startup,
831 .shutdown = stm32_shutdown,
832 .set_termios = stm32_set_termios,
833 .pm = stm32_pm,
834 .type = stm32_type,
835 .release_port = stm32_release_port,
836 .request_port = stm32_request_port,
837 .config_port = stm32_config_port,
838 .verify_port = stm32_verify_port,
839 };
840
841 static int stm32_init_port(struct stm32_port *stm32port,
842 struct platform_device *pdev)
843 {
844 struct uart_port *port = &stm32port->port;
845 struct resource *res;
846 int ret;
847
848 port->iotype = UPIO_MEM;
849 port->flags = UPF_BOOT_AUTOCONF;
850 port->ops = &stm32_uart_ops;
851 port->dev = &pdev->dev;
852 port->irq = platform_get_irq(pdev, 0);
853 port->rs485_config = stm32_config_rs485;
854
855 stm32_init_rs485(port, pdev);
856
857 stm32port->wakeirq = platform_get_irq(pdev, 1);
858 stm32port->fifoen = stm32port->info->cfg.has_fifo;
859
860 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
861 port->membase = devm_ioremap_resource(&pdev->dev, res);
862 if (IS_ERR(port->membase))
863 return PTR_ERR(port->membase);
864 port->mapbase = res->start;
865
866 spin_lock_init(&port->lock);
867
868 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
869 if (IS_ERR(stm32port->clk))
870 return PTR_ERR(stm32port->clk);
871
872 /* Ensure that clk rate is correct by enabling the clk */
873 ret = clk_prepare_enable(stm32port->clk);
874 if (ret)
875 return ret;
876
877 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
878 if (!stm32port->port.uartclk) {
879 clk_disable_unprepare(stm32port->clk);
880 ret = -EINVAL;
881 }
882
883 return ret;
884 }
885
886 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
887 {
888 struct device_node *np = pdev->dev.of_node;
889 int id;
890
891 if (!np)
892 return NULL;
893
894 id = of_alias_get_id(np, "serial");
895 if (id < 0) {
896 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
897 return NULL;
898 }
899
900 if (WARN_ON(id >= STM32_MAX_PORTS))
901 return NULL;
902
903 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
904 "st,hw-flow-ctrl");
905 stm32_ports[id].port.line = id;
906 stm32_ports[id].last_res = RX_BUF_L;
907 return &stm32_ports[id];
908 }
909
910 #ifdef CONFIG_OF
911 static const struct of_device_id stm32_match[] = {
912 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
913 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
914 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
915 {},
916 };
917
918 MODULE_DEVICE_TABLE(of, stm32_match);
919 #endif
920
921 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
922 struct platform_device *pdev)
923 {
924 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
925 struct uart_port *port = &stm32port->port;
926 struct device *dev = &pdev->dev;
927 struct dma_slave_config config;
928 struct dma_async_tx_descriptor *desc = NULL;
929 dma_cookie_t cookie;
930 int ret;
931
932 /* Request DMA RX channel */
933 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
934 if (!stm32port->rx_ch) {
935 dev_info(dev, "rx dma alloc failed\n");
936 return -ENODEV;
937 }
938 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
939 &stm32port->rx_dma_buf,
940 GFP_KERNEL);
941 if (!stm32port->rx_buf) {
942 ret = -ENOMEM;
943 goto alloc_err;
944 }
945
946 /* Configure DMA channel */
947 memset(&config, 0, sizeof(config));
948 config.src_addr = port->mapbase + ofs->rdr;
949 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
950
951 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
952 if (ret < 0) {
953 dev_err(dev, "rx dma channel config failed\n");
954 ret = -ENODEV;
955 goto config_err;
956 }
957
958 /* Prepare a DMA cyclic transaction */
959 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
960 stm32port->rx_dma_buf,
961 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
962 DMA_PREP_INTERRUPT);
963 if (!desc) {
964 dev_err(dev, "rx dma prep cyclic failed\n");
965 ret = -ENODEV;
966 goto config_err;
967 }
968
969 /* No callback as dma buffer is drained on usart interrupt */
970 desc->callback = NULL;
971 desc->callback_param = NULL;
972
973 /* Push current DMA transaction in the pending queue */
974 cookie = dmaengine_submit(desc);
975
976 /* Issue pending DMA requests */
977 dma_async_issue_pending(stm32port->rx_ch);
978
979 return 0;
980
981 config_err:
982 dma_free_coherent(&pdev->dev,
983 RX_BUF_L, stm32port->rx_buf,
984 stm32port->rx_dma_buf);
985
986 alloc_err:
987 dma_release_channel(stm32port->rx_ch);
988 stm32port->rx_ch = NULL;
989
990 return ret;
991 }
992
993 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
994 struct platform_device *pdev)
995 {
996 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
997 struct uart_port *port = &stm32port->port;
998 struct device *dev = &pdev->dev;
999 struct dma_slave_config config;
1000 int ret;
1001
1002 stm32port->tx_dma_busy = false;
1003
1004 /* Request DMA TX channel */
1005 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1006 if (!stm32port->tx_ch) {
1007 dev_info(dev, "tx dma alloc failed\n");
1008 return -ENODEV;
1009 }
1010 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1011 &stm32port->tx_dma_buf,
1012 GFP_KERNEL);
1013 if (!stm32port->tx_buf) {
1014 ret = -ENOMEM;
1015 goto alloc_err;
1016 }
1017
1018 /* Configure DMA channel */
1019 memset(&config, 0, sizeof(config));
1020 config.dst_addr = port->mapbase + ofs->tdr;
1021 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1022
1023 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1024 if (ret < 0) {
1025 dev_err(dev, "tx dma channel config failed\n");
1026 ret = -ENODEV;
1027 goto config_err;
1028 }
1029
1030 return 0;
1031
1032 config_err:
1033 dma_free_coherent(&pdev->dev,
1034 TX_BUF_L, stm32port->tx_buf,
1035 stm32port->tx_dma_buf);
1036
1037 alloc_err:
1038 dma_release_channel(stm32port->tx_ch);
1039 stm32port->tx_ch = NULL;
1040
1041 return ret;
1042 }
1043
1044 static int stm32_serial_probe(struct platform_device *pdev)
1045 {
1046 const struct of_device_id *match;
1047 struct stm32_port *stm32port;
1048 int ret;
1049
1050 stm32port = stm32_of_get_stm32_port(pdev);
1051 if (!stm32port)
1052 return -ENODEV;
1053
1054 match = of_match_device(stm32_match, &pdev->dev);
1055 if (match && match->data)
1056 stm32port->info = (struct stm32_usart_info *)match->data;
1057 else
1058 return -EINVAL;
1059
1060 ret = stm32_init_port(stm32port, pdev);
1061 if (ret)
1062 return ret;
1063
1064 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1065 ret = device_init_wakeup(&pdev->dev, true);
1066 if (ret)
1067 goto err_uninit;
1068
1069 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1070 stm32port->wakeirq);
1071 if (ret)
1072 goto err_nowup;
1073
1074 device_set_wakeup_enable(&pdev->dev, false);
1075 }
1076
1077 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1078 if (ret)
1079 goto err_wirq;
1080
1081 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1082 if (ret)
1083 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1084
1085 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1086 if (ret)
1087 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1088
1089 platform_set_drvdata(pdev, &stm32port->port);
1090
1091 return 0;
1092
1093 err_wirq:
1094 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1095 dev_pm_clear_wake_irq(&pdev->dev);
1096
1097 err_nowup:
1098 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1099 device_init_wakeup(&pdev->dev, false);
1100
1101 err_uninit:
1102 clk_disable_unprepare(stm32port->clk);
1103
1104 return ret;
1105 }
1106
1107 static int stm32_serial_remove(struct platform_device *pdev)
1108 {
1109 struct uart_port *port = platform_get_drvdata(pdev);
1110 struct stm32_port *stm32_port = to_stm32_port(port);
1111 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1112 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1113
1114 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1115
1116 if (stm32_port->rx_ch)
1117 dma_release_channel(stm32_port->rx_ch);
1118
1119 if (stm32_port->rx_dma_buf)
1120 dma_free_coherent(&pdev->dev,
1121 RX_BUF_L, stm32_port->rx_buf,
1122 stm32_port->rx_dma_buf);
1123
1124 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1125
1126 if (stm32_port->tx_ch)
1127 dma_release_channel(stm32_port->tx_ch);
1128
1129 if (stm32_port->tx_dma_buf)
1130 dma_free_coherent(&pdev->dev,
1131 TX_BUF_L, stm32_port->tx_buf,
1132 stm32_port->tx_dma_buf);
1133
1134 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
1135 dev_pm_clear_wake_irq(&pdev->dev);
1136 device_init_wakeup(&pdev->dev, false);
1137 }
1138
1139 clk_disable_unprepare(stm32_port->clk);
1140
1141 return uart_remove_one_port(&stm32_usart_driver, port);
1142 }
1143
1144
1145 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1146 static void stm32_console_putchar(struct uart_port *port, int ch)
1147 {
1148 struct stm32_port *stm32_port = to_stm32_port(port);
1149 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1150
1151 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1152 cpu_relax();
1153
1154 writel_relaxed(ch, port->membase + ofs->tdr);
1155 }
1156
1157 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1158 {
1159 struct uart_port *port = &stm32_ports[co->index].port;
1160 struct stm32_port *stm32_port = to_stm32_port(port);
1161 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1162 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1163 unsigned long flags;
1164 u32 old_cr1, new_cr1;
1165 int locked = 1;
1166
1167 local_irq_save(flags);
1168 if (port->sysrq)
1169 locked = 0;
1170 else if (oops_in_progress)
1171 locked = spin_trylock(&port->lock);
1172 else
1173 spin_lock(&port->lock);
1174
1175 /* Save and disable interrupts, enable the transmitter */
1176 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1177 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1178 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1179 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1180
1181 uart_console_write(port, s, cnt, stm32_console_putchar);
1182
1183 /* Restore interrupt state */
1184 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1185
1186 if (locked)
1187 spin_unlock(&port->lock);
1188 local_irq_restore(flags);
1189 }
1190
1191 static int stm32_console_setup(struct console *co, char *options)
1192 {
1193 struct stm32_port *stm32port;
1194 int baud = 9600;
1195 int bits = 8;
1196 int parity = 'n';
1197 int flow = 'n';
1198
1199 if (co->index >= STM32_MAX_PORTS)
1200 return -ENODEV;
1201
1202 stm32port = &stm32_ports[co->index];
1203
1204 /*
1205 * This driver does not support early console initialization
1206 * (use ARM early printk support instead), so we only expect
1207 * this to be called during the uart port registration when the
1208 * driver gets probed and the port should be mapped at that point.
1209 */
1210 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1211 return -ENXIO;
1212
1213 if (options)
1214 uart_parse_options(options, &baud, &parity, &bits, &flow);
1215
1216 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1217 }
1218
1219 static struct console stm32_console = {
1220 .name = STM32_SERIAL_NAME,
1221 .device = uart_console_device,
1222 .write = stm32_console_write,
1223 .setup = stm32_console_setup,
1224 .flags = CON_PRINTBUFFER,
1225 .index = -1,
1226 .data = &stm32_usart_driver,
1227 };
1228
1229 #define STM32_SERIAL_CONSOLE (&stm32_console)
1230
1231 #else
1232 #define STM32_SERIAL_CONSOLE NULL
1233 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1234
1235 static struct uart_driver stm32_usart_driver = {
1236 .driver_name = DRIVER_NAME,
1237 .dev_name = STM32_SERIAL_NAME,
1238 .major = 0,
1239 .minor = 0,
1240 .nr = STM32_MAX_PORTS,
1241 .cons = STM32_SERIAL_CONSOLE,
1242 };
1243
1244 #ifdef CONFIG_PM_SLEEP
1245 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1246 {
1247 struct stm32_port *stm32_port = to_stm32_port(port);
1248 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1249 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1250 u32 val;
1251
1252 if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1253 return;
1254
1255 if (enable) {
1256 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1257 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1258 val = readl_relaxed(port->membase + ofs->cr3);
1259 val &= ~USART_CR3_WUS_MASK;
1260 /* Enable Wake up interrupt from low power on start bit */
1261 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1262 writel_relaxed(val, port->membase + ofs->cr3);
1263 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1264 } else {
1265 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1266 }
1267 }
1268
1269 static int stm32_serial_suspend(struct device *dev)
1270 {
1271 struct uart_port *port = dev_get_drvdata(dev);
1272
1273 uart_suspend_port(&stm32_usart_driver, port);
1274
1275 if (device_may_wakeup(dev))
1276 stm32_serial_enable_wakeup(port, true);
1277 else
1278 stm32_serial_enable_wakeup(port, false);
1279
1280 return 0;
1281 }
1282
1283 static int stm32_serial_resume(struct device *dev)
1284 {
1285 struct uart_port *port = dev_get_drvdata(dev);
1286
1287 if (device_may_wakeup(dev))
1288 stm32_serial_enable_wakeup(port, false);
1289
1290 return uart_resume_port(&stm32_usart_driver, port);
1291 }
1292 #endif /* CONFIG_PM_SLEEP */
1293
1294 static const struct dev_pm_ops stm32_serial_pm_ops = {
1295 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1296 };
1297
1298 static struct platform_driver stm32_serial_driver = {
1299 .probe = stm32_serial_probe,
1300 .remove = stm32_serial_remove,
1301 .driver = {
1302 .name = DRIVER_NAME,
1303 .pm = &stm32_serial_pm_ops,
1304 .of_match_table = of_match_ptr(stm32_match),
1305 },
1306 };
1307
1308 static int __init usart_init(void)
1309 {
1310 static char banner[] __initdata = "STM32 USART driver initialized";
1311 int ret;
1312
1313 pr_info("%s\n", banner);
1314
1315 ret = uart_register_driver(&stm32_usart_driver);
1316 if (ret)
1317 return ret;
1318
1319 ret = platform_driver_register(&stm32_serial_driver);
1320 if (ret)
1321 uart_unregister_driver(&stm32_usart_driver);
1322
1323 return ret;
1324 }
1325
1326 static void __exit usart_exit(void)
1327 {
1328 platform_driver_unregister(&stm32_serial_driver);
1329 uart_unregister_driver(&stm32_usart_driver);
1330 }
1331
1332 module_init(usart_init);
1333 module_exit(usart_exit);
1334
1335 MODULE_ALIAS("platform:" DRIVER_NAME);
1336 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1337 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support