1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
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6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions, and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The names of the above-listed copyright holders may not be used
15 * to endorse or promote products derived from this software without
16 * specific prior written permission.
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation; either version 2 of the License, or (at your option) any
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/of_device.h>
42 static void dwc2_set_bcm_params(struct dwc2_hsotg
*hsotg
)
44 struct dwc2_core_params
*p
= &hsotg
->params
;
46 p
->host_rx_fifo_size
= 774;
47 p
->max_transfer_size
= 65535;
48 p
->max_packet_count
= 511;
52 static void dwc2_set_his_params(struct dwc2_hsotg
*hsotg
)
54 struct dwc2_core_params
*p
= &hsotg
->params
;
56 p
->otg_cap
= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
;
57 p
->speed
= DWC2_SPEED_PARAM_HIGH
;
58 p
->host_rx_fifo_size
= 512;
59 p
->host_nperio_tx_fifo_size
= 512;
60 p
->host_perio_tx_fifo_size
= 512;
61 p
->max_transfer_size
= 65535;
62 p
->max_packet_count
= 511;
63 p
->host_channels
= 16;
64 p
->phy_type
= DWC2_PHY_TYPE_PARAM_UTMI
;
65 p
->phy_utmi_width
= 8;
66 p
->i2c_enable
= false;
67 p
->reload_ctl
= false;
68 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR16
<<
69 GAHBCFG_HBSTLEN_SHIFT
;
70 p
->change_speed_quirk
= true;
71 p
->power_down
= false;
74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg
*hsotg
)
76 struct dwc2_core_params
*p
= &hsotg
->params
;
81 static void dwc2_set_rk_params(struct dwc2_hsotg
*hsotg
)
83 struct dwc2_core_params
*p
= &hsotg
->params
;
85 p
->otg_cap
= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
;
86 p
->host_rx_fifo_size
= 525;
87 p
->host_nperio_tx_fifo_size
= 128;
88 p
->host_perio_tx_fifo_size
= 256;
89 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR16
<<
90 GAHBCFG_HBSTLEN_SHIFT
;
94 static void dwc2_set_ltq_params(struct dwc2_hsotg
*hsotg
)
96 struct dwc2_core_params
*p
= &hsotg
->params
;
99 p
->host_rx_fifo_size
= 288;
100 p
->host_nperio_tx_fifo_size
= 128;
101 p
->host_perio_tx_fifo_size
= 96;
102 p
->max_transfer_size
= 65535;
103 p
->max_packet_count
= 511;
104 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR16
<<
105 GAHBCFG_HBSTLEN_SHIFT
;
108 static void dwc2_set_amlogic_params(struct dwc2_hsotg
*hsotg
)
110 struct dwc2_core_params
*p
= &hsotg
->params
;
112 p
->otg_cap
= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
;
113 p
->speed
= DWC2_SPEED_PARAM_HIGH
;
114 p
->host_rx_fifo_size
= 512;
115 p
->host_nperio_tx_fifo_size
= 500;
116 p
->host_perio_tx_fifo_size
= 500;
117 p
->host_channels
= 16;
118 p
->phy_type
= DWC2_PHY_TYPE_PARAM_UTMI
;
119 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR8
<<
120 GAHBCFG_HBSTLEN_SHIFT
;
121 p
->power_down
= DWC2_POWER_DOWN_PARAM_NONE
;
124 static void dwc2_set_amcc_params(struct dwc2_hsotg
*hsotg
)
126 struct dwc2_core_params
*p
= &hsotg
->params
;
128 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR16
<< GAHBCFG_HBSTLEN_SHIFT
;
131 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg
*hsotg
)
133 struct dwc2_core_params
*p
= &hsotg
->params
;
135 p
->otg_cap
= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
;
136 p
->speed
= DWC2_SPEED_PARAM_FULL
;
137 p
->host_rx_fifo_size
= 128;
138 p
->host_nperio_tx_fifo_size
= 96;
139 p
->host_perio_tx_fifo_size
= 96;
140 p
->max_packet_count
= 256;
141 p
->phy_type
= DWC2_PHY_TYPE_PARAM_FS
;
142 p
->i2c_enable
= false;
143 p
->activate_stm_fs_transceiver
= true;
146 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg
*hsotg
)
148 struct dwc2_core_params
*p
= &hsotg
->params
;
150 p
->host_rx_fifo_size
= 622;
151 p
->host_nperio_tx_fifo_size
= 128;
152 p
->host_perio_tx_fifo_size
= 256;
155 const struct of_device_id dwc2_of_match_table
[] = {
156 { .compatible
= "brcm,bcm2835-usb", .data
= dwc2_set_bcm_params
},
157 { .compatible
= "hisilicon,hi6220-usb", .data
= dwc2_set_his_params
},
158 { .compatible
= "rockchip,rk3066-usb", .data
= dwc2_set_rk_params
},
159 { .compatible
= "lantiq,arx100-usb", .data
= dwc2_set_ltq_params
},
160 { .compatible
= "lantiq,xrx200-usb", .data
= dwc2_set_ltq_params
},
161 { .compatible
= "snps,dwc2" },
162 { .compatible
= "samsung,s3c6400-hsotg",
163 .data
= dwc2_set_s3c6400_params
},
164 { .compatible
= "amlogic,meson8-usb",
165 .data
= dwc2_set_amlogic_params
},
166 { .compatible
= "amlogic,meson8b-usb",
167 .data
= dwc2_set_amlogic_params
},
168 { .compatible
= "amlogic,meson-gxbb-usb",
169 .data
= dwc2_set_amlogic_params
},
170 { .compatible
= "amcc,dwc-otg", .data
= dwc2_set_amcc_params
},
171 { .compatible
= "st,stm32f4x9-fsotg",
172 .data
= dwc2_set_stm32f4x9_fsotg_params
},
173 { .compatible
= "st,stm32f4x9-hsotg" },
174 { .compatible
= "st,stm32f7-hsotg",
175 .data
= dwc2_set_stm32f7_hsotg_params
},
178 MODULE_DEVICE_TABLE(of
, dwc2_of_match_table
);
180 static void dwc2_set_param_otg_cap(struct dwc2_hsotg
*hsotg
)
184 switch (hsotg
->hw_params
.op_mode
) {
185 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE
:
186 val
= DWC2_CAP_PARAM_HNP_SRP_CAPABLE
;
188 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE
:
189 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
:
190 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST
:
191 val
= DWC2_CAP_PARAM_SRP_ONLY_CAPABLE
;
194 val
= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
;
198 hsotg
->params
.otg_cap
= val
;
201 static void dwc2_set_param_phy_type(struct dwc2_hsotg
*hsotg
)
204 u32 hs_phy_type
= hsotg
->hw_params
.hs_phy_type
;
206 val
= DWC2_PHY_TYPE_PARAM_FS
;
207 if (hs_phy_type
!= GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED
) {
208 if (hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
||
209 hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI_ULPI
)
210 val
= DWC2_PHY_TYPE_PARAM_UTMI
;
212 val
= DWC2_PHY_TYPE_PARAM_ULPI
;
215 if (dwc2_is_fs_iot(hsotg
))
216 hsotg
->params
.phy_type
= DWC2_PHY_TYPE_PARAM_FS
;
218 hsotg
->params
.phy_type
= val
;
221 static void dwc2_set_param_speed(struct dwc2_hsotg
*hsotg
)
225 val
= hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
?
226 DWC2_SPEED_PARAM_FULL
: DWC2_SPEED_PARAM_HIGH
;
228 if (dwc2_is_fs_iot(hsotg
))
229 val
= DWC2_SPEED_PARAM_FULL
;
231 if (dwc2_is_hs_iot(hsotg
))
232 val
= DWC2_SPEED_PARAM_HIGH
;
234 hsotg
->params
.speed
= val
;
237 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg
*hsotg
)
241 val
= (hsotg
->hw_params
.utmi_phy_data_width
==
242 GHWCFG4_UTMI_PHY_DATA_WIDTH_8
) ? 8 : 16;
244 hsotg
->params
.phy_utmi_width
= val
;
247 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg
*hsotg
)
249 struct dwc2_core_params
*p
= &hsotg
->params
;
254 fifo_count
= dwc2_hsotg_tx_fifo_count(hsotg
);
256 memset(p
->g_tx_fifo_size
, 0, sizeof(p
->g_tx_fifo_size
));
257 depth_average
= dwc2_hsotg_tx_fifo_average_depth(hsotg
);
258 for (i
= 1; i
<= fifo_count
; i
++)
259 p
->g_tx_fifo_size
[i
] = depth_average
;
262 static void dwc2_set_param_power_down(struct dwc2_hsotg
*hsotg
)
266 if (hsotg
->hw_params
.hibernation
)
268 else if (hsotg
->hw_params
.power_optimized
)
273 hsotg
->params
.power_down
= val
;
277 * dwc2_set_default_params() - Set all core parameters to their
278 * auto-detected default values.
280 * @hsotg: Programming view of the DWC_otg controller
283 static void dwc2_set_default_params(struct dwc2_hsotg
*hsotg
)
285 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
286 struct dwc2_core_params
*p
= &hsotg
->params
;
287 bool dma_capable
= !(hw
->arch
== GHWCFG2_SLAVE_ONLY_ARCH
);
289 dwc2_set_param_otg_cap(hsotg
);
290 dwc2_set_param_phy_type(hsotg
);
291 dwc2_set_param_speed(hsotg
);
292 dwc2_set_param_phy_utmi_width(hsotg
);
293 dwc2_set_param_power_down(hsotg
);
294 p
->phy_ulpi_ddr
= false;
295 p
->phy_ulpi_ext_vbus
= false;
297 p
->enable_dynamic_fifo
= hw
->enable_dynamic_fifo
;
298 p
->en_multiple_tx_fifo
= hw
->en_multiple_tx_fifo
;
299 p
->i2c_enable
= hw
->i2c_enable
;
300 p
->acg_enable
= hw
->acg_enable
;
301 p
->ulpi_fs_ls
= false;
303 p
->reload_ctl
= (hw
->snpsid
>= DWC2_CORE_REV_2_92a
);
304 p
->uframe_sched
= true;
305 p
->external_id_pin_ctl
= false;
307 p
->lpm_clock_gating
= true;
309 p
->hird_threshold_en
= true;
310 p
->hird_threshold
= 4;
311 p
->ipg_isoc_en
= false;
312 p
->max_packet_count
= hw
->max_packet_count
;
313 p
->max_transfer_size
= hw
->max_transfer_size
;
314 p
->ahbcfg
= GAHBCFG_HBSTLEN_INCR
<< GAHBCFG_HBSTLEN_SHIFT
;
316 if ((hsotg
->dr_mode
== USB_DR_MODE_HOST
) ||
317 (hsotg
->dr_mode
== USB_DR_MODE_OTG
)) {
318 p
->host_dma
= dma_capable
;
319 p
->dma_desc_enable
= false;
320 p
->dma_desc_fs_enable
= false;
321 p
->host_support_fs_ls_low_power
= false;
322 p
->host_ls_low_power_phy_clk
= false;
323 p
->host_channels
= hw
->host_channels
;
324 p
->host_rx_fifo_size
= hw
->rx_fifo_size
;
325 p
->host_nperio_tx_fifo_size
= hw
->host_nperio_tx_fifo_size
;
326 p
->host_perio_tx_fifo_size
= hw
->host_perio_tx_fifo_size
;
329 if ((hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) ||
330 (hsotg
->dr_mode
== USB_DR_MODE_OTG
)) {
331 p
->g_dma
= dma_capable
;
332 p
->g_dma_desc
= hw
->dma_desc_enable
;
335 * The values for g_rx_fifo_size (2048) and
336 * g_np_tx_fifo_size (1024) come from the legacy s3c
337 * gadget driver. These defaults have been hard-coded
338 * for some time so many platforms depend on these
339 * values. Leave them as defaults for now and only
340 * auto-detect if the hardware does not support the
343 p
->g_rx_fifo_size
= 2048;
344 p
->g_np_tx_fifo_size
= 1024;
345 dwc2_set_param_tx_fifo_sizes(hsotg
);
350 * dwc2_get_device_properties() - Read in device properties.
352 * @hsotg: Programming view of the DWC_otg controller
354 * Read in the device properties and adjust core parameters if needed.
356 static void dwc2_get_device_properties(struct dwc2_hsotg
*hsotg
)
358 struct dwc2_core_params
*p
= &hsotg
->params
;
361 if ((hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) ||
362 (hsotg
->dr_mode
== USB_DR_MODE_OTG
)) {
363 device_property_read_u32(hsotg
->dev
, "g-rx-fifo-size",
366 device_property_read_u32(hsotg
->dev
, "g-np-tx-fifo-size",
367 &p
->g_np_tx_fifo_size
);
369 num
= device_property_read_u32_array(hsotg
->dev
,
375 memset(p
->g_tx_fifo_size
, 0,
376 sizeof(p
->g_tx_fifo_size
));
377 device_property_read_u32_array(hsotg
->dev
,
379 &p
->g_tx_fifo_size
[1],
384 if (of_find_property(hsotg
->dev
->of_node
, "disable-over-current", NULL
))
385 p
->oc_disable
= true;
388 static void dwc2_check_param_otg_cap(struct dwc2_hsotg
*hsotg
)
392 switch (hsotg
->params
.otg_cap
) {
393 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE
:
394 if (hsotg
->hw_params
.op_mode
!= GHWCFG2_OP_MODE_HNP_SRP_CAPABLE
)
397 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE
:
398 switch (hsotg
->hw_params
.op_mode
) {
399 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE
:
400 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE
:
401 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
:
402 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST
:
409 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
:
418 dwc2_set_param_otg_cap(hsotg
);
421 static void dwc2_check_param_phy_type(struct dwc2_hsotg
*hsotg
)
427 hs_phy_type
= hsotg
->hw_params
.hs_phy_type
;
428 fs_phy_type
= hsotg
->hw_params
.fs_phy_type
;
430 switch (hsotg
->params
.phy_type
) {
431 case DWC2_PHY_TYPE_PARAM_FS
:
432 if (fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
)
435 case DWC2_PHY_TYPE_PARAM_UTMI
:
436 if ((hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
) ||
437 (hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI_ULPI
))
440 case DWC2_PHY_TYPE_PARAM_ULPI
:
441 if ((hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
) ||
442 (hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI_ULPI
))
450 dwc2_set_param_phy_type(hsotg
);
453 static void dwc2_check_param_speed(struct dwc2_hsotg
*hsotg
)
456 int phy_type
= hsotg
->params
.phy_type
;
457 int speed
= hsotg
->params
.speed
;
460 case DWC2_SPEED_PARAM_HIGH
:
461 if ((hsotg
->params
.speed
== DWC2_SPEED_PARAM_HIGH
) &&
462 (phy_type
== DWC2_PHY_TYPE_PARAM_FS
))
465 case DWC2_SPEED_PARAM_FULL
:
466 case DWC2_SPEED_PARAM_LOW
:
474 dwc2_set_param_speed(hsotg
);
477 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg
*hsotg
)
480 int param
= hsotg
->params
.phy_utmi_width
;
481 int width
= hsotg
->hw_params
.utmi_phy_data_width
;
484 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8
:
485 valid
= (param
== 8);
487 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16
:
488 valid
= (param
== 16);
490 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16
:
491 valid
= (param
== 8 || param
== 16);
496 dwc2_set_param_phy_utmi_width(hsotg
);
499 static void dwc2_check_param_power_down(struct dwc2_hsotg
*hsotg
)
501 int param
= hsotg
->params
.power_down
;
504 case DWC2_POWER_DOWN_PARAM_NONE
:
506 case DWC2_POWER_DOWN_PARAM_PARTIAL
:
507 if (hsotg
->hw_params
.power_optimized
)
510 "Partial power down isn't supported by HW\n");
511 param
= DWC2_POWER_DOWN_PARAM_NONE
;
513 case DWC2_POWER_DOWN_PARAM_HIBERNATION
:
514 if (hsotg
->hw_params
.hibernation
)
517 "Hibernation isn't supported by HW\n");
518 param
= DWC2_POWER_DOWN_PARAM_NONE
;
522 "%s: Invalid parameter power_down=%d\n",
524 param
= DWC2_POWER_DOWN_PARAM_NONE
;
528 hsotg
->params
.power_down
= param
;
531 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg
*hsotg
)
539 fifo_count
= dwc2_hsotg_tx_fifo_count(hsotg
);
540 min
= hsotg
->hw_params
.en_multiple_tx_fifo
? 16 : 4;
542 for (fifo
= 1; fifo
<= fifo_count
; fifo
++)
543 total
+= hsotg
->params
.g_tx_fifo_size
[fifo
];
545 if (total
> dwc2_hsotg_tx_fifo_total_depth(hsotg
) || !total
) {
546 dev_warn(hsotg
->dev
, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
548 dwc2_set_param_tx_fifo_sizes(hsotg
);
551 for (fifo
= 1; fifo
<= fifo_count
; fifo
++) {
552 dptxfszn
= hsotg
->hw_params
.g_tx_fifo_size
[fifo
];
554 if (hsotg
->params
.g_tx_fifo_size
[fifo
] < min
||
555 hsotg
->params
.g_tx_fifo_size
[fifo
] > dptxfszn
) {
556 dev_warn(hsotg
->dev
, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
558 hsotg
->params
.g_tx_fifo_size
[fifo
]);
559 hsotg
->params
.g_tx_fifo_size
[fifo
] = dptxfszn
;
564 #define CHECK_RANGE(_param, _min, _max, _def) do { \
565 if ((int)(hsotg->params._param) < (_min) || \
566 (hsotg->params._param) > (_max)) { \
567 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
568 __func__, #_param, hsotg->params._param); \
569 hsotg->params._param = (_def); \
573 #define CHECK_BOOL(_param, _check) do { \
574 if (hsotg->params._param && !(_check)) { \
575 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
576 __func__, #_param, hsotg->params._param); \
577 hsotg->params._param = false; \
581 static void dwc2_check_params(struct dwc2_hsotg
*hsotg
)
583 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
584 struct dwc2_core_params
*p
= &hsotg
->params
;
585 bool dma_capable
= !(hw
->arch
== GHWCFG2_SLAVE_ONLY_ARCH
);
587 dwc2_check_param_otg_cap(hsotg
);
588 dwc2_check_param_phy_type(hsotg
);
589 dwc2_check_param_speed(hsotg
);
590 dwc2_check_param_phy_utmi_width(hsotg
);
591 dwc2_check_param_power_down(hsotg
);
592 CHECK_BOOL(enable_dynamic_fifo
, hw
->enable_dynamic_fifo
);
593 CHECK_BOOL(en_multiple_tx_fifo
, hw
->en_multiple_tx_fifo
);
594 CHECK_BOOL(i2c_enable
, hw
->i2c_enable
);
595 CHECK_BOOL(ipg_isoc_en
, hw
->ipg_isoc_en
);
596 CHECK_BOOL(acg_enable
, hw
->acg_enable
);
597 CHECK_BOOL(reload_ctl
, (hsotg
->hw_params
.snpsid
> DWC2_CORE_REV_2_92a
));
598 CHECK_BOOL(lpm
, (hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_2_80a
));
599 CHECK_BOOL(lpm
, hw
->lpm_mode
);
600 CHECK_BOOL(lpm_clock_gating
, hsotg
->params
.lpm
);
601 CHECK_BOOL(besl
, hsotg
->params
.lpm
);
602 CHECK_BOOL(besl
, (hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_3_00a
));
603 CHECK_BOOL(hird_threshold_en
, hsotg
->params
.lpm
);
604 CHECK_RANGE(hird_threshold
, 0, hsotg
->params
.besl
? 12 : 7, 0);
605 CHECK_RANGE(max_packet_count
,
606 15, hw
->max_packet_count
,
607 hw
->max_packet_count
);
608 CHECK_RANGE(max_transfer_size
,
609 2047, hw
->max_transfer_size
,
610 hw
->max_transfer_size
);
612 if ((hsotg
->dr_mode
== USB_DR_MODE_HOST
) ||
613 (hsotg
->dr_mode
== USB_DR_MODE_OTG
)) {
614 CHECK_BOOL(host_dma
, dma_capable
);
615 CHECK_BOOL(dma_desc_enable
, p
->host_dma
);
616 CHECK_BOOL(dma_desc_fs_enable
, p
->dma_desc_enable
);
617 CHECK_BOOL(host_ls_low_power_phy_clk
,
618 p
->phy_type
== DWC2_PHY_TYPE_PARAM_FS
);
619 CHECK_RANGE(host_channels
,
620 1, hw
->host_channels
,
622 CHECK_RANGE(host_rx_fifo_size
,
623 16, hw
->rx_fifo_size
,
625 CHECK_RANGE(host_nperio_tx_fifo_size
,
626 16, hw
->host_nperio_tx_fifo_size
,
627 hw
->host_nperio_tx_fifo_size
);
628 CHECK_RANGE(host_perio_tx_fifo_size
,
629 16, hw
->host_perio_tx_fifo_size
,
630 hw
->host_perio_tx_fifo_size
);
633 if ((hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) ||
634 (hsotg
->dr_mode
== USB_DR_MODE_OTG
)) {
635 CHECK_BOOL(g_dma
, dma_capable
);
636 CHECK_BOOL(g_dma_desc
, (p
->g_dma
&& hw
->dma_desc_enable
));
637 CHECK_RANGE(g_rx_fifo_size
,
638 16, hw
->rx_fifo_size
,
640 CHECK_RANGE(g_np_tx_fifo_size
,
641 16, hw
->dev_nperio_tx_fifo_size
,
642 hw
->dev_nperio_tx_fifo_size
);
643 dwc2_check_param_tx_fifo_sizes(hsotg
);
648 * Gets host hardware parameters. Forces host mode if not currently in
649 * host mode. Should be called immediately after a core soft reset in
650 * order to get the reset values.
652 static void dwc2_get_host_hwparams(struct dwc2_hsotg
*hsotg
)
654 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
658 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
661 dwc2_force_mode(hsotg
, true);
663 gnptxfsiz
= dwc2_readl(hsotg
, GNPTXFSIZ
);
664 hptxfsiz
= dwc2_readl(hsotg
, HPTXFSIZ
);
666 hw
->host_nperio_tx_fifo_size
= (gnptxfsiz
& FIFOSIZE_DEPTH_MASK
) >>
667 FIFOSIZE_DEPTH_SHIFT
;
668 hw
->host_perio_tx_fifo_size
= (hptxfsiz
& FIFOSIZE_DEPTH_MASK
) >>
669 FIFOSIZE_DEPTH_SHIFT
;
673 * Gets device hardware parameters. Forces device mode if not
674 * currently in device mode. Should be called immediately after a core
675 * soft reset in order to get the reset values.
677 static void dwc2_get_dev_hwparams(struct dwc2_hsotg
*hsotg
)
679 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
681 int fifo
, fifo_count
;
683 if (hsotg
->dr_mode
== USB_DR_MODE_HOST
)
686 dwc2_force_mode(hsotg
, false);
688 gnptxfsiz
= dwc2_readl(hsotg
, GNPTXFSIZ
);
690 fifo_count
= dwc2_hsotg_tx_fifo_count(hsotg
);
692 for (fifo
= 1; fifo
<= fifo_count
; fifo
++) {
693 hw
->g_tx_fifo_size
[fifo
] =
694 (dwc2_readl(hsotg
, DPTXFSIZN(fifo
)) &
695 FIFOSIZE_DEPTH_MASK
) >> FIFOSIZE_DEPTH_SHIFT
;
698 hw
->dev_nperio_tx_fifo_size
= (gnptxfsiz
& FIFOSIZE_DEPTH_MASK
) >>
699 FIFOSIZE_DEPTH_SHIFT
;
703 * During device initialization, read various hardware configuration
704 * registers and interpret the contents.
706 * @hsotg: Programming view of the DWC_otg controller
709 int dwc2_get_hwparams(struct dwc2_hsotg
*hsotg
)
711 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
713 u32 hwcfg1
, hwcfg2
, hwcfg3
, hwcfg4
;
717 * Attempt to ensure this device is really a DWC_otg Controller.
718 * Read and verify the GSNPSID register contents. The value should be
719 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
722 hw
->snpsid
= dwc2_readl(hsotg
, GSNPSID
);
723 if ((hw
->snpsid
& GSNPSID_ID_MASK
) != DWC2_OTG_ID
&&
724 (hw
->snpsid
& GSNPSID_ID_MASK
) != DWC2_FS_IOT_ID
&&
725 (hw
->snpsid
& GSNPSID_ID_MASK
) != DWC2_HS_IOT_ID
) {
726 dev_err(hsotg
->dev
, "Bad value for GSNPSID: 0x%08x\n",
731 dev_dbg(hsotg
->dev
, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
732 hw
->snpsid
>> 12 & 0xf, hw
->snpsid
>> 8 & 0xf,
733 hw
->snpsid
>> 4 & 0xf, hw
->snpsid
& 0xf, hw
->snpsid
);
735 hwcfg1
= dwc2_readl(hsotg
, GHWCFG1
);
736 hwcfg2
= dwc2_readl(hsotg
, GHWCFG2
);
737 hwcfg3
= dwc2_readl(hsotg
, GHWCFG3
);
738 hwcfg4
= dwc2_readl(hsotg
, GHWCFG4
);
739 grxfsiz
= dwc2_readl(hsotg
, GRXFSIZ
);
742 hw
->dev_ep_dirs
= hwcfg1
;
745 hw
->op_mode
= (hwcfg2
& GHWCFG2_OP_MODE_MASK
) >>
746 GHWCFG2_OP_MODE_SHIFT
;
747 hw
->arch
= (hwcfg2
& GHWCFG2_ARCHITECTURE_MASK
) >>
748 GHWCFG2_ARCHITECTURE_SHIFT
;
749 hw
->enable_dynamic_fifo
= !!(hwcfg2
& GHWCFG2_DYNAMIC_FIFO
);
750 hw
->host_channels
= 1 + ((hwcfg2
& GHWCFG2_NUM_HOST_CHAN_MASK
) >>
751 GHWCFG2_NUM_HOST_CHAN_SHIFT
);
752 hw
->hs_phy_type
= (hwcfg2
& GHWCFG2_HS_PHY_TYPE_MASK
) >>
753 GHWCFG2_HS_PHY_TYPE_SHIFT
;
754 hw
->fs_phy_type
= (hwcfg2
& GHWCFG2_FS_PHY_TYPE_MASK
) >>
755 GHWCFG2_FS_PHY_TYPE_SHIFT
;
756 hw
->num_dev_ep
= (hwcfg2
& GHWCFG2_NUM_DEV_EP_MASK
) >>
757 GHWCFG2_NUM_DEV_EP_SHIFT
;
758 hw
->nperio_tx_q_depth
=
759 (hwcfg2
& GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK
) >>
760 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT
<< 1;
761 hw
->host_perio_tx_q_depth
=
762 (hwcfg2
& GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK
) >>
763 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT
<< 1;
764 hw
->dev_token_q_depth
=
765 (hwcfg2
& GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK
) >>
766 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT
;
769 width
= (hwcfg3
& GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK
) >>
770 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT
;
771 hw
->max_transfer_size
= (1 << (width
+ 11)) - 1;
772 width
= (hwcfg3
& GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK
) >>
773 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT
;
774 hw
->max_packet_count
= (1 << (width
+ 4)) - 1;
775 hw
->i2c_enable
= !!(hwcfg3
& GHWCFG3_I2C
);
776 hw
->total_fifo_size
= (hwcfg3
& GHWCFG3_DFIFO_DEPTH_MASK
) >>
777 GHWCFG3_DFIFO_DEPTH_SHIFT
;
778 hw
->lpm_mode
= !!(hwcfg3
& GHWCFG3_OTG_LPM_EN
);
781 hw
->en_multiple_tx_fifo
= !!(hwcfg4
& GHWCFG4_DED_FIFO_EN
);
782 hw
->num_dev_perio_in_ep
= (hwcfg4
& GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK
) >>
783 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT
;
784 hw
->num_dev_in_eps
= (hwcfg4
& GHWCFG4_NUM_IN_EPS_MASK
) >>
785 GHWCFG4_NUM_IN_EPS_SHIFT
;
786 hw
->dma_desc_enable
= !!(hwcfg4
& GHWCFG4_DESC_DMA
);
787 hw
->power_optimized
= !!(hwcfg4
& GHWCFG4_POWER_OPTIMIZ
);
788 hw
->hibernation
= !!(hwcfg4
& GHWCFG4_HIBER
);
789 hw
->utmi_phy_data_width
= (hwcfg4
& GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK
) >>
790 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT
;
791 hw
->acg_enable
= !!(hwcfg4
& GHWCFG4_ACG_SUPPORTED
);
792 hw
->ipg_isoc_en
= !!(hwcfg4
& GHWCFG4_IPG_ISOC_SUPPORTED
);
795 hw
->rx_fifo_size
= (grxfsiz
& GRXFSIZ_DEPTH_MASK
) >>
798 * Host specific hardware parameters. Reading these parameters
799 * requires the controller to be in host mode. The mode will
800 * be forced, if necessary, to read these values.
802 dwc2_get_host_hwparams(hsotg
);
803 dwc2_get_dev_hwparams(hsotg
);
808 int dwc2_init_params(struct dwc2_hsotg
*hsotg
)
810 const struct of_device_id
*match
;
811 void (*set_params
)(void *data
);
813 dwc2_set_default_params(hsotg
);
814 dwc2_get_device_properties(hsotg
);
816 match
= of_match_device(dwc2_of_match_table
, hsotg
->dev
);
817 if (match
&& match
->data
) {
818 set_params
= match
->data
;
822 dwc2_check_params(hsotg
);