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mmc: rtsx: Configure SD_CFG2 register in sd_rw_multi
[linux/fpc-iii.git] / drivers / pcmcia / m8xx_pcmcia.c
bloba3a851e49321542ac84659f4f3315219163430ae
1 /*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@opensource.se>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
42
43 #include <linux/kernel.h>
44 #include <linux/errno.h>
45 #include <linux/timer.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <linux/fsl_devices.h>
50 #include <linux/bitops.h>
51 #include <linux/of_device.h>
52 #include <linux/of_platform.h>
53
54 #include <asm/io.h>
55 #include <asm/time.h>
56 #include <asm/mpc8xx.h>
57 #include <asm/8xx_immap.h>
58 #include <asm/irq.h>
59 #include <asm/fs_pd.h>
60
61 #include <pcmcia/ss.h>
62
63 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
64 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
65
66 static const char *version = "Version 0.06, Aug 2005";
67 MODULE_LICENSE("Dual MPL/GPL");
68
69 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
70
71 /* The RPX series use SLOT_B */
72 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
73 #define CONFIG_PCMCIA_SLOT_B
74 #define CONFIG_BD_IS_MHZ
75 #endif
76
77 /* The ADS board use SLOT_A */
78 #ifdef CONFIG_ADS
79 #define CONFIG_PCMCIA_SLOT_A
80 #define CONFIG_BD_IS_MHZ
81 #endif
82
83 /* The FADS series are a mess */
84 #ifdef CONFIG_FADS
85 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
86 #define CONFIG_PCMCIA_SLOT_A
87 #else
88 #define CONFIG_PCMCIA_SLOT_B
89 #endif
90 #endif
91
92 #if defined(CONFIG_MPC885ADS)
93 #define CONFIG_PCMCIA_SLOT_A
94 #define PCMCIA_GLITCHY_CD
95 #endif
96
97 /* Cyclades ACS uses both slots */
98 #ifdef CONFIG_PRxK
99 #define CONFIG_PCMCIA_SLOT_A
100 #define CONFIG_PCMCIA_SLOT_B
101 #endif
102
103 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
104
105 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
106
107 #define PCMCIA_SOCKETS_NO 2
108 /* We have only 8 windows, dualsocket support will be limited. */
109 #define PCMCIA_MEM_WIN_NO 2
110 #define PCMCIA_IO_WIN_NO 2
111 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
112
113 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
114
115 #define PCMCIA_SOCKETS_NO 1
116 /* full support for one slot */
117 #define PCMCIA_MEM_WIN_NO 5
118 #define PCMCIA_IO_WIN_NO 2
119
120 /* define _slot_ to be able to optimize macros */
121
122 #ifdef CONFIG_PCMCIA_SLOT_A
123 #define _slot_ 0
124 #define PCMCIA_SLOT_MSG "SLOT_A"
125 #else
126 #define _slot_ 1
127 #define PCMCIA_SLOT_MSG "SLOT_B"
128 #endif
129
130 #else
131 #error m8xx_pcmcia: Bad configuration!
132 #endif
133
134 /* ------------------------------------------------------------------------- */
135
136 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
137 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
138 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
139 /* ------------------------------------------------------------------------- */
140
141 static int pcmcia_schlvl;
142
143 static DEFINE_SPINLOCK(events_lock);
144
145 #define PCMCIA_SOCKET_KEY_5V 1
146 #define PCMCIA_SOCKET_KEY_LV 2
147
148 /* look up table for pgcrx registers */
149 static u32 *m8xx_pgcrx[2];
150
151 /*
152 * This structure is used to address each window in the PCMCIA controller.
153 *
154 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
155 * after pcmcia_win[n]...
156 */
157
158 struct pcmcia_win {
159 u32 br;
160 u32 or;
161 };
162
163 /*
164 * For some reason the hardware guys decided to make both slots share
165 * some registers.
166 *
167 * Could someone invent object oriented hardware ?
168 *
169 * The macros are used to get the right bit from the registers.
170 * SLOT_A : slot = 0
171 * SLOT_B : slot = 1
172 */
173
174 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
175 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
176 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
177 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
178
179 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
180 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
181 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
182 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
183 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
184 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
185 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
186 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
187 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
188 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
189 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
190
191 #define M8XX_PCMCIA_POR_VALID 0x00000001
192 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
193 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
194 #define M8XX_PCMCIA_POR_IO 0x00000018
195 #define M8XX_PCMCIA_POR_16BIT 0x00000040
196
197 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
198
199 #define M8XX_PGCRX_CXOE 0x00000080
200 #define M8XX_PGCRX_CXRESET 0x00000040
201
202 /* we keep one lookup table per socket to check flags */
203
204 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
205
206 struct event_table {
207 u32 regbit;
208 u32 eventbit;
209 };
210
211 static const char driver_name[] = "m8xx-pcmcia";
212
213 struct socket_info {
214 void (*handler) (void *info, u32 events);
215 void *info;
216
217 u32 slot;
218 pcmconf8xx_t *pcmcia;
219 u32 bus_freq;
220 int hwirq;
221
222 socket_state_t state;
223 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
224 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
225 struct event_table events[PCMCIA_EVENTS_MAX];
226 struct pcmcia_socket socket;
227 };
228
229 static struct socket_info socket[PCMCIA_SOCKETS_NO];
230
231 /*
232 * Search this table to see if the windowsize is
233 * supported...
234 */
235
236 #define M8XX_SIZES_NO 32
237
238 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
239 0x00000001, 0x00000002, 0x00000008, 0x00000004,
240 0x00000080, 0x00000040, 0x00000010, 0x00000020,
241 0x00008000, 0x00004000, 0x00001000, 0x00002000,
242 0x00000100, 0x00000200, 0x00000800, 0x00000400,
243
244 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
245 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
246 0x00010000, 0x00020000, 0x00080000, 0x00040000,
247 0x00800000, 0x00400000, 0x00100000, 0x00200000
248 };
249
250 /* ------------------------------------------------------------------------- */
251
252 static irqreturn_t m8xx_interrupt(int irq, void *dev);
253
254 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
255
256 /* ------------------------------------------------------------------------- */
257 /* board specific stuff: */
258 /* voltage_set(), hardware_enable() and hardware_disable() */
259 /* ------------------------------------------------------------------------- */
260 /* RPX Boards from Embedded Planet */
261
262 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
263
264 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
265 * SYPCR is write once only, therefore must the slowest memory be faster
266 * than the bus monitor or we will get a machine check due to the bus timeout.
267 */
268
269 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
270
271 #undef PCMCIA_BMT_LIMIT
272 #define PCMCIA_BMT_LIMIT (6*8)
273
274 static int voltage_set(int slot, int vcc, int vpp)
275 {
276 u32 reg = 0;
277
278 switch (vcc) {
279 case 0:
280 break;
281 case 33:
282 reg |= BCSR1_PCVCTL4;
283 break;
284 case 50:
285 reg |= BCSR1_PCVCTL5;
286 break;
287 default:
288 return 1;
289 }
290
291 switch (vpp) {
292 case 0:
293 break;
294 case 33:
295 case 50:
296 if (vcc == vpp)
297 reg |= BCSR1_PCVCTL6;
298 else
299 return 1;
300 break;
301 case 120:
302 reg |= BCSR1_PCVCTL7;
303 default:
304 return 1;
305 }
306
307 if (!((vcc == 50) || (vcc == 0)))
308 return 1;
309
310 /* first, turn off all power */
311
312 out_be32(((u32 *) RPX_CSR_ADDR),
313 in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
314 BCSR1_PCVCTL5 |
315 BCSR1_PCVCTL6 |
316 BCSR1_PCVCTL7));
317
318 /* enable new powersettings */
319
320 out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
321
322 return 0;
323 }
324
325 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
326 #define hardware_enable(_slot_) /* No hardware to enable */
327 #define hardware_disable(_slot_) /* No hardware to disable */
328
329 #endif /* CONFIG_RPXCLASSIC */
330
331 /* FADS Boards from Motorola */
332
333 #if defined(CONFIG_FADS)
334
335 #define PCMCIA_BOARD_MSG "FADS"
336
337 static int voltage_set(int slot, int vcc, int vpp)
338 {
339 u32 reg = 0;
340
341 switch (vcc) {
342 case 0:
343 break;
344 case 33:
345 reg |= BCSR1_PCCVCC0;
346 break;
347 case 50:
348 reg |= BCSR1_PCCVCC1;
349 break;
350 default:
351 return 1;
352 }
353
354 switch (vpp) {
355 case 0:
356 break;
357 case 33:
358 case 50:
359 if (vcc == vpp)
360 reg |= BCSR1_PCCVPP1;
361 else
362 return 1;
363 break;
364 case 120:
365 if ((vcc == 33) || (vcc == 50))
366 reg |= BCSR1_PCCVPP0;
367 else
368 return 1;
369 default:
370 return 1;
371 }
372
373 /* first, turn off all power */
374 out_be32((u32 *) BCSR1,
375 in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
376 BCSR1_PCCVPP_MASK));
377
378 /* enable new powersettings */
379 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
380
381 return 0;
382 }
383
384 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
385
386 static void hardware_enable(int slot)
387 {
388 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
389 }
390
391 static void hardware_disable(int slot)
392 {
393 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
394 }
395
396 #endif
397
398 /* MPC885ADS Boards */
399
400 #if defined(CONFIG_MPC885ADS)
401
402 #define PCMCIA_BOARD_MSG "MPC885ADS"
403 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
404
405 static inline void hardware_enable(int slot)
406 {
407 m8xx_pcmcia_ops.hw_ctrl(slot, 1);
408 }
409
410 static inline void hardware_disable(int slot)
411 {
412 m8xx_pcmcia_ops.hw_ctrl(slot, 0);
413 }
414
415 static inline int voltage_set(int slot, int vcc, int vpp)
416 {
417 return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
418 }
419
420 #endif
421
422 /* ------------------------------------------------------------------------- */
423 /* Motorola MBX860 */
424
425 #if defined(CONFIG_MBX)
426
427 #define PCMCIA_BOARD_MSG "MBX"
428
429 static int voltage_set(int slot, int vcc, int vpp)
430 {
431 u8 reg = 0;
432
433 switch (vcc) {
434 case 0:
435 break;
436 case 33:
437 reg |= CSR2_VCC_33;
438 break;
439 case 50:
440 reg |= CSR2_VCC_50;
441 break;
442 default:
443 return 1;
444 }
445
446 switch (vpp) {
447 case 0:
448 break;
449 case 33:
450 case 50:
451 if (vcc == vpp)
452 reg |= CSR2_VPP_VCC;
453 else
454 return 1;
455 break;
456 case 120:
457 if ((vcc == 33) || (vcc == 50))
458 reg |= CSR2_VPP_12;
459 else
460 return 1;
461 default:
462 return 1;
463 }
464
465 /* first, turn off all power */
466 out_8((u8 *) MBX_CSR2_ADDR,
467 in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
468
469 /* enable new powersettings */
470 out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
471
472 return 0;
473 }
474
475 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
476 #define hardware_enable(_slot_) /* No hardware to enable */
477 #define hardware_disable(_slot_) /* No hardware to disable */
478
479 #endif /* CONFIG_MBX */
480
481 #if defined(CONFIG_PRxK)
482 #include <asm/cpld.h>
483 extern volatile fpga_pc_regs *fpga_pc;
484
485 #define PCMCIA_BOARD_MSG "MPC855T"
486
487 static int voltage_set(int slot, int vcc, int vpp)
488 {
489 u8 reg = 0;
490 u8 regread;
491 cpld_regs *ccpld = get_cpld();
492
493 switch (vcc) {
494 case 0:
495 break;
496 case 33:
497 reg |= PCMCIA_VCC_33;
498 break;
499 case 50:
500 reg |= PCMCIA_VCC_50;
501 break;
502 default:
503 return 1;
504 }
505
506 switch (vpp) {
507 case 0:
508 break;
509 case 33:
510 case 50:
511 if (vcc == vpp)
512 reg |= PCMCIA_VPP_VCC;
513 else
514 return 1;
515 break;
516 case 120:
517 if ((vcc == 33) || (vcc == 50))
518 reg |= PCMCIA_VPP_12;
519 else
520 return 1;
521 default:
522 return 1;
523 }
524
525 reg = reg >> (slot << 2);
526 regread = in_8(&ccpld->fpga_pc_ctl);
527 if (reg !=
528 (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
529 /* enable new powersettings */
530 regread =
531 regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
532 (slot << 2));
533 out_8(&ccpld->fpga_pc_ctl, reg | regread);
534 msleep(100);
535 }
536
537 return 0;
538 }
539
540 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
541 #define hardware_enable(_slot_) /* No hardware to enable */
542 #define hardware_disable(_slot_) /* No hardware to disable */
543
544 #endif /* CONFIG_PRxK */
545
546 static u32 pending_events[PCMCIA_SOCKETS_NO];
547 static DEFINE_SPINLOCK(pending_event_lock);
548
549 static irqreturn_t m8xx_interrupt(int irq, void *dev)
550 {
551 struct socket_info *s;
552 struct event_table *e;
553 unsigned int i, events, pscr, pipr, per;
554 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
555
556 pr_debug("m8xx_pcmcia: Interrupt!\n");
557 /* get interrupt sources */
558
559 pscr = in_be32(&pcmcia->pcmc_pscr);
560 pipr = in_be32(&pcmcia->pcmc_pipr);
561 per = in_be32(&pcmcia->pcmc_per);
562
563 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
564 s = &socket[i];
565 e = &s->events[0];
566 events = 0;
567
568 while (e->regbit) {
569 if (pscr & e->regbit)
570 events |= e->eventbit;
571
572 e++;
573 }
574
575 /*
576 * report only if both card detect signals are the same
577 * not too nice done,
578 * we depend on that CD2 is the bit to the left of CD1...
579 */
580 if (events & SS_DETECT)
581 if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
582 (pipr & M8XX_PCMCIA_CD1(i))) {
583 events &= ~SS_DETECT;
584 }
585 #ifdef PCMCIA_GLITCHY_CD
586 /*
587 * I've experienced CD problems with my ADS board.
588 * We make an extra check to see if there was a
589 * real change of Card detection.
590 */
591
592 if ((events & SS_DETECT) &&
593 ((pipr &
594 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
595 (s->state.Vcc | s->state.Vpp)) {
596 events &= ~SS_DETECT;
597 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
598 (pipr & (M8XX_PCMCIA_CD2(i)
599 | M8XX_PCMCIA_CD1(i)))); */
600 }
601 #endif
602
603 /* call the handler */
604
605 pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
606 "pipr = 0x%08x\n", i, events, pscr, pipr);
607
608 if (events) {
609 spin_lock(&pending_event_lock);
610 pending_events[i] |= events;
611 spin_unlock(&pending_event_lock);
612 /*
613 * Turn off RDY_L bits in the PER mask on
614 * CD interrupt receival.
615 *
616 * They can generate bad interrupts on the
617 * ACS4,8,16,32. - marcelo
618 */
619 per &= ~M8XX_PCMCIA_RDY_L(0);
620 per &= ~M8XX_PCMCIA_RDY_L(1);
621
622 out_be32(&pcmcia->pcmc_per, per);
623
624 if (events)
625 pcmcia_parse_events(&socket[i].socket, events);
626 }
627 }
628
629 /* clear the interrupt sources */
630 out_be32(&pcmcia->pcmc_pscr, pscr);
631
632 pr_debug("m8xx_pcmcia: Interrupt done.\n");
633
634 return IRQ_HANDLED;
635 }
636
637 static u32 m8xx_get_graycode(u32 size)
638 {
639 u32 k;
640
641 for (k = 0; k < M8XX_SIZES_NO; k++)
642 if (m8xx_size_to_gray[k] == size)
643 break;
644
645 if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
646 k = -1;
647
648 return k;
649 }
650
651 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
652 {
653 u32 reg, clocks, psst, psl, psht;
654
655 if (!ns) {
656
657 /*
658 * We get called with IO maps setup to 0ns
659 * if not specified by the user.
660 * They should be 255ns.
661 */
662
663 if (is_io)
664 ns = 255;
665 else
666 ns = 100; /* fast memory if 0 */
667 }
668
669 /*
670 * In PSST, PSL, PSHT fields we tell the controller
671 * timing parameters in CLKOUT clock cycles.
672 * CLKOUT is the same as GCLK2_50.
673 */
674
675 /* how we want to adjust the timing - in percent */
676
677 #define ADJ 180 /* 80 % longer accesstime - to be sure */
678
679 clocks = ((bus_freq / 1000) * ns) / 1000;
680 clocks = (clocks * ADJ) / (100 * 1000);
681 if (clocks >= PCMCIA_BMT_LIMIT) {
682 printk("Max access time limit reached\n");
683 clocks = PCMCIA_BMT_LIMIT - 1;
684 }
685
686 psst = clocks / 7; /* setup time */
687 psht = clocks / 7; /* hold time */
688 psl = (clocks * 5) / 7; /* strobe length */
689
690 psst += clocks - (psst + psht + psl);
691
692 reg = psst << 12;
693 reg |= psl << 7;
694 reg |= psht << 16;
695
696 return reg;
697 }
698
699 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
700 {
701 int lsock = container_of(sock, struct socket_info, socket)->slot;
702 struct socket_info *s = &socket[lsock];
703 unsigned int pipr, reg;
704 pcmconf8xx_t *pcmcia = s->pcmcia;
705
706 pipr = in_be32(&pcmcia->pcmc_pipr);
707
708 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
709 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
710 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
711
712 if (s->state.flags & SS_IOCARD)
713 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
714 else {
715 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
716 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
717 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
718 }
719
720 if (s->state.Vcc | s->state.Vpp)
721 *value |= SS_POWERON;
722
723 /*
724 * Voltage detection:
725 * This driver only supports 16-Bit pc-cards.
726 * Cardbus is not handled here.
727 *
728 * To determine what voltage to use we must read the VS1 and VS2 pin.
729 * Depending on what socket type is present,
730 * different combinations mean different things.
731 *
732 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
733 *
734 * 5V 5V, LV* NC NC 5V only 5V (if available)
735 *
736 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
737 *
738 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
739 *
740 * LV* 5V - - shall not fit into socket
741 *
742 * LV* LV* GND NC 3.3V only 3.3V
743 *
744 * LV* LV* NC GND x.xV x.xV (if avail.)
745 *
746 * LV* LV* GND GND 3.3 or x.xV as low as possible
747 *
748 * *LV means Low Voltage
749 *
750 *
751 * That gives us the following table:
752 *
753 * Socket VS1 VS2 Voltage
754 *
755 * 5V NC NC 5V
756 * 5V NC GND none (should not be possible)
757 * 5V GND NC >= 3.3V
758 * 5V GND GND >= x.xV
759 *
760 * LV NC NC 5V (if available)
761 * LV NC GND x.xV (if available)
762 * LV GND NC 3.3V
763 * LV GND GND >= x.xV
764 *
765 * So, how do I determine if I have a 5V or a LV
766 * socket on my board? Look at the socket!
767 *
768 *
769 * Socket with 5V key:
770 * ++--------------------------------------------+
771 * || |
772 * || ||
773 * || ||
774 * | |
775 * +---------------------------------------------+
776 *
777 * Socket with LV key:
778 * ++--------------------------------------------+
779 * || |
780 * | ||
781 * | ||
782 * | |
783 * +---------------------------------------------+
784 *
785 *
786 * With other words - LV only cards does not fit
787 * into the 5V socket!
788 */
789
790 /* read out VS1 and VS2 */
791
792 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
793 >> M8XX_PCMCIA_VS_SHIFT(lsock);
794
795 if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
796 switch (reg) {
797 case 1:
798 *value |= SS_3VCARD;
799 break; /* GND, NC - 3.3V only */
800 case 2:
801 *value |= SS_XVCARD;
802 break; /* NC. GND - x.xV only */
803 };
804 }
805
806 pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
807 return 0;
808 }
809
810 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
811 {
812 int lsock = container_of(sock, struct socket_info, socket)->slot;
813 struct socket_info *s = &socket[lsock];
814 struct event_table *e;
815 unsigned int reg;
816 unsigned long flags;
817 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
818
819 pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
820 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
821 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
822
823 /* First, set voltage - bail out if invalid */
824 if (voltage_set(lsock, state->Vcc, state->Vpp))
825 return -EINVAL;
826
827 /* Take care of reset... */
828 if (state->flags & SS_RESET)
829 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
830 else
831 out_be32(M8XX_PGCRX(lsock),
832 in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
833
834 /* ... and output enable. */
835
836 /* The CxOE signal is connected to a 74541 on the ADS.
837 I guess most other boards used the ADS as a reference.
838 I tried to control the CxOE signal with SS_OUTPUT_ENA,
839 but the reset signal seems connected via the 541.
840 If the CxOE is left high are some signals tristated and
841 no pullups are present -> the cards act weird.
842 So right now the buffers are enabled if the power is on. */
843
844 if (state->Vcc || state->Vpp)
845 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
846 else
847 out_be32(M8XX_PGCRX(lsock),
848 in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
849
850 /*
851 * We'd better turn off interrupts before
852 * we mess with the events-table..
853 */
854
855 spin_lock_irqsave(&events_lock, flags);
856
857 /*
858 * Play around with the interrupt mask to be able to
859 * give the events the generic pcmcia driver wants us to.
860 */
861
862 e = &s->events[0];
863 reg = 0;
864
865 if (state->csc_mask & SS_DETECT) {
866 e->eventbit = SS_DETECT;
867 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
868 | M8XX_PCMCIA_CD1(lsock));
869 e++;
870 }
871 if (state->flags & SS_IOCARD) {
872 /*
873 * I/O card
874 */
875 if (state->csc_mask & SS_STSCHG) {
876 e->eventbit = SS_STSCHG;
877 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
878 e++;
879 }
880 /*
881 * If io_irq is non-zero we should enable irq.
882 */
883 if (state->io_irq) {
884 out_be32(M8XX_PGCRX(lsock),
885 in_be32(M8XX_PGCRX(lsock)) |
886 mk_int_int_mask(s->hwirq) << 24);
887 /*
888 * Strange thing here:
889 * The manual does not tell us which interrupt
890 * the sources generate.
891 * Anyhow, I found out that RDY_L generates IREQLVL.
892 *
893 * We use level triggerd interrupts, and they don't
894 * have to be cleared in PSCR in the interrupt handler.
895 */
896 reg |= M8XX_PCMCIA_RDY_L(lsock);
897 } else
898 out_be32(M8XX_PGCRX(lsock),
899 in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
900 } else {
901 /*
902 * Memory card
903 */
904 if (state->csc_mask & SS_BATDEAD) {
905 e->eventbit = SS_BATDEAD;
906 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
907 e++;
908 }
909 if (state->csc_mask & SS_BATWARN) {
910 e->eventbit = SS_BATWARN;
911 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
912 e++;
913 }
914 /* What should I trigger on - low/high,raise,fall? */
915 if (state->csc_mask & SS_READY) {
916 e->eventbit = SS_READY;
917 reg |= e->regbit = 0; //??
918 e++;
919 }
920 }
921
922 e->regbit = 0; /* terminate list */
923
924 /*
925 * Clear the status changed .
926 * Port A and Port B share the same port.
927 * Writing ones will clear the bits.
928 */
929
930 out_be32(&pcmcia->pcmc_pscr, reg);
931
932 /*
933 * Write the mask.
934 * Port A and Port B share the same port.
935 * Need for read-modify-write.
936 * Ones will enable the interrupt.
937 */
938
939 reg |=
940 in_be32(&pcmcia->
941 pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
942 out_be32(&pcmcia->pcmc_per, reg);
943
944 spin_unlock_irqrestore(&events_lock, flags);
945
946 /* copy the struct and modify the copy */
947
948 s->state = *state;
949
950 return 0;
951 }
952
953 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
954 {
955 int lsock = container_of(sock, struct socket_info, socket)->slot;
956
957 struct socket_info *s = &socket[lsock];
958 struct pcmcia_win *w;
959 unsigned int reg, winnr;
960 pcmconf8xx_t *pcmcia = s->pcmcia;
961
962 #define M8XX_SIZE (io->stop - io->start + 1)
963 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
964
965 pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
966 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
967 io->speed, (unsigned long long)io->start,
968 (unsigned long long)io->stop);
969
970 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
971 || (io->stop > 0xffff) || (io->stop < io->start))
972 return -EINVAL;
973
974 if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
975 return -EINVAL;
976
977 if (io->flags & MAP_ACTIVE) {
978
979 pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
980
981 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
982 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
983
984 /* setup registers */
985
986 w = (void *)&pcmcia->pcmc_pbr0;
987 w += winnr;
988
989 out_be32(&w->or, 0); /* turn off window first */
990 out_be32(&w->br, M8XX_BASE);
991
992 reg <<= 27;
993 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
994
995 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
996
997 if (io->flags & MAP_WRPROT)
998 reg |= M8XX_PCMCIA_POR_WRPROT;
999
1000 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1001 if (io->flags & MAP_16BIT)
1002 reg |= M8XX_PCMCIA_POR_16BIT;
1003
1004 if (io->flags & MAP_ACTIVE)
1005 reg |= M8XX_PCMCIA_POR_VALID;
1006
1007 out_be32(&w->or, reg);
1008
1009 pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
1010 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1011 } else {
1012 /* shutdown IO window */
1013 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1014 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1015
1016 /* setup registers */
1017
1018 w = (void *)&pcmcia->pcmc_pbr0;
1019 w += winnr;
1020
1021 out_be32(&w->or, 0); /* turn off window */
1022 out_be32(&w->br, 0); /* turn off base address */
1023
1024 pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
1025 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1026 }
1027
1028 /* copy the struct and modify the copy */
1029 s->io_win[io->map] = *io;
1030 s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1031 pr_debug("m8xx_pcmcia: SetIOMap exit\n");
1032
1033 return 0;
1034 }
1035
1036 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1037 struct pccard_mem_map *mem)
1038 {
1039 int lsock = container_of(sock, struct socket_info, socket)->slot;
1040 struct socket_info *s = &socket[lsock];
1041 struct pcmcia_win *w;
1042 struct pccard_mem_map *old;
1043 unsigned int reg, winnr;
1044 pcmconf8xx_t *pcmcia = s->pcmcia;
1045
1046 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1047 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1048 mem->speed, (unsigned long long)mem->static_start,
1049 mem->card_start);
1050
1051 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1052 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1053 || (mem->card_start >= 0x04000000)
1054 || (mem->static_start & 0xfff) /* 4KByte resolution */
1055 ||(mem->card_start & 0xfff))
1056 return -EINVAL;
1057
1058 if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1059 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1060 return -EINVAL;
1061 }
1062 reg <<= 27;
1063
1064 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1065
1066 /* Setup the window in the pcmcia controller */
1067
1068 w = (void *)&pcmcia->pcmc_pbr0;
1069 w += winnr;
1070
1071 reg |= lsock << 2;
1072
1073 reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1074
1075 if (mem->flags & MAP_ATTRIB)
1076 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1077
1078 if (mem->flags & MAP_WRPROT)
1079 reg |= M8XX_PCMCIA_POR_WRPROT;
1080
1081 if (mem->flags & MAP_16BIT)
1082 reg |= M8XX_PCMCIA_POR_16BIT;
1083
1084 if (mem->flags & MAP_ACTIVE)
1085 reg |= M8XX_PCMCIA_POR_VALID;
1086
1087 out_be32(&w->or, reg);
1088
1089 pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1090 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1091
1092 if (mem->flags & MAP_ACTIVE) {
1093 /* get the new base address */
1094 mem->static_start = PCMCIA_MEM_WIN_BASE +
1095 (PCMCIA_MEM_WIN_SIZE * winnr)
1096 + mem->card_start;
1097 }
1098
1099 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1100 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1101 mem->speed, (unsigned long long)mem->static_start,
1102 mem->card_start);
1103
1104 /* copy the struct and modify the copy */
1105
1106 old = &s->mem_win[mem->map];
1107
1108 *old = *mem;
1109 old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1110
1111 return 0;
1112 }
1113
1114 static int m8xx_sock_init(struct pcmcia_socket *sock)
1115 {
1116 int i;
1117 pccard_io_map io = { 0, 0, 0, 0, 1 };
1118 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1119
1120 pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1121
1122 m8xx_set_socket(sock, &dead_socket);
1123 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1124 io.map = i;
1125 m8xx_set_io_map(sock, &io);
1126 }
1127 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1128 mem.map = i;
1129 m8xx_set_mem_map(sock, &mem);
1130 }
1131
1132 return 0;
1133
1134 }
1135
1136 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1137 {
1138 return m8xx_set_socket(sock, &dead_socket);
1139 }
1140
1141 static struct pccard_operations m8xx_services = {
1142 .init = m8xx_sock_init,
1143 .suspend = m8xx_sock_suspend,
1144 .get_status = m8xx_get_status,
1145 .set_socket = m8xx_set_socket,
1146 .set_io_map = m8xx_set_io_map,
1147 .set_mem_map = m8xx_set_mem_map,
1148 };
1149
1150 static int __init m8xx_probe(struct platform_device *ofdev)
1151 {
1152 struct pcmcia_win *w;
1153 unsigned int i, m, hwirq;
1154 pcmconf8xx_t *pcmcia;
1155 int status;
1156 struct device_node *np = ofdev->dev.of_node;
1157
1158 pcmcia_info("%s\n", version);
1159
1160 pcmcia = of_iomap(np, 0);
1161 if (pcmcia == NULL)
1162 return -EINVAL;
1163
1164 pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1165 hwirq = irq_map[pcmcia_schlvl].hwirq;
1166 if (pcmcia_schlvl < 0) {
1167 iounmap(pcmcia);
1168 return -EINVAL;
1169 }
1170
1171 m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1172 m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1173
1174 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1175 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1176
1177 /* Configure Status change interrupt */
1178
1179 if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1180 driver_name, socket)) {
1181 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1182 pcmcia_schlvl);
1183 iounmap(pcmcia);
1184 return -1;
1185 }
1186
1187 w = (void *)&pcmcia->pcmc_pbr0;
1188
1189 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1190 clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1191
1192 /* connect interrupt and disable CxOE */
1193
1194 out_be32(M8XX_PGCRX(0),
1195 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1196 out_be32(M8XX_PGCRX(1),
1197 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1198
1199 /* initialize the fixed memory windows */
1200
1201 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1202 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1203 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1204 (PCMCIA_MEM_WIN_SIZE
1205 * (m + i * PCMCIA_MEM_WIN_NO)));
1206
1207 out_be32(&w->or, 0); /* set to not valid */
1208
1209 w++;
1210 }
1211 }
1212
1213 /* turn off voltage */
1214 voltage_set(0, 0, 0);
1215 voltage_set(1, 0, 0);
1216
1217 /* Enable external hardware */
1218 hardware_enable(0);
1219 hardware_enable(1);
1220
1221 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1222 socket[i].slot = i;
1223 socket[i].socket.owner = THIS_MODULE;
1224 socket[i].socket.features =
1225 SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1226 socket[i].socket.irq_mask = 0x000;
1227 socket[i].socket.map_size = 0x1000;
1228 socket[i].socket.io_offset = 0;
1229 socket[i].socket.pci_irq = pcmcia_schlvl;
1230 socket[i].socket.ops = &m8xx_services;
1231 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1232 socket[i].socket.cb_dev = NULL;
1233 socket[i].socket.dev.parent = &ofdev->dev;
1234 socket[i].pcmcia = pcmcia;
1235 socket[i].bus_freq = ppc_proc_freq;
1236 socket[i].hwirq = hwirq;
1237
1238 }
1239
1240 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1241 status = pcmcia_register_socket(&socket[i].socket);
1242 if (status < 0)
1243 pcmcia_error("Socket register failed\n");
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int m8xx_remove(struct platform_device *ofdev)
1250 {
1251 u32 m, i;
1252 struct pcmcia_win *w;
1253 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1254
1255 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1256 w = (void *)&pcmcia->pcmc_pbr0;
1257
1258 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1259 out_be32(&pcmcia->pcmc_per,
1260 in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1261
1262 /* turn off interrupt and disable CxOE */
1263 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1264
1265 /* turn off memory windows */
1266 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1267 out_be32(&w->or, 0); /* set to not valid */
1268 w++;
1269 }
1270
1271 /* turn off voltage */
1272 voltage_set(i, 0, 0);
1273
1274 /* disable external hardware */
1275 hardware_disable(i);
1276 }
1277 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1278 pcmcia_unregister_socket(&socket[i].socket);
1279 iounmap(pcmcia);
1280
1281 free_irq(pcmcia_schlvl, NULL);
1282
1283 return 0;
1284 }
1285
1286 static const struct of_device_id m8xx_pcmcia_match[] = {
1287 {
1288 .type = "pcmcia",
1289 .compatible = "fsl,pq-pcmcia",
1290 },
1291 {},
1292 };
1293
1294 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1295
1296 static struct platform_driver m8xx_pcmcia_driver = {
1297 .driver = {
1298 .name = driver_name,
1299 .owner = THIS_MODULE,
1300 .of_match_table = m8xx_pcmcia_match,
1301 },
1302 .probe = m8xx_probe,
1303 .remove = m8xx_remove,
1304 };
1305
1306 module_platform_driver(m8xx_pcmcia_driver);
Linux with added FPC-III support