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Revert "radeon, kdb, kms: Save and restore the LUT on atomic KMS enter/exit"
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_display.c
blob0383631da69c42db417f27f6b87ddf58f19eb24e
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99 }
100
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102 {
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123 }
124
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
126 {
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139 }
140
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144 {
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150 }
151
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155 {
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161 }
162
163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t start, uint32_t size)
165 {
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 /* userspace palettes are always correct as is */
170 for (i = start; i < end; i++) {
171 radeon_crtc->lut_r[i] = red[i] >> 6;
172 radeon_crtc->lut_g[i] = green[i] >> 6;
173 radeon_crtc->lut_b[i] = blue[i] >> 6;
174 }
175 radeon_crtc_load_lut(crtc);
176 }
177
178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
179 {
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
181
182 drm_crtc_cleanup(crtc);
183 kfree(radeon_crtc);
184 }
185
186 static const struct drm_crtc_funcs radeon_crtc_funcs = {
187 .cursor_set = radeon_crtc_cursor_set,
188 .cursor_move = radeon_crtc_cursor_move,
189 .gamma_set = radeon_crtc_gamma_set,
190 .set_config = drm_crtc_helper_set_config,
191 .destroy = radeon_crtc_destroy,
192 };
193
194 static void radeon_crtc_init(struct drm_device *dev, int index)
195 {
196 struct radeon_device *rdev = dev->dev_private;
197 struct radeon_crtc *radeon_crtc;
198 int i;
199
200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
201 if (radeon_crtc == NULL)
202 return;
203
204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
205
206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
207 radeon_crtc->crtc_id = index;
208 rdev->mode_info.crtcs[index] = radeon_crtc;
209
210 #if 0
211 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
212 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
213 radeon_crtc->mode_set.num_connectors = 0;
214 #endif
215
216 for (i = 0; i < 256; i++) {
217 radeon_crtc->lut_r[i] = i << 2;
218 radeon_crtc->lut_g[i] = i << 2;
219 radeon_crtc->lut_b[i] = i << 2;
220 }
221
222 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
223 radeon_atombios_init_crtc(dev, radeon_crtc);
224 else
225 radeon_legacy_init_crtc(dev, radeon_crtc);
226 }
227
228 static const char *encoder_names[34] = {
229 "NONE",
230 "INTERNAL_LVDS",
231 "INTERNAL_TMDS1",
232 "INTERNAL_TMDS2",
233 "INTERNAL_DAC1",
234 "INTERNAL_DAC2",
235 "INTERNAL_SDVOA",
236 "INTERNAL_SDVOB",
237 "SI170B",
238 "CH7303",
239 "CH7301",
240 "INTERNAL_DVO1",
241 "EXTERNAL_SDVOA",
242 "EXTERNAL_SDVOB",
243 "TITFP513",
244 "INTERNAL_LVTM1",
245 "VT1623",
246 "HDMI_SI1930",
247 "HDMI_INTERNAL",
248 "INTERNAL_KLDSCP_TMDS1",
249 "INTERNAL_KLDSCP_DVO1",
250 "INTERNAL_KLDSCP_DAC1",
251 "INTERNAL_KLDSCP_DAC2",
252 "SI178",
253 "MVPU_FPGA",
254 "INTERNAL_DDI",
255 "VT1625",
256 "HDMI_SI1932",
257 "DP_AN9801",
258 "DP_DP501",
259 "INTERNAL_UNIPHY",
260 "INTERNAL_KLDSCP_LVTMA",
261 "INTERNAL_UNIPHY1",
262 "INTERNAL_UNIPHY2",
263 };
264
265 static const char *connector_names[15] = {
266 "Unknown",
267 "VGA",
268 "DVI-I",
269 "DVI-D",
270 "DVI-A",
271 "Composite",
272 "S-video",
273 "LVDS",
274 "Component",
275 "DIN",
276 "DisplayPort",
277 "HDMI-A",
278 "HDMI-B",
279 "TV",
280 "eDP",
281 };
282
283 static const char *hpd_names[6] = {
284 "HPD1",
285 "HPD2",
286 "HPD3",
287 "HPD4",
288 "HPD5",
289 "HPD6",
290 };
291
292 static void radeon_print_display_setup(struct drm_device *dev)
293 {
294 struct drm_connector *connector;
295 struct radeon_connector *radeon_connector;
296 struct drm_encoder *encoder;
297 struct radeon_encoder *radeon_encoder;
298 uint32_t devices;
299 int i = 0;
300
301 DRM_INFO("Radeon Display Connectors\n");
302 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
303 radeon_connector = to_radeon_connector(connector);
304 DRM_INFO("Connector %d:\n", i);
305 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
306 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
307 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
308 if (radeon_connector->ddc_bus) {
309 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
310 radeon_connector->ddc_bus->rec.mask_clk_reg,
311 radeon_connector->ddc_bus->rec.mask_data_reg,
312 radeon_connector->ddc_bus->rec.a_clk_reg,
313 radeon_connector->ddc_bus->rec.a_data_reg,
314 radeon_connector->ddc_bus->rec.en_clk_reg,
315 radeon_connector->ddc_bus->rec.en_data_reg,
316 radeon_connector->ddc_bus->rec.y_clk_reg,
317 radeon_connector->ddc_bus->rec.y_data_reg);
318 if (radeon_connector->router_bus)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.mux_control_pin,
321 radeon_connector->router.mux_state);
322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
325 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
326 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
327 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
330 }
331 DRM_INFO(" Encoders:\n");
332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
333 radeon_encoder = to_radeon_encoder(encoder);
334 devices = radeon_encoder->devices & radeon_connector->devices;
335 if (devices) {
336 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
337 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
338 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
339 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
340 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
341 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
343 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
345 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
347 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
353 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_TV1_SUPPORT)
355 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
356 if (devices & ATOM_DEVICE_CV_SUPPORT)
357 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
358 }
359 }
360 i++;
361 }
362 }
363
364 static bool radeon_setup_enc_conn(struct drm_device *dev)
365 {
366 struct radeon_device *rdev = dev->dev_private;
367 struct drm_connector *drm_connector;
368 bool ret = false;
369
370 if (rdev->bios) {
371 if (rdev->is_atom_bios) {
372 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
373 if (ret == false)
374 ret = radeon_get_atom_connector_info_from_object_table(dev);
375 } else {
376 ret = radeon_get_legacy_connector_info_from_bios(dev);
377 if (ret == false)
378 ret = radeon_get_legacy_connector_info_from_table(dev);
379 }
380 } else {
381 if (!ASIC_IS_AVIVO(rdev))
382 ret = radeon_get_legacy_connector_info_from_table(dev);
383 }
384 if (ret) {
385 radeon_setup_encoder_clones(dev);
386 radeon_print_display_setup(dev);
387 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
388 radeon_ddc_dump(drm_connector);
389 }
390
391 return ret;
392 }
393
394 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
395 {
396 struct drm_device *dev = radeon_connector->base.dev;
397 struct radeon_device *rdev = dev->dev_private;
398 int ret = 0;
399
400 /* on hw with routers, select right port */
401 if (radeon_connector->router.valid)
402 radeon_router_select_port(radeon_connector);
403
404 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
405 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
406 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
407 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
408 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
409 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
410 }
411 if (!radeon_connector->ddc_bus)
412 return -1;
413 if (!radeon_connector->edid) {
414 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
415 }
416 /* some servers provide a hardcoded edid in rom for KVMs */
417 if (!radeon_connector->edid)
418 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
419 if (radeon_connector->edid) {
420 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
421 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
422 return ret;
423 }
424 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
425 return 0;
426 }
427
428 static int radeon_ddc_dump(struct drm_connector *connector)
429 {
430 struct edid *edid;
431 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
432 int ret = 0;
433
434 /* on hw with routers, select right port */
435 if (radeon_connector->router.valid)
436 radeon_router_select_port(radeon_connector);
437
438 if (!radeon_connector->ddc_bus)
439 return -1;
440 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
441 if (edid) {
442 kfree(edid);
443 }
444 return ret;
445 }
446
447 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
448 {
449 uint64_t mod;
450
451 n += d / 2;
452
453 mod = do_div(n, d);
454 return n;
455 }
456
457 void radeon_compute_pll(struct radeon_pll *pll,
458 uint64_t freq,
459 uint32_t *dot_clock_p,
460 uint32_t *fb_div_p,
461 uint32_t *frac_fb_div_p,
462 uint32_t *ref_div_p,
463 uint32_t *post_div_p)
464 {
465 uint32_t min_ref_div = pll->min_ref_div;
466 uint32_t max_ref_div = pll->max_ref_div;
467 uint32_t min_post_div = pll->min_post_div;
468 uint32_t max_post_div = pll->max_post_div;
469 uint32_t min_fractional_feed_div = 0;
470 uint32_t max_fractional_feed_div = 0;
471 uint32_t best_vco = pll->best_vco;
472 uint32_t best_post_div = 1;
473 uint32_t best_ref_div = 1;
474 uint32_t best_feedback_div = 1;
475 uint32_t best_frac_feedback_div = 0;
476 uint32_t best_freq = -1;
477 uint32_t best_error = 0xffffffff;
478 uint32_t best_vco_diff = 1;
479 uint32_t post_div;
480 u32 pll_out_min, pll_out_max;
481
482 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
483 freq = freq * 1000;
484
485 if (pll->flags & RADEON_PLL_IS_LCD) {
486 pll_out_min = pll->lcd_pll_out_min;
487 pll_out_max = pll->lcd_pll_out_max;
488 } else {
489 pll_out_min = pll->pll_out_min;
490 pll_out_max = pll->pll_out_max;
491 }
492
493 if (pll->flags & RADEON_PLL_USE_REF_DIV)
494 min_ref_div = max_ref_div = pll->reference_div;
495 else {
496 while (min_ref_div < max_ref_div-1) {
497 uint32_t mid = (min_ref_div + max_ref_div) / 2;
498 uint32_t pll_in = pll->reference_freq / mid;
499 if (pll_in < pll->pll_in_min)
500 max_ref_div = mid;
501 else if (pll_in > pll->pll_in_max)
502 min_ref_div = mid;
503 else
504 break;
505 }
506 }
507
508 if (pll->flags & RADEON_PLL_USE_POST_DIV)
509 min_post_div = max_post_div = pll->post_div;
510
511 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
512 min_fractional_feed_div = pll->min_frac_feedback_div;
513 max_fractional_feed_div = pll->max_frac_feedback_div;
514 }
515
516 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
517 uint32_t ref_div;
518
519 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
520 continue;
521
522 /* legacy radeons only have a few post_divs */
523 if (pll->flags & RADEON_PLL_LEGACY) {
524 if ((post_div == 5) ||
525 (post_div == 7) ||
526 (post_div == 9) ||
527 (post_div == 10) ||
528 (post_div == 11) ||
529 (post_div == 13) ||
530 (post_div == 14) ||
531 (post_div == 15))
532 continue;
533 }
534
535 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
536 uint32_t feedback_div, current_freq = 0, error, vco_diff;
537 uint32_t pll_in = pll->reference_freq / ref_div;
538 uint32_t min_feed_div = pll->min_feedback_div;
539 uint32_t max_feed_div = pll->max_feedback_div + 1;
540
541 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
542 continue;
543
544 while (min_feed_div < max_feed_div) {
545 uint32_t vco;
546 uint32_t min_frac_feed_div = min_fractional_feed_div;
547 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
548 uint32_t frac_feedback_div;
549 uint64_t tmp;
550
551 feedback_div = (min_feed_div + max_feed_div) / 2;
552
553 tmp = (uint64_t)pll->reference_freq * feedback_div;
554 vco = radeon_div(tmp, ref_div);
555
556 if (vco < pll_out_min) {
557 min_feed_div = feedback_div + 1;
558 continue;
559 } else if (vco > pll_out_max) {
560 max_feed_div = feedback_div;
561 continue;
562 }
563
564 while (min_frac_feed_div < max_frac_feed_div) {
565 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
566 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
567 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
568 current_freq = radeon_div(tmp, ref_div * post_div);
569
570 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
571 if (freq < current_freq)
572 error = 0xffffffff;
573 else
574 error = freq - current_freq;
575 } else
576 error = abs(current_freq - freq);
577 vco_diff = abs(vco - best_vco);
578
579 if ((best_vco == 0 && error < best_error) ||
580 (best_vco != 0 &&
581 ((best_error > 100 && error < best_error - 100) ||
582 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
583 best_post_div = post_div;
584 best_ref_div = ref_div;
585 best_feedback_div = feedback_div;
586 best_frac_feedback_div = frac_feedback_div;
587 best_freq = current_freq;
588 best_error = error;
589 best_vco_diff = vco_diff;
590 } else if (current_freq == freq) {
591 if (best_freq == -1) {
592 best_post_div = post_div;
593 best_ref_div = ref_div;
594 best_feedback_div = feedback_div;
595 best_frac_feedback_div = frac_feedback_div;
596 best_freq = current_freq;
597 best_error = error;
598 best_vco_diff = vco_diff;
599 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
600 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
601 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
602 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
603 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
604 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
605 best_post_div = post_div;
606 best_ref_div = ref_div;
607 best_feedback_div = feedback_div;
608 best_frac_feedback_div = frac_feedback_div;
609 best_freq = current_freq;
610 best_error = error;
611 best_vco_diff = vco_diff;
612 }
613 }
614 if (current_freq < freq)
615 min_frac_feed_div = frac_feedback_div + 1;
616 else
617 max_frac_feed_div = frac_feedback_div;
618 }
619 if (current_freq < freq)
620 min_feed_div = feedback_div + 1;
621 else
622 max_feed_div = feedback_div;
623 }
624 }
625 }
626
627 *dot_clock_p = best_freq / 10000;
628 *fb_div_p = best_feedback_div;
629 *frac_fb_div_p = best_frac_feedback_div;
630 *ref_div_p = best_ref_div;
631 *post_div_p = best_post_div;
632 }
633
634 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
635 {
636 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
637
638 if (radeon_fb->obj) {
639 drm_gem_object_unreference_unlocked(radeon_fb->obj);
640 }
641 drm_framebuffer_cleanup(fb);
642 kfree(radeon_fb);
643 }
644
645 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
646 struct drm_file *file_priv,
647 unsigned int *handle)
648 {
649 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
650
651 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
652 }
653
654 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
655 .destroy = radeon_user_framebuffer_destroy,
656 .create_handle = radeon_user_framebuffer_create_handle,
657 };
658
659 void
660 radeon_framebuffer_init(struct drm_device *dev,
661 struct radeon_framebuffer *rfb,
662 struct drm_mode_fb_cmd *mode_cmd,
663 struct drm_gem_object *obj)
664 {
665 rfb->obj = obj;
666 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
667 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
668 }
669
670 static struct drm_framebuffer *
671 radeon_user_framebuffer_create(struct drm_device *dev,
672 struct drm_file *file_priv,
673 struct drm_mode_fb_cmd *mode_cmd)
674 {
675 struct drm_gem_object *obj;
676 struct radeon_framebuffer *radeon_fb;
677
678 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
679 if (obj == NULL) {
680 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
681 "can't create framebuffer\n", mode_cmd->handle);
682 return ERR_PTR(-ENOENT);
683 }
684
685 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
686 if (radeon_fb == NULL)
687 return ERR_PTR(-ENOMEM);
688
689 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
690
691 return &radeon_fb->base;
692 }
693
694 static void radeon_output_poll_changed(struct drm_device *dev)
695 {
696 struct radeon_device *rdev = dev->dev_private;
697 radeon_fb_output_poll_changed(rdev);
698 }
699
700 static const struct drm_mode_config_funcs radeon_mode_funcs = {
701 .fb_create = radeon_user_framebuffer_create,
702 .output_poll_changed = radeon_output_poll_changed
703 };
704
705 struct drm_prop_enum_list {
706 int type;
707 char *name;
708 };
709
710 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
711 { { 0, "driver" },
712 { 1, "bios" },
713 };
714
715 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
716 { { TV_STD_NTSC, "ntsc" },
717 { TV_STD_PAL, "pal" },
718 { TV_STD_PAL_M, "pal-m" },
719 { TV_STD_PAL_60, "pal-60" },
720 { TV_STD_NTSC_J, "ntsc-j" },
721 { TV_STD_SCART_PAL, "scart-pal" },
722 { TV_STD_PAL_CN, "pal-cn" },
723 { TV_STD_SECAM, "secam" },
724 };
725
726 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
727 { { UNDERSCAN_OFF, "off" },
728 { UNDERSCAN_ON, "on" },
729 { UNDERSCAN_AUTO, "auto" },
730 };
731
732 static int radeon_modeset_create_props(struct radeon_device *rdev)
733 {
734 int i, sz;
735
736 if (rdev->is_atom_bios) {
737 rdev->mode_info.coherent_mode_property =
738 drm_property_create(rdev->ddev,
739 DRM_MODE_PROP_RANGE,
740 "coherent", 2);
741 if (!rdev->mode_info.coherent_mode_property)
742 return -ENOMEM;
743
744 rdev->mode_info.coherent_mode_property->values[0] = 0;
745 rdev->mode_info.coherent_mode_property->values[1] = 1;
746 }
747
748 if (!ASIC_IS_AVIVO(rdev)) {
749 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
750 rdev->mode_info.tmds_pll_property =
751 drm_property_create(rdev->ddev,
752 DRM_MODE_PROP_ENUM,
753 "tmds_pll", sz);
754 for (i = 0; i < sz; i++) {
755 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
756 i,
757 radeon_tmds_pll_enum_list[i].type,
758 radeon_tmds_pll_enum_list[i].name);
759 }
760 }
761
762 rdev->mode_info.load_detect_property =
763 drm_property_create(rdev->ddev,
764 DRM_MODE_PROP_RANGE,
765 "load detection", 2);
766 if (!rdev->mode_info.load_detect_property)
767 return -ENOMEM;
768 rdev->mode_info.load_detect_property->values[0] = 0;
769 rdev->mode_info.load_detect_property->values[1] = 1;
770
771 drm_mode_create_scaling_mode_property(rdev->ddev);
772
773 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
774 rdev->mode_info.tv_std_property =
775 drm_property_create(rdev->ddev,
776 DRM_MODE_PROP_ENUM,
777 "tv standard", sz);
778 for (i = 0; i < sz; i++) {
779 drm_property_add_enum(rdev->mode_info.tv_std_property,
780 i,
781 radeon_tv_std_enum_list[i].type,
782 radeon_tv_std_enum_list[i].name);
783 }
784
785 sz = ARRAY_SIZE(radeon_underscan_enum_list);
786 rdev->mode_info.underscan_property =
787 drm_property_create(rdev->ddev,
788 DRM_MODE_PROP_ENUM,
789 "underscan", sz);
790 for (i = 0; i < sz; i++) {
791 drm_property_add_enum(rdev->mode_info.underscan_property,
792 i,
793 radeon_underscan_enum_list[i].type,
794 radeon_underscan_enum_list[i].name);
795 }
796
797 rdev->mode_info.underscan_hborder_property =
798 drm_property_create(rdev->ddev,
799 DRM_MODE_PROP_RANGE,
800 "underscan hborder", 2);
801 if (!rdev->mode_info.underscan_hborder_property)
802 return -ENOMEM;
803 rdev->mode_info.underscan_hborder_property->values[0] = 0;
804 rdev->mode_info.underscan_hborder_property->values[1] = 128;
805
806 rdev->mode_info.underscan_vborder_property =
807 drm_property_create(rdev->ddev,
808 DRM_MODE_PROP_RANGE,
809 "underscan vborder", 2);
810 if (!rdev->mode_info.underscan_vborder_property)
811 return -ENOMEM;
812 rdev->mode_info.underscan_vborder_property->values[0] = 0;
813 rdev->mode_info.underscan_vborder_property->values[1] = 128;
814
815 return 0;
816 }
817
818 void radeon_update_display_priority(struct radeon_device *rdev)
819 {
820 /* adjustment options for the display watermarks */
821 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
822 /* set display priority to high for r3xx, rv515 chips
823 * this avoids flickering due to underflow to the
824 * display controllers during heavy acceleration.
825 * Don't force high on rs4xx igp chips as it seems to
826 * affect the sound card. See kernel bug 15982.
827 */
828 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
829 !(rdev->flags & RADEON_IS_IGP))
830 rdev->disp_priority = 2;
831 else
832 rdev->disp_priority = 0;
833 } else
834 rdev->disp_priority = radeon_disp_priority;
835
836 }
837
838 int radeon_modeset_init(struct radeon_device *rdev)
839 {
840 int i;
841 int ret;
842
843 drm_mode_config_init(rdev->ddev);
844 rdev->mode_info.mode_config_initialized = true;
845
846 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
847
848 if (ASIC_IS_AVIVO(rdev)) {
849 rdev->ddev->mode_config.max_width = 8192;
850 rdev->ddev->mode_config.max_height = 8192;
851 } else {
852 rdev->ddev->mode_config.max_width = 4096;
853 rdev->ddev->mode_config.max_height = 4096;
854 }
855
856 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
857
858 ret = radeon_modeset_create_props(rdev);
859 if (ret) {
860 return ret;
861 }
862
863 /* init i2c buses */
864 radeon_i2c_init(rdev);
865
866 /* check combios for a valid hardcoded EDID - Sun servers */
867 if (!rdev->is_atom_bios) {
868 /* check for hardcoded EDID in BIOS */
869 radeon_combios_check_hardcoded_edid(rdev);
870 }
871
872 /* allocate crtcs */
873 for (i = 0; i < rdev->num_crtc; i++) {
874 radeon_crtc_init(rdev->ddev, i);
875 }
876
877 /* okay we should have all the bios connectors */
878 ret = radeon_setup_enc_conn(rdev->ddev);
879 if (!ret) {
880 return ret;
881 }
882 /* initialize hpd */
883 radeon_hpd_init(rdev);
884
885 /* Initialize power management */
886 radeon_pm_init(rdev);
887
888 radeon_fbdev_init(rdev);
889 drm_kms_helper_poll_init(rdev->ddev);
890
891 return 0;
892 }
893
894 void radeon_modeset_fini(struct radeon_device *rdev)
895 {
896 radeon_fbdev_fini(rdev);
897 kfree(rdev->mode_info.bios_hardcoded_edid);
898 radeon_pm_fini(rdev);
899
900 if (rdev->mode_info.mode_config_initialized) {
901 drm_kms_helper_poll_fini(rdev->ddev);
902 radeon_hpd_fini(rdev);
903 drm_mode_config_cleanup(rdev->ddev);
904 rdev->mode_info.mode_config_initialized = false;
905 }
906 /* free i2c buses */
907 radeon_i2c_fini(rdev);
908 }
909
910 static bool is_hdtv_mode(struct drm_display_mode *mode)
911 {
912 /* try and guess if this is a tv or a monitor */
913 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
914 (mode->vdisplay == 576) || /* 576p */
915 (mode->vdisplay == 720) || /* 720p */
916 (mode->vdisplay == 1080)) /* 1080p */
917 return true;
918 else
919 return false;
920 }
921
922 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
923 struct drm_display_mode *mode,
924 struct drm_display_mode *adjusted_mode)
925 {
926 struct drm_device *dev = crtc->dev;
927 struct radeon_device *rdev = dev->dev_private;
928 struct drm_encoder *encoder;
929 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
930 struct radeon_encoder *radeon_encoder;
931 struct drm_connector *connector;
932 struct radeon_connector *radeon_connector;
933 bool first = true;
934 u32 src_v = 1, dst_v = 1;
935 u32 src_h = 1, dst_h = 1;
936
937 radeon_crtc->h_border = 0;
938 radeon_crtc->v_border = 0;
939
940 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
941 if (encoder->crtc != crtc)
942 continue;
943 radeon_encoder = to_radeon_encoder(encoder);
944 connector = radeon_get_connector_for_encoder(encoder);
945 radeon_connector = to_radeon_connector(connector);
946
947 if (first) {
948 /* set scaling */
949 if (radeon_encoder->rmx_type == RMX_OFF)
950 radeon_crtc->rmx_type = RMX_OFF;
951 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
952 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
953 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
954 else
955 radeon_crtc->rmx_type = RMX_OFF;
956 /* copy native mode */
957 memcpy(&radeon_crtc->native_mode,
958 &radeon_encoder->native_mode,
959 sizeof(struct drm_display_mode));
960 src_v = crtc->mode.vdisplay;
961 dst_v = radeon_crtc->native_mode.vdisplay;
962 src_h = crtc->mode.hdisplay;
963 dst_h = radeon_crtc->native_mode.hdisplay;
964
965 /* fix up for overscan on hdmi */
966 if (ASIC_IS_AVIVO(rdev) &&
967 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
968 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
969 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
970 drm_detect_hdmi_monitor(radeon_connector->edid) &&
971 is_hdtv_mode(mode)))) {
972 if (radeon_encoder->underscan_hborder != 0)
973 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
974 else
975 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
976 if (radeon_encoder->underscan_vborder != 0)
977 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
978 else
979 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
980 radeon_crtc->rmx_type = RMX_FULL;
981 src_v = crtc->mode.vdisplay;
982 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
983 src_h = crtc->mode.hdisplay;
984 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
985 }
986 first = false;
987 } else {
988 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
989 /* WARNING: Right now this can't happen but
990 * in the future we need to check that scaling
991 * are consistent across different encoder
992 * (ie all encoder can work with the same
993 * scaling).
994 */
995 DRM_ERROR("Scaling not consistent across encoder.\n");
996 return false;
997 }
998 }
999 }
1000 if (radeon_crtc->rmx_type != RMX_OFF) {
1001 fixed20_12 a, b;
1002 a.full = dfixed_const(src_v);
1003 b.full = dfixed_const(dst_v);
1004 radeon_crtc->vsc.full = dfixed_div(a, b);
1005 a.full = dfixed_const(src_h);
1006 b.full = dfixed_const(dst_h);
1007 radeon_crtc->hsc.full = dfixed_div(a, b);
1008 } else {
1009 radeon_crtc->vsc.full = dfixed_const(1);
1010 radeon_crtc->hsc.full = dfixed_const(1);
1011 }
1012 return true;
1013 }
1014
1015 /*
1016 * Retrieve current video scanout position of crtc on a given gpu.
1017 *
1018 * \param rdev Device to query.
1019 * \param crtc Crtc to query.
1020 * \param *vpos Location where vertical scanout position should be stored.
1021 * \param *hpos Location where horizontal scanout position should go.
1022 *
1023 * Returns vpos as a positive number while in active scanout area.
1024 * Returns vpos as a negative number inside vblank, counting the number
1025 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1026 * until start of active scanout / end of vblank."
1027 *
1028 * \return Flags, or'ed together as follows:
1029 *
1030 * RADEON_SCANOUTPOS_VALID = Query successfull.
1031 * RADEON_SCANOUTPOS_INVBL = Inside vblank.
1032 * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1033 * this flag means that returned position may be offset by a constant but
1034 * unknown small number of scanlines wrt. real scanout position.
1035 *
1036 */
1037 int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos)
1038 {
1039 u32 stat_crtc = 0, vbl = 0, position = 0;
1040 int vbl_start, vbl_end, vtotal, ret = 0;
1041 bool in_vbl = true;
1042
1043 if (ASIC_IS_DCE4(rdev)) {
1044 if (crtc == 0) {
1045 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1046 EVERGREEN_CRTC0_REGISTER_OFFSET);
1047 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1048 EVERGREEN_CRTC0_REGISTER_OFFSET);
1049 ret |= RADEON_SCANOUTPOS_VALID;
1050 }
1051 if (crtc == 1) {
1052 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1053 EVERGREEN_CRTC1_REGISTER_OFFSET);
1054 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1055 EVERGREEN_CRTC1_REGISTER_OFFSET);
1056 ret |= RADEON_SCANOUTPOS_VALID;
1057 }
1058 if (crtc == 2) {
1059 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1060 EVERGREEN_CRTC2_REGISTER_OFFSET);
1061 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1062 EVERGREEN_CRTC2_REGISTER_OFFSET);
1063 ret |= RADEON_SCANOUTPOS_VALID;
1064 }
1065 if (crtc == 3) {
1066 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1067 EVERGREEN_CRTC3_REGISTER_OFFSET);
1068 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1069 EVERGREEN_CRTC3_REGISTER_OFFSET);
1070 ret |= RADEON_SCANOUTPOS_VALID;
1071 }
1072 if (crtc == 4) {
1073 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1074 EVERGREEN_CRTC4_REGISTER_OFFSET);
1075 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1076 EVERGREEN_CRTC4_REGISTER_OFFSET);
1077 ret |= RADEON_SCANOUTPOS_VALID;
1078 }
1079 if (crtc == 5) {
1080 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1081 EVERGREEN_CRTC5_REGISTER_OFFSET);
1082 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1083 EVERGREEN_CRTC5_REGISTER_OFFSET);
1084 ret |= RADEON_SCANOUTPOS_VALID;
1085 }
1086 } else if (ASIC_IS_AVIVO(rdev)) {
1087 if (crtc == 0) {
1088 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1089 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1090 ret |= RADEON_SCANOUTPOS_VALID;
1091 }
1092 if (crtc == 1) {
1093 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1094 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1095 ret |= RADEON_SCANOUTPOS_VALID;
1096 }
1097 } else {
1098 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1099 if (crtc == 0) {
1100 /* Assume vbl_end == 0, get vbl_start from
1101 * upper 16 bits.
1102 */
1103 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1104 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1105 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1106 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1107 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1108 if (!(stat_crtc & 1))
1109 in_vbl = false;
1110
1111 ret |= RADEON_SCANOUTPOS_VALID;
1112 }
1113 if (crtc == 1) {
1114 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1115 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1116 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1117 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1118 if (!(stat_crtc & 1))
1119 in_vbl = false;
1120
1121 ret |= RADEON_SCANOUTPOS_VALID;
1122 }
1123 }
1124
1125 /* Decode into vertical and horizontal scanout position. */
1126 *vpos = position & 0x1fff;
1127 *hpos = (position >> 16) & 0x1fff;
1128
1129 /* Valid vblank area boundaries from gpu retrieved? */
1130 if (vbl > 0) {
1131 /* Yes: Decode. */
1132 ret |= RADEON_SCANOUTPOS_ACCURATE;
1133 vbl_start = vbl & 0x1fff;
1134 vbl_end = (vbl >> 16) & 0x1fff;
1135 }
1136 else {
1137 /* No: Fake something reasonable which gives at least ok results. */
1138 vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay;
1139 vbl_end = 0;
1140 }
1141
1142 /* Test scanout position against vblank region. */
1143 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1144 in_vbl = false;
1145
1146 /* Check if inside vblank area and apply corrective offsets:
1147 * vpos will then be >=0 in video scanout area, but negative
1148 * within vblank area, counting down the number of lines until
1149 * start of scanout.
1150 */
1151
1152 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1153 if (in_vbl && (*vpos >= vbl_start)) {
1154 vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal;
1155 *vpos = *vpos - vtotal;
1156 }
1157
1158 /* Correct for shifted end of vbl at vbl_end. */
1159 *vpos = *vpos - vbl_end;
1160
1161 /* In vblank? */
1162 if (in_vbl)
1163 ret |= RADEON_SCANOUTPOS_INVBL;
1164
1165 return ret;
1166 }
Linux with added FPC-III support