drivers/spi/spi-fsl-cpm.c

   1 /*
   2  * Freescale SPI controller driver cpm functions.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #include <asm/cpm.h>
  19 #include <asm/qe.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/fsl_devices.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/types.h>
  27
  28 #include "spi-fsl-cpm.h"
  29 #include "spi-fsl-lib.h"
  30 #include "spi-fsl-spi.h"
  31
  32 /* CPM1 and CPM2 are mutually exclusive. */
  33 #ifdef CONFIG_CPM1
  34 #include <asm/cpm1.h>
  35 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
  36 #else
  37 #include <asm/cpm2.h>
  38 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
  39 #endif
  40
  41 #define SPIE_TXB        0x00000200      /* Last char is written to tx fifo */
  42 #define SPIE_RXB        0x00000100      /* Last char is written to rx buf */
  43
  44 /* SPCOM register values */
  45 #define SPCOM_STR       (1 << 23)       /* Start transmit */
  46
  47 #define SPI_PRAM_SIZE   0x100
  48 #define SPI_MRBLR       ((unsigned int)PAGE_SIZE)
  49
  50 static void *fsl_dummy_rx;
  51 static DEFINE_MUTEX(fsl_dummy_rx_lock);
  52 static int fsl_dummy_rx_refcnt;
  53
  54 void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi)
  55 {
  56         if (mspi->flags & SPI_QE) {
  57                 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
  58                              QE_CR_PROTOCOL_UNSPECIFIED, 0);
  59         } else {
  60                 if (mspi->flags & SPI_CPM1) {
  61                         out_be32(&mspi->pram->rstate, 0);
  62                         out_be16(&mspi->pram->rbptr,
  63                                  in_be16(&mspi->pram->rbase));
  64                         out_be32(&mspi->pram->tstate, 0);
  65                         out_be16(&mspi->pram->tbptr,
  66                                  in_be16(&mspi->pram->tbase));
  67                 } else {
  68                         cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
  69                 }
  70         }
  71 }
  72 EXPORT_SYMBOL_GPL(fsl_spi_cpm_reinit_txrx);
  73
  74 static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
  75 {
  76         struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
  77         struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
  78         unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
  79         unsigned int xfer_ofs;
  80         struct fsl_spi_reg *reg_base = mspi->reg_base;
  81
  82         xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
  83
  84         if (mspi->rx_dma == mspi->dma_dummy_rx)
  85                 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma);
  86         else
  87                 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
  88         out_be16(&rx_bd->cbd_datlen, 0);
  89         out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
  90
  91         if (mspi->tx_dma == mspi->dma_dummy_tx)
  92                 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma);
  93         else
  94                 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
  95         out_be16(&tx_bd->cbd_datlen, xfer_len);
  96         out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
  97                                  BD_SC_LAST);
  98
  99         /* start transfer */
 100         mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR);
 101 }
 102
 103 int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
 104                      struct spi_transfer *t, bool is_dma_mapped)
 105 {
 106         struct device *dev = mspi->dev;
 107         struct fsl_spi_reg *reg_base = mspi->reg_base;
 108
 109         if (is_dma_mapped) {
 110                 mspi->map_tx_dma = 0;
 111                 mspi->map_rx_dma = 0;
 112         } else {
 113                 mspi->map_tx_dma = 1;
 114                 mspi->map_rx_dma = 1;
 115         }
 116
 117         if (!t->tx_buf) {
 118                 mspi->tx_dma = mspi->dma_dummy_tx;
 119                 mspi->map_tx_dma = 0;
 120         }
 121
 122         if (!t->rx_buf) {
 123                 mspi->rx_dma = mspi->dma_dummy_rx;
 124                 mspi->map_rx_dma = 0;
 125         }
 126
 127         if (mspi->map_tx_dma) {
 128                 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
 129
 130                 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
 131                                               DMA_TO_DEVICE);
 132                 if (dma_mapping_error(dev, mspi->tx_dma)) {
 133                         dev_err(dev, "unable to map tx dma\n");
 134                         return -ENOMEM;
 135                 }
 136         } else if (t->tx_buf) {
 137                 mspi->tx_dma = t->tx_dma;
 138         }
 139
 140         if (mspi->map_rx_dma) {
 141                 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
 142                                               DMA_FROM_DEVICE);
 143                 if (dma_mapping_error(dev, mspi->rx_dma)) {
 144                         dev_err(dev, "unable to map rx dma\n");
 145                         goto err_rx_dma;
 146                 }
 147         } else if (t->rx_buf) {
 148                 mspi->rx_dma = t->rx_dma;
 149         }
 150
 151         /* enable rx ints */
 152         mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB);
 153
 154         mspi->xfer_in_progress = t;
 155         mspi->count = t->len;
 156
 157         /* start CPM transfers */
 158         fsl_spi_cpm_bufs_start(mspi);
 159
 160         return 0;
 161
 162 err_rx_dma:
 163         if (mspi->map_tx_dma)
 164                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
 165         return -ENOMEM;
 166 }
 167 EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs);
 168
 169 void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
 170 {
 171         struct device *dev = mspi->dev;
 172         struct spi_transfer *t = mspi->xfer_in_progress;
 173
 174         if (mspi->map_tx_dma)
 175                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
 176         if (mspi->map_rx_dma)
 177                 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
 178         mspi->xfer_in_progress = NULL;
 179 }
 180 EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete);
 181
 182 void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
 183 {
 184         u16 len;
 185         struct fsl_spi_reg *reg_base = mspi->reg_base;
 186
 187         dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
 188                 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
 189
 190         len = in_be16(&mspi->rx_bd->cbd_datlen);
 191         if (len > mspi->count) {
 192                 WARN_ON(1);
 193                 len = mspi->count;
 194         }
 195
 196         /* Clear the events */
 197         mpc8xxx_spi_write_reg(&reg_base->event, events);
 198
 199         mspi->count -= len;
 200         if (mspi->count)
 201                 fsl_spi_cpm_bufs_start(mspi);
 202         else
 203                 complete(&mspi->done);
 204 }
 205 EXPORT_SYMBOL_GPL(fsl_spi_cpm_irq);
 206
 207 static void *fsl_spi_alloc_dummy_rx(void)
 208 {
 209         mutex_lock(&fsl_dummy_rx_lock);
 210
 211         if (!fsl_dummy_rx)
 212                 fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
 213         if (fsl_dummy_rx)
 214                 fsl_dummy_rx_refcnt++;
 215
 216         mutex_unlock(&fsl_dummy_rx_lock);
 217
 218         return fsl_dummy_rx;
 219 }
 220
 221 static void fsl_spi_free_dummy_rx(void)
 222 {
 223         mutex_lock(&fsl_dummy_rx_lock);
 224
 225         switch (fsl_dummy_rx_refcnt) {
 226         case 0:
 227                 WARN_ON(1);
 228                 break;
 229         case 1:
 230                 kfree(fsl_dummy_rx);
 231                 fsl_dummy_rx = NULL;
 232                 /* fall through */
 233         default:
 234                 fsl_dummy_rx_refcnt--;
 235                 break;
 236         }
 237
 238         mutex_unlock(&fsl_dummy_rx_lock);
 239 }
 240
 241 static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
 242 {
 243         struct device *dev = mspi->dev;
 244         struct device_node *np = dev->of_node;
 245         const u32 *iprop;
 246         int size;
 247         void __iomem *spi_base;
 248         unsigned long pram_ofs = -ENOMEM;
 249
 250         /* Can't use of_address_to_resource(), QE muram isn't at 0. */
 251         iprop = of_get_property(np, "reg", &size);
 252
 253         /* QE with a fixed pram location? */
 254         if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
 255                 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
 256
 257         /* QE but with a dynamic pram location? */
 258         if (mspi->flags & SPI_QE) {
 259                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
 260                 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
 261                              QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
 262                 return pram_ofs;
 263         }
 264
 265         spi_base = of_iomap(np, 1);
 266         if (spi_base == NULL)
 267                 return -EINVAL;
 268
 269         if (mspi->flags & SPI_CPM2) {
 270                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
 271                 out_be16(spi_base, pram_ofs);
 272         } else {
 273                 struct spi_pram __iomem *pram = spi_base;
 274                 u16 rpbase = in_be16(&pram->rpbase);
 275
 276                 /* Microcode relocation patch applied? */
 277                 if (rpbase) {
 278                         pram_ofs = rpbase;
 279                 } else {
 280                         pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
 281                         out_be16(spi_base, pram_ofs);
 282                 }
 283         }
 284
 285         iounmap(spi_base);
 286         return pram_ofs;
 287 }
 288
 289 int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
 290 {
 291         struct device *dev = mspi->dev;
 292         struct device_node *np = dev->of_node;
 293         const u32 *iprop;
 294         int size;
 295         unsigned long pram_ofs;
 296         unsigned long bds_ofs;
 297
 298         if (!(mspi->flags & SPI_CPM_MODE))
 299                 return 0;
 300
 301         if (!fsl_spi_alloc_dummy_rx())
 302                 return -ENOMEM;
 303
 304         if (mspi->flags & SPI_QE) {
 305                 iprop = of_get_property(np, "cell-index", &size);
 306                 if (iprop && size == sizeof(*iprop))
 307                         mspi->subblock = *iprop;
 308
 309                 switch (mspi->subblock) {
 310                 default:
 311                         dev_warn(dev, "cell-index unspecified, assuming SPI1\n");
 312                         /* fall through */
 313                 case 0:
 314                         mspi->subblock = QE_CR_SUBBLOCK_SPI1;
 315                         break;
 316                 case 1:
 317                         mspi->subblock = QE_CR_SUBBLOCK_SPI2;
 318                         break;
 319                 }
 320         }
 321
 322         pram_ofs = fsl_spi_cpm_get_pram(mspi);
 323         if (IS_ERR_VALUE(pram_ofs)) {
 324                 dev_err(dev, "can't allocate spi parameter ram\n");
 325                 goto err_pram;
 326         }
 327
 328         bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
 329                                   sizeof(*mspi->rx_bd), 8);
 330         if (IS_ERR_VALUE(bds_ofs)) {
 331                 dev_err(dev, "can't allocate bds\n");
 332                 goto err_bds;
 333         }
 334
 335         mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
 336                                             DMA_TO_DEVICE);
 337         if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
 338                 dev_err(dev, "unable to map dummy tx buffer\n");
 339                 goto err_dummy_tx;
 340         }
 341
 342         mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
 343                                             DMA_FROM_DEVICE);
 344         if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
 345                 dev_err(dev, "unable to map dummy rx buffer\n");
 346                 goto err_dummy_rx;
 347         }
 348
 349         mspi->pram = cpm_muram_addr(pram_ofs);
 350
 351         mspi->tx_bd = cpm_muram_addr(bds_ofs);
 352         mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
 353
 354         /* Initialize parameter ram. */
 355         out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
 356         out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
 357         out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
 358         out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
 359         out_be16(&mspi->pram->mrblr, SPI_MRBLR);
 360         out_be32(&mspi->pram->rstate, 0);
 361         out_be32(&mspi->pram->rdp, 0);
 362         out_be16(&mspi->pram->rbptr, 0);
 363         out_be16(&mspi->pram->rbc, 0);
 364         out_be32(&mspi->pram->rxtmp, 0);
 365         out_be32(&mspi->pram->tstate, 0);
 366         out_be32(&mspi->pram->tdp, 0);
 367         out_be16(&mspi->pram->tbptr, 0);
 368         out_be16(&mspi->pram->tbc, 0);
 369         out_be32(&mspi->pram->txtmp, 0);
 370
 371         return 0;
 372
 373 err_dummy_rx:
 374         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
 375 err_dummy_tx:
 376         cpm_muram_free(bds_ofs);
 377 err_bds:
 378         cpm_muram_free(pram_ofs);
 379 err_pram:
 380         fsl_spi_free_dummy_rx();
 381         return -ENOMEM;
 382 }
 383 EXPORT_SYMBOL_GPL(fsl_spi_cpm_init);
 384
 385 void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
 386 {
 387         struct device *dev = mspi->dev;
 388
 389         if (!(mspi->flags & SPI_CPM_MODE))
 390                 return;
 391
 392         dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
 393         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
 394         cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
 395         cpm_muram_free(cpm_muram_offset(mspi->pram));
 396         fsl_spi_free_dummy_rx();
 397 }
 398 EXPORT_SYMBOL_GPL(fsl_spi_cpm_free);
 399
 400 MODULE_LICENSE("GPL");