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floppy: make controller const
[linux/fpc-iii.git] / drivers / char / agp / amd64-agp.c
blob70312da4c968f9e4af7c39e9a5a649b4952f8bd3
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
17 #include <asm/e820.h>
18 #include <asm/k8.h>
19 #include <asm/gart.h>
20 #include "agp.h"
21
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
29
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
34
35 static struct resource *aperture_resource;
36 static int __initdata agp_try_unsupported = 1;
37 static int agp_bridges_found;
38
39 static void amd64_tlbflush(struct agp_memory *temp)
40 {
41 k8_flush_garts();
42 }
43
44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
45 {
46 int i, j, num_entries;
47 long long tmp;
48 int mask_type;
49 struct agp_bridge_data *bridge = mem->bridge;
50 u32 pte;
51
52 num_entries = agp_num_entries();
53
54 if (type != mem->type)
55 return -EINVAL;
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
57 if (mask_type != 0)
58 return -EINVAL;
59
60
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
64 return -EINVAL;
65
66 j = pg_start;
67
68 /* gatt table should be empty. */
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
71 return -EBUSY;
72 j++;
73 }
74
75 if (!mem->is_flushed) {
76 global_cache_flush();
77 mem->is_flushed = true;
78 }
79
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 page_to_phys(mem->pages[i]),
83 mask_type);
84
85 BUG_ON(tmp & 0xffffff0000000ffcULL);
86 pte = (tmp & 0x000000ff00000000ULL) >> 28;
87 pte |=(tmp & 0x00000000fffff000ULL);
88 pte |= GPTE_VALID | GPTE_COHERENT;
89
90 writel(pte, agp_bridge->gatt_table+j);
91 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
92 }
93 amd64_tlbflush(mem);
94 return 0;
95 }
96
97 /*
98 * This hack alters the order element according
99 * to the size of a long. It sucks. I totally disown this, even
100 * though it does appear to work for the most part.
101 */
102 static struct aper_size_info_32 amd64_aperture_sizes[7] =
103 {
104 {32, 8192, 3+(sizeof(long)/8), 0 },
105 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
106 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
107 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
108 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
109 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
110 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
111 };
112
113
114 /*
115 * Get the current Aperture size from the x86-64.
116 * Note, that there may be multiple x86-64's, but we just return
117 * the value from the first one we find. The set_size functions
118 * keep the rest coherent anyway. Or at least should do.
119 */
120 static int amd64_fetch_size(void)
121 {
122 struct pci_dev *dev;
123 int i;
124 u32 temp;
125 struct aper_size_info_32 *values;
126
127 dev = k8_northbridges[0];
128 if (dev==NULL)
129 return 0;
130
131 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
132 temp = (temp & 0xe);
133 values = A_SIZE_32(amd64_aperture_sizes);
134
135 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
136 if (temp == values[i].size_value) {
137 agp_bridge->previous_size =
138 agp_bridge->current_size = (void *) (values + i);
139
140 agp_bridge->aperture_size_idx = i;
141 return values[i].size;
142 }
143 }
144 return 0;
145 }
146
147 /*
148 * In a multiprocessor x86-64 system, this function gets
149 * called once for each CPU.
150 */
151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
152 {
153 u64 aperturebase;
154 u32 tmp;
155 u64 aper_base;
156
157 /* Address to map to */
158 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
159 aperturebase = tmp << 25;
160 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
161
162 enable_gart_translation(hammer, gatt_table);
163
164 return aper_base;
165 }
166
167
168 static const struct aper_size_info_32 amd_8151_sizes[7] =
169 {
170 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
171 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
172 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
173 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
174 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
175 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
176 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
177 };
178
179 static int amd_8151_configure(void)
180 {
181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
182 int i;
183
184 /* Configure AGP regs in each x86-64 host bridge. */
185 for (i = 0; i < num_k8_northbridges; i++) {
186 agp_bridge->gart_bus_addr =
187 amd64_configure(k8_northbridges[i], gatt_bus);
188 }
189 k8_flush_garts();
190 return 0;
191 }
192
193
194 static void amd64_cleanup(void)
195 {
196 u32 tmp;
197 int i;
198 for (i = 0; i < num_k8_northbridges; i++) {
199 struct pci_dev *dev = k8_northbridges[i];
200 /* disable gart translation */
201 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
202 tmp &= ~AMD64_GARTEN;
203 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
204 }
205 }
206
207
208 static const struct agp_bridge_driver amd_8151_driver = {
209 .owner = THIS_MODULE,
210 .aperture_sizes = amd_8151_sizes,
211 .size_type = U32_APER_SIZE,
212 .num_aperture_sizes = 7,
213 .needs_scratch_page = true,
214 .configure = amd_8151_configure,
215 .fetch_size = amd64_fetch_size,
216 .cleanup = amd64_cleanup,
217 .tlb_flush = amd64_tlbflush,
218 .mask_memory = agp_generic_mask_memory,
219 .masks = NULL,
220 .agp_enable = agp_generic_enable,
221 .cache_flush = global_cache_flush,
222 .create_gatt_table = agp_generic_create_gatt_table,
223 .free_gatt_table = agp_generic_free_gatt_table,
224 .insert_memory = amd64_insert_memory,
225 .remove_memory = agp_generic_remove_memory,
226 .alloc_by_type = agp_generic_alloc_by_type,
227 .free_by_type = agp_generic_free_by_type,
228 .agp_alloc_page = agp_generic_alloc_page,
229 .agp_alloc_pages = agp_generic_alloc_pages,
230 .agp_destroy_page = agp_generic_destroy_page,
231 .agp_destroy_pages = agp_generic_destroy_pages,
232 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
233 };
234
235 /* Some basic sanity checks for the aperture. */
236 static int __devinit agp_aperture_valid(u64 aper, u32 size)
237 {
238 if (!aperture_valid(aper, size, 32*1024*1024))
239 return 0;
240
241 /* Request the Aperture. This catches cases when someone else
242 already put a mapping in there - happens with some very broken BIOS
243
244 Maybe better to use pci_assign_resource/pci_enable_device instead
245 trusting the bridges? */
246 if (!aperture_resource &&
247 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
248 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
249 return 0;
250 }
251 return 1;
252 }
253
254 /*
255 * W*s centric BIOS sometimes only set up the aperture in the AGP
256 * bridge, not the northbridge. On AMD64 this is handled early
257 * in aperture.c, but when IOMMU is not enabled or we run
258 * on a 32bit kernel this needs to be redone.
259 * Unfortunately it is impossible to fix the aperture here because it's too late
260 * to allocate that much memory. But at least error out cleanly instead of
261 * crashing.
262 */
263 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
264 u16 cap)
265 {
266 u32 aper_low, aper_hi;
267 u64 aper, nb_aper;
268 int order = 0;
269 u32 nb_order, nb_base;
270 u16 apsize;
271
272 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
273 nb_order = (nb_order >> 1) & 7;
274 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
275 nb_aper = nb_base << 25;
276
277 /* Northbridge seems to contain crap. Try the AGP bridge. */
278
279 pci_read_config_word(agp, cap+0x14, &apsize);
280 if (apsize == 0xffff) {
281 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
282 return 0;
283 return -1;
284 }
285
286 apsize &= 0xfff;
287 /* Some BIOS use weird encodings not in the AGPv3 table. */
288 if (apsize & 0xff)
289 apsize |= 0xf00;
290 order = 7 - hweight16(apsize);
291
292 pci_read_config_dword(agp, 0x10, &aper_low);
293 pci_read_config_dword(agp, 0x14, &aper_hi);
294 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
295
296 /*
297 * On some sick chips APSIZE is 0. This means it wants 4G
298 * so let double check that order, and lets trust the AMD NB settings
299 */
300 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
301 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
302 32 << order);
303 order = nb_order;
304 }
305
306 if (nb_order >= order) {
307 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
308 return 0;
309 }
310
311 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
312 aper, 32 << order);
313 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
314 return -1;
315
316 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
317 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
318
319 return 0;
320 }
321
322 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
323 {
324 int i;
325
326 if (cache_k8_northbridges() < 0)
327 return -ENODEV;
328
329 i = 0;
330 for (i = 0; i < num_k8_northbridges; i++) {
331 struct pci_dev *dev = k8_northbridges[i];
332 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
333 dev_err(&dev->dev, "no usable aperture found\n");
334 #ifdef __x86_64__
335 /* should port this to i386 */
336 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
337 #endif
338 return -1;
339 }
340 }
341 return 0;
342 }
343
344 /* Handle AMD 8151 quirks */
345 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
346 {
347 char *revstring;
348
349 switch (pdev->revision) {
350 case 0x01: revstring="A0"; break;
351 case 0x02: revstring="A1"; break;
352 case 0x11: revstring="B0"; break;
353 case 0x12: revstring="B1"; break;
354 case 0x13: revstring="B2"; break;
355 case 0x14: revstring="B3"; break;
356 default: revstring="??"; break;
357 }
358
359 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
360
361 /*
362 * Work around errata.
363 * Chips before B2 stepping incorrectly reporting v3.5
364 */
365 if (pdev->revision < 0x13) {
366 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
367 bridge->major_version = 3;
368 bridge->minor_version = 0;
369 }
370 }
371
372
373 static const struct aper_size_info_32 uli_sizes[7] =
374 {
375 {256, 65536, 6, 10},
376 {128, 32768, 5, 9},
377 {64, 16384, 4, 8},
378 {32, 8192, 3, 7},
379 {16, 4096, 2, 6},
380 {8, 2048, 1, 4},
381 {4, 1024, 0, 3}
382 };
383 static int __devinit uli_agp_init(struct pci_dev *pdev)
384 {
385 u32 httfea,baseaddr,enuscr;
386 struct pci_dev *dev1;
387 int i, ret;
388 unsigned size = amd64_fetch_size();
389
390 dev_info(&pdev->dev, "setting up ULi AGP\n");
391 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
392 if (dev1 == NULL) {
393 dev_info(&pdev->dev, "can't find ULi secondary device\n");
394 return -ENODEV;
395 }
396
397 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
398 if (uli_sizes[i].size == size)
399 break;
400
401 if (i == ARRAY_SIZE(uli_sizes)) {
402 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
403 ret = -ENODEV;
404 goto put;
405 }
406
407 /* shadow x86-64 registers into ULi registers */
408 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
409
410 /* if x86-64 aperture base is beyond 4G, exit here */
411 if ((httfea & 0x7fff) >> (32 - 25)) {
412 ret = -ENODEV;
413 goto put;
414 }
415
416 httfea = (httfea& 0x7fff) << 25;
417
418 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
419 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
420 baseaddr|= httfea;
421 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
422
423 enuscr= httfea+ (size * 1024 * 1024) - 1;
424 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
425 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
426 ret = 0;
427 put:
428 pci_dev_put(dev1);
429 return ret;
430 }
431
432
433 static const struct aper_size_info_32 nforce3_sizes[5] =
434 {
435 {512, 131072, 7, 0x00000000 },
436 {256, 65536, 6, 0x00000008 },
437 {128, 32768, 5, 0x0000000C },
438 {64, 16384, 4, 0x0000000E },
439 {32, 8192, 3, 0x0000000F }
440 };
441
442 /* Handle shadow device of the Nvidia NForce3 */
443 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
444 static int nforce3_agp_init(struct pci_dev *pdev)
445 {
446 u32 tmp, apbase, apbar, aplimit;
447 struct pci_dev *dev1;
448 int i, ret;
449 unsigned size = amd64_fetch_size();
450
451 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
452
453 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
454 if (dev1 == NULL) {
455 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
456 return -ENODEV;
457 }
458
459 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
460 if (nforce3_sizes[i].size == size)
461 break;
462
463 if (i == ARRAY_SIZE(nforce3_sizes)) {
464 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
465 ret = -ENODEV;
466 goto put;
467 }
468
469 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
470 tmp &= ~(0xf);
471 tmp |= nforce3_sizes[i].size_value;
472 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
473
474 /* shadow x86-64 registers into NVIDIA registers */
475 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
476
477 /* if x86-64 aperture base is beyond 4G, exit here */
478 if ( (apbase & 0x7fff) >> (32 - 25) ) {
479 dev_info(&pdev->dev, "aperture base > 4G\n");
480 ret = -ENODEV;
481 goto put;
482 }
483
484 apbase = (apbase & 0x7fff) << 25;
485
486 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
487 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
488 apbar |= apbase;
489 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
490
491 aplimit = apbase + (size * 1024 * 1024) - 1;
492 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
493 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
494 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
495 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
496
497 ret = 0;
498 put:
499 pci_dev_put(dev1);
500
501 return ret;
502 }
503
504 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
505 const struct pci_device_id *ent)
506 {
507 struct agp_bridge_data *bridge;
508 u8 cap_ptr;
509 int err;
510
511 /* The Highlander principle */
512 if (agp_bridges_found)
513 return -ENODEV;
514
515 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
516 if (!cap_ptr)
517 return -ENODEV;
518
519 /* Could check for AGPv3 here */
520
521 bridge = agp_alloc_bridge();
522 if (!bridge)
523 return -ENOMEM;
524
525 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
526 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
527 amd8151_init(pdev, bridge);
528 } else {
529 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
530 pdev->vendor, pdev->device);
531 }
532
533 bridge->driver = &amd_8151_driver;
534 bridge->dev = pdev;
535 bridge->capndx = cap_ptr;
536
537 /* Fill in the mode register */
538 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
539
540 if (cache_nbs(pdev, cap_ptr) == -1) {
541 agp_put_bridge(bridge);
542 return -ENODEV;
543 }
544
545 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
546 int ret = nforce3_agp_init(pdev);
547 if (ret) {
548 agp_put_bridge(bridge);
549 return ret;
550 }
551 }
552
553 if (pdev->vendor == PCI_VENDOR_ID_AL) {
554 int ret = uli_agp_init(pdev);
555 if (ret) {
556 agp_put_bridge(bridge);
557 return ret;
558 }
559 }
560
561 pci_set_drvdata(pdev, bridge);
562 err = agp_add_bridge(bridge);
563 if (err < 0)
564 return err;
565
566 agp_bridges_found++;
567 return 0;
568 }
569
570 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
571 {
572 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
573
574 release_mem_region(virt_to_phys(bridge->gatt_table_real),
575 amd64_aperture_sizes[bridge->aperture_size_idx].size);
576 agp_remove_bridge(bridge);
577 agp_put_bridge(bridge);
578
579 agp_bridges_found--;
580 }
581
582 #ifdef CONFIG_PM
583
584 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
585 {
586 pci_save_state(pdev);
587 pci_set_power_state(pdev, pci_choose_state(pdev, state));
588
589 return 0;
590 }
591
592 static int agp_amd64_resume(struct pci_dev *pdev)
593 {
594 pci_set_power_state(pdev, PCI_D0);
595 pci_restore_state(pdev);
596
597 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
598 nforce3_agp_init(pdev);
599
600 return amd_8151_configure();
601 }
602
603 #endif /* CONFIG_PM */
604
605 static struct pci_device_id agp_amd64_pci_table[] = {
606 {
607 .class = (PCI_CLASS_BRIDGE_HOST << 8),
608 .class_mask = ~0,
609 .vendor = PCI_VENDOR_ID_AMD,
610 .device = PCI_DEVICE_ID_AMD_8151_0,
611 .subvendor = PCI_ANY_ID,
612 .subdevice = PCI_ANY_ID,
613 },
614 /* ULi M1689 */
615 {
616 .class = (PCI_CLASS_BRIDGE_HOST << 8),
617 .class_mask = ~0,
618 .vendor = PCI_VENDOR_ID_AL,
619 .device = PCI_DEVICE_ID_AL_M1689,
620 .subvendor = PCI_ANY_ID,
621 .subdevice = PCI_ANY_ID,
622 },
623 /* VIA K8T800Pro */
624 {
625 .class = (PCI_CLASS_BRIDGE_HOST << 8),
626 .class_mask = ~0,
627 .vendor = PCI_VENDOR_ID_VIA,
628 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 },
632 /* VIA K8T800 */
633 {
634 .class = (PCI_CLASS_BRIDGE_HOST << 8),
635 .class_mask = ~0,
636 .vendor = PCI_VENDOR_ID_VIA,
637 .device = PCI_DEVICE_ID_VIA_8385_0,
638 .subvendor = PCI_ANY_ID,
639 .subdevice = PCI_ANY_ID,
640 },
641 /* VIA K8M800 / K8N800 */
642 {
643 .class = (PCI_CLASS_BRIDGE_HOST << 8),
644 .class_mask = ~0,
645 .vendor = PCI_VENDOR_ID_VIA,
646 .device = PCI_DEVICE_ID_VIA_8380_0,
647 .subvendor = PCI_ANY_ID,
648 .subdevice = PCI_ANY_ID,
649 },
650 /* VIA K8M890 / K8N890 */
651 {
652 .class = (PCI_CLASS_BRIDGE_HOST << 8),
653 .class_mask = ~0,
654 .vendor = PCI_VENDOR_ID_VIA,
655 .device = PCI_DEVICE_ID_VIA_VT3336,
656 .subvendor = PCI_ANY_ID,
657 .subdevice = PCI_ANY_ID,
658 },
659 /* VIA K8T890 */
660 {
661 .class = (PCI_CLASS_BRIDGE_HOST << 8),
662 .class_mask = ~0,
663 .vendor = PCI_VENDOR_ID_VIA,
664 .device = PCI_DEVICE_ID_VIA_3238_0,
665 .subvendor = PCI_ANY_ID,
666 .subdevice = PCI_ANY_ID,
667 },
668 /* VIA K8T800/K8M800/K8N800 */
669 {
670 .class = (PCI_CLASS_BRIDGE_HOST << 8),
671 .class_mask = ~0,
672 .vendor = PCI_VENDOR_ID_VIA,
673 .device = PCI_DEVICE_ID_VIA_838X_1,
674 .subvendor = PCI_ANY_ID,
675 .subdevice = PCI_ANY_ID,
676 },
677 /* NForce3 */
678 {
679 .class = (PCI_CLASS_BRIDGE_HOST << 8),
680 .class_mask = ~0,
681 .vendor = PCI_VENDOR_ID_NVIDIA,
682 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
683 .subvendor = PCI_ANY_ID,
684 .subdevice = PCI_ANY_ID,
685 },
686 {
687 .class = (PCI_CLASS_BRIDGE_HOST << 8),
688 .class_mask = ~0,
689 .vendor = PCI_VENDOR_ID_NVIDIA,
690 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
691 .subvendor = PCI_ANY_ID,
692 .subdevice = PCI_ANY_ID,
693 },
694 /* SIS 755 */
695 {
696 .class = (PCI_CLASS_BRIDGE_HOST << 8),
697 .class_mask = ~0,
698 .vendor = PCI_VENDOR_ID_SI,
699 .device = PCI_DEVICE_ID_SI_755,
700 .subvendor = PCI_ANY_ID,
701 .subdevice = PCI_ANY_ID,
702 },
703 /* SIS 760 */
704 {
705 .class = (PCI_CLASS_BRIDGE_HOST << 8),
706 .class_mask = ~0,
707 .vendor = PCI_VENDOR_ID_SI,
708 .device = PCI_DEVICE_ID_SI_760,
709 .subvendor = PCI_ANY_ID,
710 .subdevice = PCI_ANY_ID,
711 },
712 /* ALI/ULI M1695 */
713 {
714 .class = (PCI_CLASS_BRIDGE_HOST << 8),
715 .class_mask = ~0,
716 .vendor = PCI_VENDOR_ID_AL,
717 .device = 0x1695,
718 .subvendor = PCI_ANY_ID,
719 .subdevice = PCI_ANY_ID,
720 },
721
722 { }
723 };
724
725 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
726
727 static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = {
728 { PCI_DEVICE_CLASS(0, 0) },
729 { }
730 };
731
732 static struct pci_driver agp_amd64_pci_driver = {
733 .name = "agpgart-amd64",
734 .id_table = agp_amd64_pci_table,
735 .probe = agp_amd64_probe,
736 .remove = agp_amd64_remove,
737 #ifdef CONFIG_PM
738 .suspend = agp_amd64_suspend,
739 .resume = agp_amd64_resume,
740 #endif
741 };
742
743
744 /* Not static due to IOMMU code calling it early. */
745 int __init agp_amd64_init(void)
746 {
747 int err = 0;
748
749 if (agp_off)
750 return -EINVAL;
751
752 err = pci_register_driver(&agp_amd64_pci_driver);
753 if (err < 0)
754 return err;
755
756 if (agp_bridges_found == 0) {
757 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
758 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
759 #ifdef MODULE
760 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
761 #else
762 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
763 #endif
764 return -ENODEV;
765 }
766
767 /* First check that we have at least one AMD64 NB */
768 if (!pci_dev_present(k8_nb_ids))
769 return -ENODEV;
770
771 /* Look for any AGP bridge */
772 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
773 err = driver_attach(&agp_amd64_pci_driver.driver);
774 if (err == 0 && agp_bridges_found == 0)
775 err = -ENODEV;
776 }
777 return err;
778 }
779
780 static int __init agp_amd64_mod_init(void)
781 {
782 #ifndef MODULE
783 if (gart_iommu_aperture)
784 return agp_bridges_found ? 0 : -ENODEV;
785 #endif
786 return agp_amd64_init();
787 }
788
789 static void __exit agp_amd64_cleanup(void)
790 {
791 #ifndef MODULE
792 if (gart_iommu_aperture)
793 return;
794 #endif
795 if (aperture_resource)
796 release_resource(aperture_resource);
797 pci_unregister_driver(&agp_amd64_pci_driver);
798 }
799
800 module_init(agp_amd64_mod_init);
801 module_exit(agp_amd64_cleanup);
802
803 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
804 module_param(agp_try_unsupported, bool, 0);
805 MODULE_LICENSE("GPL");
Linux with added FPC-III support