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floppy: make controller const
[linux/fpc-iii.git] / drivers / char / agp / intel-agp.c
blobd836a71bf06db79f5df5b1fb1ddbd6b79e660081
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/slab.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/pagemap.h>
11 #include <linux/agp_backend.h>
12 #include <asm/smp.h>
13 #include "agp.h"
14 #include "intel-agp.h"
15
16 #include "intel-gtt.c"
17
18 int intel_agp_enabled;
19 EXPORT_SYMBOL(intel_agp_enabled);
20
21 static int intel_fetch_size(void)
22 {
23 int i;
24 u16 temp;
25 struct aper_size_info_16 *values;
26
27 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
28 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
29
30 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
31 if (temp == values[i].size_value) {
32 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
33 agp_bridge->aperture_size_idx = i;
34 return values[i].size;
35 }
36 }
37
38 return 0;
39 }
40
41 static int __intel_8xx_fetch_size(u8 temp)
42 {
43 int i;
44 struct aper_size_info_8 *values;
45
46 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
47
48 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
49 if (temp == values[i].size_value) {
50 agp_bridge->previous_size =
51 agp_bridge->current_size = (void *) (values + i);
52 agp_bridge->aperture_size_idx = i;
53 return values[i].size;
54 }
55 }
56 return 0;
57 }
58
59 static int intel_8xx_fetch_size(void)
60 {
61 u8 temp;
62
63 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
64 return __intel_8xx_fetch_size(temp);
65 }
66
67 static int intel_815_fetch_size(void)
68 {
69 u8 temp;
70
71 /* Intel 815 chipsets have a _weird_ APSIZE register with only
72 * one non-reserved bit, so mask the others out ... */
73 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
74 temp &= (1 << 3);
75
76 return __intel_8xx_fetch_size(temp);
77 }
78
79 static void intel_tlbflush(struct agp_memory *mem)
80 {
81 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
82 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
83 }
84
85
86 static void intel_8xx_tlbflush(struct agp_memory *mem)
87 {
88 u32 temp;
89 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
90 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
91 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
92 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
93 }
94
95
96 static void intel_cleanup(void)
97 {
98 u16 temp;
99 struct aper_size_info_16 *previous_size;
100
101 previous_size = A_SIZE_16(agp_bridge->previous_size);
102 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
103 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
104 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
105 }
106
107
108 static void intel_8xx_cleanup(void)
109 {
110 u16 temp;
111 struct aper_size_info_8 *previous_size;
112
113 previous_size = A_SIZE_8(agp_bridge->previous_size);
114 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
115 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
116 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
117 }
118
119
120 static int intel_configure(void)
121 {
122 u32 temp;
123 u16 temp2;
124 struct aper_size_info_16 *current_size;
125
126 current_size = A_SIZE_16(agp_bridge->current_size);
127
128 /* aperture size */
129 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
130
131 /* address to map to */
132 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
133 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
134
135 /* attbase - aperture base */
136 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
137
138 /* agpctrl */
139 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
140
141 /* paccfg/nbxcfg */
142 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
143 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
144 (temp2 & ~(1 << 10)) | (1 << 9));
145 /* clear any possible error conditions */
146 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
147 return 0;
148 }
149
150 static int intel_815_configure(void)
151 {
152 u32 temp, addr;
153 u8 temp2;
154 struct aper_size_info_8 *current_size;
155
156 /* attbase - aperture base */
157 /* the Intel 815 chipset spec. says that bits 29-31 in the
158 * ATTBASE register are reserved -> try not to write them */
159 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
160 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
161 return -EINVAL;
162 }
163
164 current_size = A_SIZE_8(agp_bridge->current_size);
165
166 /* aperture size */
167 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
168 current_size->size_value);
169
170 /* address to map to */
171 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
172 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
173
174 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
175 addr &= INTEL_815_ATTBASE_MASK;
176 addr |= agp_bridge->gatt_bus_addr;
177 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
178
179 /* agpctrl */
180 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
181
182 /* apcont */
183 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
184 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
185
186 /* clear any possible error conditions */
187 /* Oddness : this chipset seems to have no ERRSTS register ! */
188 return 0;
189 }
190
191 static void intel_820_tlbflush(struct agp_memory *mem)
192 {
193 return;
194 }
195
196 static void intel_820_cleanup(void)
197 {
198 u8 temp;
199 struct aper_size_info_8 *previous_size;
200
201 previous_size = A_SIZE_8(agp_bridge->previous_size);
202 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
203 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
204 temp & ~(1 << 1));
205 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
206 previous_size->size_value);
207 }
208
209
210 static int intel_820_configure(void)
211 {
212 u32 temp;
213 u8 temp2;
214 struct aper_size_info_8 *current_size;
215
216 current_size = A_SIZE_8(agp_bridge->current_size);
217
218 /* aperture size */
219 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
220
221 /* address to map to */
222 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
223 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
224
225 /* attbase - aperture base */
226 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
227
228 /* agpctrl */
229 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
230
231 /* global enable aperture access */
232 /* This flag is not accessed through MCHCFG register as in */
233 /* i850 chipset. */
234 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
235 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
236 /* clear any possible AGP-related error conditions */
237 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
238 return 0;
239 }
240
241 static int intel_840_configure(void)
242 {
243 u32 temp;
244 u16 temp2;
245 struct aper_size_info_8 *current_size;
246
247 current_size = A_SIZE_8(agp_bridge->current_size);
248
249 /* aperture size */
250 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
251
252 /* address to map to */
253 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
254 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
255
256 /* attbase - aperture base */
257 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
258
259 /* agpctrl */
260 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
261
262 /* mcgcfg */
263 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
264 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
265 /* clear any possible error conditions */
266 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
267 return 0;
268 }
269
270 static int intel_845_configure(void)
271 {
272 u32 temp;
273 u8 temp2;
274 struct aper_size_info_8 *current_size;
275
276 current_size = A_SIZE_8(agp_bridge->current_size);
277
278 /* aperture size */
279 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
280
281 if (agp_bridge->apbase_config != 0) {
282 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
283 agp_bridge->apbase_config);
284 } else {
285 /* address to map to */
286 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
287 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
288 agp_bridge->apbase_config = temp;
289 }
290
291 /* attbase - aperture base */
292 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
293
294 /* agpctrl */
295 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
296
297 /* agpm */
298 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
299 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
300 /* clear any possible error conditions */
301 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
302 return 0;
303 }
304
305 static int intel_850_configure(void)
306 {
307 u32 temp;
308 u16 temp2;
309 struct aper_size_info_8 *current_size;
310
311 current_size = A_SIZE_8(agp_bridge->current_size);
312
313 /* aperture size */
314 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
315
316 /* address to map to */
317 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
318 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
319
320 /* attbase - aperture base */
321 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
322
323 /* agpctrl */
324 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
325
326 /* mcgcfg */
327 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
328 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
329 /* clear any possible AGP-related error conditions */
330 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
331 return 0;
332 }
333
334 static int intel_860_configure(void)
335 {
336 u32 temp;
337 u16 temp2;
338 struct aper_size_info_8 *current_size;
339
340 current_size = A_SIZE_8(agp_bridge->current_size);
341
342 /* aperture size */
343 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
344
345 /* address to map to */
346 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
347 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
348
349 /* attbase - aperture base */
350 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
351
352 /* agpctrl */
353 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
354
355 /* mcgcfg */
356 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
357 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
358 /* clear any possible AGP-related error conditions */
359 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
360 return 0;
361 }
362
363 static int intel_830mp_configure(void)
364 {
365 u32 temp;
366 u16 temp2;
367 struct aper_size_info_8 *current_size;
368
369 current_size = A_SIZE_8(agp_bridge->current_size);
370
371 /* aperture size */
372 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
373
374 /* address to map to */
375 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
376 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
377
378 /* attbase - aperture base */
379 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
380
381 /* agpctrl */
382 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
383
384 /* gmch */
385 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
386 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
387 /* clear any possible AGP-related error conditions */
388 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
389 return 0;
390 }
391
392 static int intel_7505_configure(void)
393 {
394 u32 temp;
395 u16 temp2;
396 struct aper_size_info_8 *current_size;
397
398 current_size = A_SIZE_8(agp_bridge->current_size);
399
400 /* aperture size */
401 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
402
403 /* address to map to */
404 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
405 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
406
407 /* attbase - aperture base */
408 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
409
410 /* agpctrl */
411 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
412
413 /* mchcfg */
414 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
415 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
416
417 return 0;
418 }
419
420 /* Setup function */
421 static const struct gatt_mask intel_generic_masks[] =
422 {
423 {.mask = 0x00000017, .type = 0}
424 };
425
426 static const struct aper_size_info_8 intel_815_sizes[2] =
427 {
428 {64, 16384, 4, 0},
429 {32, 8192, 3, 8},
430 };
431
432 static const struct aper_size_info_8 intel_8xx_sizes[7] =
433 {
434 {256, 65536, 6, 0},
435 {128, 32768, 5, 32},
436 {64, 16384, 4, 48},
437 {32, 8192, 3, 56},
438 {16, 4096, 2, 60},
439 {8, 2048, 1, 62},
440 {4, 1024, 0, 63}
441 };
442
443 static const struct aper_size_info_16 intel_generic_sizes[7] =
444 {
445 {256, 65536, 6, 0},
446 {128, 32768, 5, 32},
447 {64, 16384, 4, 48},
448 {32, 8192, 3, 56},
449 {16, 4096, 2, 60},
450 {8, 2048, 1, 62},
451 {4, 1024, 0, 63}
452 };
453
454 static const struct aper_size_info_8 intel_830mp_sizes[4] =
455 {
456 {256, 65536, 6, 0},
457 {128, 32768, 5, 32},
458 {64, 16384, 4, 48},
459 {32, 8192, 3, 56}
460 };
461
462 static const struct agp_bridge_driver intel_generic_driver = {
463 .owner = THIS_MODULE,
464 .aperture_sizes = intel_generic_sizes,
465 .size_type = U16_APER_SIZE,
466 .num_aperture_sizes = 7,
467 .needs_scratch_page = true,
468 .configure = intel_configure,
469 .fetch_size = intel_fetch_size,
470 .cleanup = intel_cleanup,
471 .tlb_flush = intel_tlbflush,
472 .mask_memory = agp_generic_mask_memory,
473 .masks = intel_generic_masks,
474 .agp_enable = agp_generic_enable,
475 .cache_flush = global_cache_flush,
476 .create_gatt_table = agp_generic_create_gatt_table,
477 .free_gatt_table = agp_generic_free_gatt_table,
478 .insert_memory = agp_generic_insert_memory,
479 .remove_memory = agp_generic_remove_memory,
480 .alloc_by_type = agp_generic_alloc_by_type,
481 .free_by_type = agp_generic_free_by_type,
482 .agp_alloc_page = agp_generic_alloc_page,
483 .agp_alloc_pages = agp_generic_alloc_pages,
484 .agp_destroy_page = agp_generic_destroy_page,
485 .agp_destroy_pages = agp_generic_destroy_pages,
486 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
487 };
488
489 static const struct agp_bridge_driver intel_815_driver = {
490 .owner = THIS_MODULE,
491 .aperture_sizes = intel_815_sizes,
492 .size_type = U8_APER_SIZE,
493 .num_aperture_sizes = 2,
494 .needs_scratch_page = true,
495 .configure = intel_815_configure,
496 .fetch_size = intel_815_fetch_size,
497 .cleanup = intel_8xx_cleanup,
498 .tlb_flush = intel_8xx_tlbflush,
499 .mask_memory = agp_generic_mask_memory,
500 .masks = intel_generic_masks,
501 .agp_enable = agp_generic_enable,
502 .cache_flush = global_cache_flush,
503 .create_gatt_table = agp_generic_create_gatt_table,
504 .free_gatt_table = agp_generic_free_gatt_table,
505 .insert_memory = agp_generic_insert_memory,
506 .remove_memory = agp_generic_remove_memory,
507 .alloc_by_type = agp_generic_alloc_by_type,
508 .free_by_type = agp_generic_free_by_type,
509 .agp_alloc_page = agp_generic_alloc_page,
510 .agp_alloc_pages = agp_generic_alloc_pages,
511 .agp_destroy_page = agp_generic_destroy_page,
512 .agp_destroy_pages = agp_generic_destroy_pages,
513 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
514 };
515
516 static const struct agp_bridge_driver intel_820_driver = {
517 .owner = THIS_MODULE,
518 .aperture_sizes = intel_8xx_sizes,
519 .size_type = U8_APER_SIZE,
520 .num_aperture_sizes = 7,
521 .needs_scratch_page = true,
522 .configure = intel_820_configure,
523 .fetch_size = intel_8xx_fetch_size,
524 .cleanup = intel_820_cleanup,
525 .tlb_flush = intel_820_tlbflush,
526 .mask_memory = agp_generic_mask_memory,
527 .masks = intel_generic_masks,
528 .agp_enable = agp_generic_enable,
529 .cache_flush = global_cache_flush,
530 .create_gatt_table = agp_generic_create_gatt_table,
531 .free_gatt_table = agp_generic_free_gatt_table,
532 .insert_memory = agp_generic_insert_memory,
533 .remove_memory = agp_generic_remove_memory,
534 .alloc_by_type = agp_generic_alloc_by_type,
535 .free_by_type = agp_generic_free_by_type,
536 .agp_alloc_page = agp_generic_alloc_page,
537 .agp_alloc_pages = agp_generic_alloc_pages,
538 .agp_destroy_page = agp_generic_destroy_page,
539 .agp_destroy_pages = agp_generic_destroy_pages,
540 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
541 };
542
543 static const struct agp_bridge_driver intel_830mp_driver = {
544 .owner = THIS_MODULE,
545 .aperture_sizes = intel_830mp_sizes,
546 .size_type = U8_APER_SIZE,
547 .num_aperture_sizes = 4,
548 .needs_scratch_page = true,
549 .configure = intel_830mp_configure,
550 .fetch_size = intel_8xx_fetch_size,
551 .cleanup = intel_8xx_cleanup,
552 .tlb_flush = intel_8xx_tlbflush,
553 .mask_memory = agp_generic_mask_memory,
554 .masks = intel_generic_masks,
555 .agp_enable = agp_generic_enable,
556 .cache_flush = global_cache_flush,
557 .create_gatt_table = agp_generic_create_gatt_table,
558 .free_gatt_table = agp_generic_free_gatt_table,
559 .insert_memory = agp_generic_insert_memory,
560 .remove_memory = agp_generic_remove_memory,
561 .alloc_by_type = agp_generic_alloc_by_type,
562 .free_by_type = agp_generic_free_by_type,
563 .agp_alloc_page = agp_generic_alloc_page,
564 .agp_alloc_pages = agp_generic_alloc_pages,
565 .agp_destroy_page = agp_generic_destroy_page,
566 .agp_destroy_pages = agp_generic_destroy_pages,
567 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
568 };
569
570 static const struct agp_bridge_driver intel_840_driver = {
571 .owner = THIS_MODULE,
572 .aperture_sizes = intel_8xx_sizes,
573 .size_type = U8_APER_SIZE,
574 .num_aperture_sizes = 7,
575 .needs_scratch_page = true,
576 .configure = intel_840_configure,
577 .fetch_size = intel_8xx_fetch_size,
578 .cleanup = intel_8xx_cleanup,
579 .tlb_flush = intel_8xx_tlbflush,
580 .mask_memory = agp_generic_mask_memory,
581 .masks = intel_generic_masks,
582 .agp_enable = agp_generic_enable,
583 .cache_flush = global_cache_flush,
584 .create_gatt_table = agp_generic_create_gatt_table,
585 .free_gatt_table = agp_generic_free_gatt_table,
586 .insert_memory = agp_generic_insert_memory,
587 .remove_memory = agp_generic_remove_memory,
588 .alloc_by_type = agp_generic_alloc_by_type,
589 .free_by_type = agp_generic_free_by_type,
590 .agp_alloc_page = agp_generic_alloc_page,
591 .agp_alloc_pages = agp_generic_alloc_pages,
592 .agp_destroy_page = agp_generic_destroy_page,
593 .agp_destroy_pages = agp_generic_destroy_pages,
594 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
595 };
596
597 static const struct agp_bridge_driver intel_845_driver = {
598 .owner = THIS_MODULE,
599 .aperture_sizes = intel_8xx_sizes,
600 .size_type = U8_APER_SIZE,
601 .num_aperture_sizes = 7,
602 .needs_scratch_page = true,
603 .configure = intel_845_configure,
604 .fetch_size = intel_8xx_fetch_size,
605 .cleanup = intel_8xx_cleanup,
606 .tlb_flush = intel_8xx_tlbflush,
607 .mask_memory = agp_generic_mask_memory,
608 .masks = intel_generic_masks,
609 .agp_enable = agp_generic_enable,
610 .cache_flush = global_cache_flush,
611 .create_gatt_table = agp_generic_create_gatt_table,
612 .free_gatt_table = agp_generic_free_gatt_table,
613 .insert_memory = agp_generic_insert_memory,
614 .remove_memory = agp_generic_remove_memory,
615 .alloc_by_type = agp_generic_alloc_by_type,
616 .free_by_type = agp_generic_free_by_type,
617 .agp_alloc_page = agp_generic_alloc_page,
618 .agp_alloc_pages = agp_generic_alloc_pages,
619 .agp_destroy_page = agp_generic_destroy_page,
620 .agp_destroy_pages = agp_generic_destroy_pages,
621 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
622 };
623
624 static const struct agp_bridge_driver intel_850_driver = {
625 .owner = THIS_MODULE,
626 .aperture_sizes = intel_8xx_sizes,
627 .size_type = U8_APER_SIZE,
628 .num_aperture_sizes = 7,
629 .needs_scratch_page = true,
630 .configure = intel_850_configure,
631 .fetch_size = intel_8xx_fetch_size,
632 .cleanup = intel_8xx_cleanup,
633 .tlb_flush = intel_8xx_tlbflush,
634 .mask_memory = agp_generic_mask_memory,
635 .masks = intel_generic_masks,
636 .agp_enable = agp_generic_enable,
637 .cache_flush = global_cache_flush,
638 .create_gatt_table = agp_generic_create_gatt_table,
639 .free_gatt_table = agp_generic_free_gatt_table,
640 .insert_memory = agp_generic_insert_memory,
641 .remove_memory = agp_generic_remove_memory,
642 .alloc_by_type = agp_generic_alloc_by_type,
643 .free_by_type = agp_generic_free_by_type,
644 .agp_alloc_page = agp_generic_alloc_page,
645 .agp_alloc_pages = agp_generic_alloc_pages,
646 .agp_destroy_page = agp_generic_destroy_page,
647 .agp_destroy_pages = agp_generic_destroy_pages,
648 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
649 };
650
651 static const struct agp_bridge_driver intel_860_driver = {
652 .owner = THIS_MODULE,
653 .aperture_sizes = intel_8xx_sizes,
654 .size_type = U8_APER_SIZE,
655 .num_aperture_sizes = 7,
656 .needs_scratch_page = true,
657 .configure = intel_860_configure,
658 .fetch_size = intel_8xx_fetch_size,
659 .cleanup = intel_8xx_cleanup,
660 .tlb_flush = intel_8xx_tlbflush,
661 .mask_memory = agp_generic_mask_memory,
662 .masks = intel_generic_masks,
663 .agp_enable = agp_generic_enable,
664 .cache_flush = global_cache_flush,
665 .create_gatt_table = agp_generic_create_gatt_table,
666 .free_gatt_table = agp_generic_free_gatt_table,
667 .insert_memory = agp_generic_insert_memory,
668 .remove_memory = agp_generic_remove_memory,
669 .alloc_by_type = agp_generic_alloc_by_type,
670 .free_by_type = agp_generic_free_by_type,
671 .agp_alloc_page = agp_generic_alloc_page,
672 .agp_alloc_pages = agp_generic_alloc_pages,
673 .agp_destroy_page = agp_generic_destroy_page,
674 .agp_destroy_pages = agp_generic_destroy_pages,
675 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
676 };
677
678 static const struct agp_bridge_driver intel_7505_driver = {
679 .owner = THIS_MODULE,
680 .aperture_sizes = intel_8xx_sizes,
681 .size_type = U8_APER_SIZE,
682 .num_aperture_sizes = 7,
683 .needs_scratch_page = true,
684 .configure = intel_7505_configure,
685 .fetch_size = intel_8xx_fetch_size,
686 .cleanup = intel_8xx_cleanup,
687 .tlb_flush = intel_8xx_tlbflush,
688 .mask_memory = agp_generic_mask_memory,
689 .masks = intel_generic_masks,
690 .agp_enable = agp_generic_enable,
691 .cache_flush = global_cache_flush,
692 .create_gatt_table = agp_generic_create_gatt_table,
693 .free_gatt_table = agp_generic_free_gatt_table,
694 .insert_memory = agp_generic_insert_memory,
695 .remove_memory = agp_generic_remove_memory,
696 .alloc_by_type = agp_generic_alloc_by_type,
697 .free_by_type = agp_generic_free_by_type,
698 .agp_alloc_page = agp_generic_alloc_page,
699 .agp_alloc_pages = agp_generic_alloc_pages,
700 .agp_destroy_page = agp_generic_destroy_page,
701 .agp_destroy_pages = agp_generic_destroy_pages,
702 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
703 };
704
705 static int find_gmch(u16 device)
706 {
707 struct pci_dev *gmch_device;
708
709 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
710 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
711 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
712 device, gmch_device);
713 }
714
715 if (!gmch_device)
716 return 0;
717
718 intel_private.pcidev = gmch_device;
719 return 1;
720 }
721
722 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
723 * driver and gmch_driver must be non-null, and find_gmch will determine
724 * which one should be used if a gmch_chip_id is present.
725 */
726 static const struct intel_driver_description {
727 unsigned int chip_id;
728 unsigned int gmch_chip_id;
729 char *name;
730 const struct agp_bridge_driver *driver;
731 const struct agp_bridge_driver *gmch_driver;
732 } intel_agp_chipsets[] = {
733 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL },
734 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL },
735 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL },
736 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
737 NULL, &intel_810_driver },
738 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
739 NULL, &intel_810_driver },
740 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
741 NULL, &intel_810_driver },
742 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
743 &intel_815_driver, &intel_810_driver },
744 { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL },
745 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL },
746 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
747 &intel_830mp_driver, &intel_830_driver },
748 { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL },
749 { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL },
750 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
751 &intel_845_driver, &intel_830_driver },
752 { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL },
753 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854",
754 &intel_845_driver, &intel_830_driver },
755 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
756 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
757 &intel_845_driver, &intel_830_driver },
758 { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
759 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
760 &intel_845_driver, &intel_830_driver },
761 { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
762 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
763 NULL, &intel_915_driver },
764 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
765 NULL, &intel_915_driver },
766 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
767 NULL, &intel_915_driver },
768 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
769 NULL, &intel_915_driver },
770 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
771 NULL, &intel_915_driver },
772 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
773 NULL, &intel_915_driver },
774 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
775 NULL, &intel_i965_driver },
776 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
777 NULL, &intel_i965_driver },
778 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
779 NULL, &intel_i965_driver },
780 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
781 NULL, &intel_i965_driver },
782 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
783 NULL, &intel_i965_driver },
784 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
785 NULL, &intel_i965_driver },
786 { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
787 { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
788 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33",
789 NULL, &intel_g33_driver },
790 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
791 NULL, &intel_g33_driver },
792 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
793 NULL, &intel_g33_driver },
794 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
795 NULL, &intel_g33_driver },
796 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
797 NULL, &intel_g33_driver },
798 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG,
799 "GM45", NULL, &intel_i965_driver },
800 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG,
801 "Eaglelake", NULL, &intel_i965_driver },
802 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG,
803 "Q45/Q43", NULL, &intel_i965_driver },
804 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG,
805 "G45/G43", NULL, &intel_i965_driver },
806 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG,
807 "B43", NULL, &intel_i965_driver },
808 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG,
809 "G41", NULL, &intel_i965_driver },
810 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
811 "HD Graphics", NULL, &intel_i965_driver },
812 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
813 "HD Graphics", NULL, &intel_i965_driver },
814 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
815 "HD Graphics", NULL, &intel_i965_driver },
816 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
817 "HD Graphics", NULL, &intel_i965_driver },
818 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
819 "Sandybridge", NULL, &intel_i965_driver },
820 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
821 "Sandybridge", NULL, &intel_i965_driver },
822 { 0, 0, NULL, NULL, NULL }
823 };
824
825 static int __devinit intel_gmch_probe(struct pci_dev *pdev,
826 struct agp_bridge_data *bridge)
827 {
828 int i;
829 bridge->driver = NULL;
830
831 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
832 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
833 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
834 bridge->driver =
835 intel_agp_chipsets[i].gmch_driver;
836 break;
837 }
838 }
839
840 if (!bridge->driver)
841 return 0;
842
843 bridge->dev_private_data = &intel_private;
844 bridge->dev = pdev;
845
846 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
847
848 if (bridge->driver->mask_memory == intel_i965_mask_memory) {
849 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
850 dev_err(&intel_private.pcidev->dev,
851 "set gfx device dma mask 36bit failed!\n");
852 else
853 pci_set_consistent_dma_mask(intel_private.pcidev,
854 DMA_BIT_MASK(36));
855 }
856
857 return 1;
858 }
859
860 static int __devinit agp_intel_probe(struct pci_dev *pdev,
861 const struct pci_device_id *ent)
862 {
863 struct agp_bridge_data *bridge;
864 u8 cap_ptr = 0;
865 struct resource *r;
866 int i, err;
867
868 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
869
870 bridge = agp_alloc_bridge();
871 if (!bridge)
872 return -ENOMEM;
873
874 bridge->capndx = cap_ptr;
875
876 if (intel_gmch_probe(pdev, bridge))
877 goto found_gmch;
878
879 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
880 /* In case that multiple models of gfx chip may
881 stand on same host bridge type, this can be
882 sure we detect the right IGD. */
883 if (pdev->device == intel_agp_chipsets[i].chip_id) {
884 bridge->driver = intel_agp_chipsets[i].driver;
885 break;
886 }
887 }
888
889 if (intel_agp_chipsets[i].name == NULL) {
890 if (cap_ptr)
891 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
892 pdev->vendor, pdev->device);
893 agp_put_bridge(bridge);
894 return -ENODEV;
895 }
896
897 if (!bridge->driver) {
898 if (cap_ptr)
899 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
900 intel_agp_chipsets[i].gmch_chip_id);
901 agp_put_bridge(bridge);
902 return -ENODEV;
903 }
904
905 bridge->dev = pdev;
906 bridge->dev_private_data = NULL;
907
908 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
909
910 /*
911 * The following fixes the case where the BIOS has "forgotten" to
912 * provide an address range for the GART.
913 * 20030610 - hamish@zot.org
914 */
915 r = &pdev->resource[0];
916 if (!r->start && r->end) {
917 if (pci_assign_resource(pdev, 0)) {
918 dev_err(&pdev->dev, "can't assign resource 0\n");
919 agp_put_bridge(bridge);
920 return -ENODEV;
921 }
922 }
923
924 /*
925 * If the device has not been properly setup, the following will catch
926 * the problem and should stop the system from crashing.
927 * 20030610 - hamish@zot.org
928 */
929 if (pci_enable_device(pdev)) {
930 dev_err(&pdev->dev, "can't enable PCI device\n");
931 agp_put_bridge(bridge);
932 return -ENODEV;
933 }
934
935 /* Fill in the mode register */
936 if (cap_ptr) {
937 pci_read_config_dword(pdev,
938 bridge->capndx+PCI_AGP_STATUS,
939 &bridge->mode);
940 }
941
942 found_gmch:
943 pci_set_drvdata(pdev, bridge);
944 err = agp_add_bridge(bridge);
945 if (!err)
946 intel_agp_enabled = 1;
947 return err;
948 }
949
950 static void __devexit agp_intel_remove(struct pci_dev *pdev)
951 {
952 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
953
954 agp_remove_bridge(bridge);
955
956 if (intel_private.pcidev)
957 pci_dev_put(intel_private.pcidev);
958
959 agp_put_bridge(bridge);
960 }
961
962 #ifdef CONFIG_PM
963 static int agp_intel_resume(struct pci_dev *pdev)
964 {
965 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
966 int ret_val;
967
968 bridge->driver->configure();
969
970 ret_val = agp_rebind_memory();
971 if (ret_val != 0)
972 return ret_val;
973
974 return 0;
975 }
976 #endif
977
978 static struct pci_device_id agp_intel_pci_table[] = {
979 #define ID(x) \
980 { \
981 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
982 .class_mask = ~0, \
983 .vendor = PCI_VENDOR_ID_INTEL, \
984 .device = x, \
985 .subvendor = PCI_ANY_ID, \
986 .subdevice = PCI_ANY_ID, \
987 }
988 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
989 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
990 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
991 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
992 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
993 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
994 ID(PCI_DEVICE_ID_INTEL_82815_MC),
995 ID(PCI_DEVICE_ID_INTEL_82820_HB),
996 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
997 ID(PCI_DEVICE_ID_INTEL_82830_HB),
998 ID(PCI_DEVICE_ID_INTEL_82840_HB),
999 ID(PCI_DEVICE_ID_INTEL_82845_HB),
1000 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1001 ID(PCI_DEVICE_ID_INTEL_82850_HB),
1002 ID(PCI_DEVICE_ID_INTEL_82854_HB),
1003 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1004 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1005 ID(PCI_DEVICE_ID_INTEL_82860_HB),
1006 ID(PCI_DEVICE_ID_INTEL_82865_HB),
1007 ID(PCI_DEVICE_ID_INTEL_82875_HB),
1008 ID(PCI_DEVICE_ID_INTEL_7505_0),
1009 ID(PCI_DEVICE_ID_INTEL_7205_0),
1010 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
1011 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1012 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1013 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1014 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1015 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
1016 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
1017 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
1018 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1019 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
1020 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1021 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1022 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
1023 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
1024 ID(PCI_DEVICE_ID_INTEL_G33_HB),
1025 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
1026 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
1027 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
1028 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
1029 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
1030 ID(PCI_DEVICE_ID_INTEL_G45_HB),
1031 ID(PCI_DEVICE_ID_INTEL_G41_HB),
1032 ID(PCI_DEVICE_ID_INTEL_B43_HB),
1033 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
1034 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
1035 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
1036 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
1037 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
1038 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
1039 { }
1040 };
1041
1042 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1043
1044 static struct pci_driver agp_intel_pci_driver = {
1045 .name = "agpgart-intel",
1046 .id_table = agp_intel_pci_table,
1047 .probe = agp_intel_probe,
1048 .remove = __devexit_p(agp_intel_remove),
1049 #ifdef CONFIG_PM
1050 .resume = agp_intel_resume,
1051 #endif
1052 };
1053
1054 static int __init agp_intel_init(void)
1055 {
1056 if (agp_off)
1057 return -EINVAL;
1058 return pci_register_driver(&agp_intel_pci_driver);
1059 }
1060
1061 static void __exit agp_intel_cleanup(void)
1062 {
1063 pci_unregister_driver(&agp_intel_pci_driver);
1064 }
1065
1066 module_init(agp_intel_init);
1067 module_exit(agp_intel_cleanup);
1068
1069 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1070 MODULE_LICENSE("GPL and additional rights");
Linux with added FPC-III support