arch/alpha/kernel/sys_eb64p.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      linux/arch/alpha/kernel/sys_eb64p.c
   4  *
   5  *      Copyright (C) 1995 David A Rusling
   6  *      Copyright (C) 1996 Jay A Estabrook
   7  *      Copyright (C) 1998, 1999 Richard Henderson
   8  *
   9  * Code supporting the EB64+ and EB66.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/dma.h>
  22 #include <asm/irq.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/io.h>
  25 #include <asm/core_apecs.h>
  26 #include <asm/core_lca.h>
  27 #include <asm/hwrpb.h>
  28 #include <asm/tlbflush.h>
  29
  30 #include "proto.h"
  31 #include "irq_impl.h"
  32 #include "pci_impl.h"
  33 #include "machvec_impl.h"
  34
  35
  36 /* Note mask bit is true for DISABLED irqs.  */
  37 static unsigned int cached_irq_mask = -1;
  38
  39 static inline void
  40 eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
  41 {
  42         outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26));
  43 }
  44
  45 static inline void
  46 eb64p_enable_irq(struct irq_data *d)
  47 {
  48         eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
  49 }
  50
  51 static void
  52 eb64p_disable_irq(struct irq_data *d)
  53 {
  54         eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
  55 }
  56
  57 static struct irq_chip eb64p_irq_type = {
  58         .name           = "EB64P",
  59         .irq_unmask     = eb64p_enable_irq,
  60         .irq_mask       = eb64p_disable_irq,
  61         .irq_mask_ack   = eb64p_disable_irq,
  62 };
  63
  64 static void
  65 eb64p_device_interrupt(unsigned long vector)
  66 {
  67         unsigned long pld;
  68         unsigned int i;
  69
  70         /* Read the interrupt summary registers */
  71         pld = inb(0x26) | (inb(0x27) << 8);
  72
  73         /*
  74          * Now, for every possible bit set, work through
  75          * them and call the appropriate interrupt handler.
  76          */
  77         while (pld) {
  78                 i = ffz(~pld);
  79                 pld &= pld - 1; /* clear least bit set */
  80
  81                 if (i == 5) {
  82                         isa_device_interrupt(vector);
  83                 } else {
  84                         handle_irq(16 + i);
  85                 }
  86         }
  87 }
  88
  89 static void __init
  90 eb64p_init_irq(void)
  91 {
  92         long i;
  93
  94 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
  95         /*
  96          * CABRIO SRM may not set variation correctly, so here we test
  97          * the high word of the interrupt summary register for the RAZ
  98          * bits, and hope that a true EB64+ would read all ones...
  99          */
 100         if (inw(0x806) != 0xffff) {
 101                 extern struct alpha_machine_vector cabriolet_mv;
 102
 103                 printk("Detected Cabriolet: correcting HWRPB.\n");
 104
 105                 hwrpb->sys_variation |= 2L << 10;
 106                 hwrpb_update_checksum(hwrpb);
 107
 108                 alpha_mv = cabriolet_mv;
 109                 alpha_mv.init_irq();
 110                 return;
 111         }
 112 #endif /* GENERIC */
 113
 114         outb(0xff, 0x26);
 115         outb(0xff, 0x27);
 116
 117         init_i8259a_irqs();
 118
 119         for (i = 16; i < 32; ++i) {
 120                 irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
 121                 irq_set_status_flags(i, IRQ_LEVEL);
 122         }
 123
 124         common_init_isa_dma();
 125         if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL))
 126                 pr_err("Failed to register isa-cascade interrupt\n");
 127 }
 128
 129 /*
 130  * PCI Fixup configuration.
 131  *
 132  * There are two 8 bit external summary registers as follows:
 133  *
 134  * Summary @ 0x26:
 135  * Bit      Meaning
 136  * 0        Interrupt Line A from slot 0
 137  * 1        Interrupt Line A from slot 1
 138  * 2        Interrupt Line B from slot 0
 139  * 3        Interrupt Line B from slot 1
 140  * 4        Interrupt Line C from slot 0
 141  * 5        Interrupt line from the two ISA PICs
 142  * 6        Tulip
 143  * 7        NCR SCSI
 144  *
 145  * Summary @ 0x27
 146  * Bit      Meaning
 147  * 0        Interrupt Line C from slot 1
 148  * 1        Interrupt Line D from slot 0
 149  * 2        Interrupt Line D from slot 1
 150  * 3        RAZ
 151  * 4        RAZ
 152  * 5        RAZ
 153  * 6        RAZ
 154  * 7        RAZ
 155  *
 156  * The device to slot mapping looks like:
 157  *
 158  * Slot     Device
 159  *  5       NCR SCSI controller
 160  *  6       PCI on board slot 0
 161  *  7       PCI on board slot 1
 162  *  8       Intel SIO PCI-ISA bridge chip
 163  *  9       Tulip - DECchip 21040 Ethernet controller
 164  *
 165  *
 166  * This two layered interrupt approach means that we allocate IRQ 16 and
 167  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 168  * comes in on.  This makes interrupt processing much easier.
 169  */
 170
 171 static int
 172 eb64p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 173 {
 174         static char irq_tab[5][5] = {
 175                 /*INT  INTA  INTB  INTC   INTD */
 176                 {16+7, 16+7, 16+7, 16+7,  16+7},  /* IdSel 5,  slot ?, ?? */
 177                 {16+0, 16+0, 16+2, 16+4,  16+9},  /* IdSel 6,  slot ?, ?? */
 178                 {16+1, 16+1, 16+3, 16+8, 16+10},  /* IdSel 7,  slot ?, ?? */
 179                 {  -1,   -1,   -1,   -1,    -1},  /* IdSel 8,  SIO */
 180                 {16+6, 16+6, 16+6, 16+6,  16+6},  /* IdSel 9,  TULIP */
 181         };
 182         const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
 183         return COMMON_TABLE_LOOKUP;
 184 }
 185
 186
 187 /*
 188  * The System Vector
 189  */
 190
 191 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P)
 192 struct alpha_machine_vector eb64p_mv __initmv = {
 193         .vector_name            = "EB64+",
 194         DO_EV4_MMU,
 195         DO_DEFAULT_RTC,
 196         DO_APECS_IO,
 197         .machine_check          = apecs_machine_check,
 198         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 199         .min_io_address         = DEFAULT_IO_BASE,
 200         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 201
 202         .nr_irqs                = 32,
 203         .device_interrupt       = eb64p_device_interrupt,
 204
 205         .init_arch              = apecs_init_arch,
 206         .init_irq               = eb64p_init_irq,
 207         .init_rtc               = common_init_rtc,
 208         .init_pci               = common_init_pci,
 209         .kill_arch              = NULL,
 210         .pci_map_irq            = eb64p_map_irq,
 211         .pci_swizzle            = common_swizzle,
 212 };
 213 ALIAS_MV(eb64p)
 214 #endif
 215
 216 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66)
 217 struct alpha_machine_vector eb66_mv __initmv = {
 218         .vector_name            = "EB66",
 219         DO_EV4_MMU,
 220         DO_DEFAULT_RTC,
 221         DO_LCA_IO,
 222         .machine_check          = lca_machine_check,
 223         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 224         .min_io_address         = DEFAULT_IO_BASE,
 225         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 226
 227         .nr_irqs                = 32,
 228         .device_interrupt       = eb64p_device_interrupt,
 229
 230         .init_arch              = lca_init_arch,
 231         .init_irq               = eb64p_init_irq,
 232         .init_rtc               = common_init_rtc,
 233         .init_pci               = common_init_pci,
 234         .pci_map_irq            = eb64p_map_irq,
 235         .pci_swizzle            = common_swizzle,
 236 };
 237 ALIAS_MV(eb66)
 238 #endif