1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/alpha/kernel/sys_sx164.c
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999, 2000 Richard Henderson
9 * Code supporting the SX164 (PCA56+PYXIS).
12 #include <linux/kernel.h>
13 #include <linux/types.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/bitops.h>
20 #include <asm/ptrace.h>
23 #include <asm/mmu_context.h>
25 #include <asm/core_cia.h>
26 #include <asm/hwrpb.h>
27 #include <asm/tlbflush.h>
28 #include <asm/special_insns.h>
33 #include "machvec_impl.h"
39 outb(0, DMA1_RESET_REG
);
40 outb(0, DMA2_RESET_REG
);
41 outb(DMA_MODE_CASCADE
, DMA2_MODE_REG
);
42 outb(0, DMA2_MASK_REG
);
45 alpha_mv
.device_interrupt
= srm_device_interrupt
;
49 /* Not interested in the bogus interrupts (0,3,4,5,40-47),
50 NMI (1), or HALT (2). */
52 init_srm_irqs(40, 0x3f0000);
54 init_pyxis_irqs(0xff00003f0000UL
);
56 if (request_irq(16 + 6, no_action
, 0, "timer-cascade", NULL
))
57 pr_err("Failed to register timer-cascade interrupt\n");
61 * PCI Fixup configuration.
63 * Summary @ PYXIS_INT_REQ:
71 * 6 Interval timer (RTC)
73 * 8 Interrupt Line A from slot 3
74 * 9 Interrupt Line A from slot 2
75 *10 Interrupt Line A from slot 1
76 *11 Interrupt Line A from slot 0
77 *12 Interrupt Line B from slot 3
78 *13 Interrupt Line B from slot 2
79 *14 Interrupt Line B from slot 1
80 *15 Interrupt line B from slot 0
81 *16 Interrupt Line C from slot 3
82 *17 Interrupt Line C from slot 2
83 *18 Interrupt Line C from slot 1
84 *19 Interrupt Line C from slot 0
85 *20 Interrupt Line D from slot 3
86 *21 Interrupt Line D from slot 2
87 *22 Interrupt Line D from slot 1
88 *23 Interrupt Line D from slot 0
91 * 5 32 bit PCI option slot 2
92 * 6 64 bit PCI option slot 0
93 * 7 64 bit PCI option slot 1
95 * 9 32 bit PCI option slot 3
99 sx164_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
101 static char irq_tab
[5][5] = {
102 /*INT INTA INTB INTC INTD */
103 { 16+ 9, 16+ 9, 16+13, 16+17, 16+21}, /* IdSel 5 slot 2 J17 */
104 { 16+11, 16+11, 16+15, 16+19, 16+23}, /* IdSel 6 slot 0 J19 */
105 { 16+10, 16+10, 16+14, 16+18, 16+22}, /* IdSel 7 slot 1 J18 */
106 { -1, -1, -1, -1, -1}, /* IdSel 8 SIO */
107 { 16+ 8, 16+ 8, 16+12, 16+16, 16+20} /* IdSel 9 slot 3 J15 */
109 const long min_idsel
= 5, max_idsel
= 9, irqs_per_slot
= 5;
110 return COMMON_TABLE_LOOKUP
;
121 sx164_init_arch(void)
124 * OSF palcode v1.23 forgets to enable PCA56 Motion Video
125 * Instructions. Let's enable it.
126 * We have to check palcode revision because CSERVE interface
127 * is subject to change without notice. For example, it
128 * has been changed completely since v1.16 (found in MILO
129 * distribution). -ink
131 struct percpu_struct
*cpu
= (struct percpu_struct
*)
132 ((char*)hwrpb
+ hwrpb
->processor_offset
);
134 if (amask(AMASK_MAX
) != 0
136 && (cpu
->pal_revision
& 0xffff) <= 0x117) {
137 __asm__
__volatile__(
139 "call_pal 9\n" /* Allow PALRES insns in kernel mode */
140 ".long 0x64000118\n\n" /* hw_mfpr $0,icsr */
141 "ldah $16,(1<<(19-16))($31)\n"
142 "or $0,$16,$0\n" /* set MVE bit */
143 ".long 0x74000118\n" /* hw_mtpr $0,icsr */
145 "call_pal 9" /* Disable PALRES insns */
147 printk("PCA56 MVI set enabled\n");
157 struct alpha_machine_vector sx164_mv __initmv
= {
158 .vector_name
= "SX164",
162 .machine_check
= cia_machine_check
,
163 .max_isa_dma_address
= ALPHA_MAX_ISA_DMA_ADDRESS
,
164 .min_io_address
= DEFAULT_IO_BASE
,
165 .min_mem_address
= DEFAULT_MEM_BASE
,
166 .pci_dac_offset
= PYXIS_DAC_OFFSET
,
169 .device_interrupt
= pyxis_device_interrupt
,
171 .init_arch
= sx164_init_arch
,
172 .init_irq
= sx164_init_irq
,
173 .init_rtc
= common_init_rtc
,
174 .init_pci
= sx164_init_pci
,
175 .kill_arch
= cia_kill_arch
,
176 .pci_map_irq
= sx164_map_irq
,
177 .pci_swizzle
= common_swizzle
,