arch/arm/include/asm/hardware/cache-l2x0.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/include/asm/hardware/cache-l2x0.h
   4  *
   5  * Copyright (C) 2007 ARM Limited
   6  */
   7
   8 #ifndef __ASM_ARM_HARDWARE_L2X0_H
   9 #define __ASM_ARM_HARDWARE_L2X0_H
  10
  11 #include <linux/errno.h>
  12
  13 #define L2X0_CACHE_ID                   0x000
  14 #define L2X0_CACHE_TYPE                 0x004
  15 #define L2X0_CTRL                       0x100
  16 #define L2X0_AUX_CTRL                   0x104
  17 #define L310_TAG_LATENCY_CTRL           0x108
  18 #define L310_DATA_LATENCY_CTRL          0x10C
  19 #define L2X0_EVENT_CNT_CTRL             0x200
  20 #define L2X0_EVENT_CNT1_CFG             0x204
  21 #define L2X0_EVENT_CNT0_CFG             0x208
  22 #define L2X0_EVENT_CNT1_VAL             0x20C
  23 #define L2X0_EVENT_CNT0_VAL             0x210
  24 #define L2X0_INTR_MASK                  0x214
  25 #define L2X0_MASKED_INTR_STAT           0x218
  26 #define L2X0_RAW_INTR_STAT              0x21C
  27 #define L2X0_INTR_CLEAR                 0x220
  28 #define L2X0_CACHE_SYNC                 0x730
  29 #define L2X0_DUMMY_REG                  0x740
  30 #define L2X0_INV_LINE_PA                0x770
  31 #define L2X0_INV_WAY                    0x77C
  32 #define L2X0_CLEAN_LINE_PA              0x7B0
  33 #define L2X0_CLEAN_LINE_IDX             0x7B8
  34 #define L2X0_CLEAN_WAY                  0x7BC
  35 #define L2X0_CLEAN_INV_LINE_PA          0x7F0
  36 #define L2X0_CLEAN_INV_LINE_IDX         0x7F8
  37 #define L2X0_CLEAN_INV_WAY              0x7FC
  38 /*
  39  * The lockdown registers repeat 8 times for L310, the L210 has only one
  40  * D and one I lockdown register at 0x0900 and 0x0904.
  41  */
  42 #define L2X0_LOCKDOWN_WAY_D_BASE        0x900
  43 #define L2X0_LOCKDOWN_WAY_I_BASE        0x904
  44 #define L2X0_LOCKDOWN_STRIDE            0x08
  45 #define L310_ADDR_FILTER_START          0xC00
  46 #define L310_ADDR_FILTER_END            0xC04
  47 #define L2X0_TEST_OPERATION             0xF00
  48 #define L2X0_LINE_DATA                  0xF10
  49 #define L2X0_LINE_TAG                   0xF30
  50 #define L2X0_DEBUG_CTRL                 0xF40
  51 #define L310_PREFETCH_CTRL              0xF60
  52 #define L310_POWER_CTRL                 0xF80
  53 #define   L310_DYNAMIC_CLK_GATING_EN    (1 << 1)
  54 #define   L310_STNDBY_MODE_EN           (1 << 0)
  55
  56 /* Registers shifts and masks */
  57 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
  58 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
  59 #define L2X0_CACHE_ID_PART_L220         (2 << 6)
  60 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
  61 #define L2X0_CACHE_ID_RTL_MASK          0x3f
  62 #define L210_CACHE_ID_RTL_R0P2_02       0x00
  63 #define L210_CACHE_ID_RTL_R0P1          0x01
  64 #define L210_CACHE_ID_RTL_R0P2_01       0x02
  65 #define L210_CACHE_ID_RTL_R0P3          0x03
  66 #define L210_CACHE_ID_RTL_R0P4          0x0b
  67 #define L210_CACHE_ID_RTL_R0P5          0x0f
  68 #define L220_CACHE_ID_RTL_R1P7_01REL0   0x06
  69 #define L310_CACHE_ID_RTL_R0P0          0x00
  70 #define L310_CACHE_ID_RTL_R1P0          0x02
  71 #define L310_CACHE_ID_RTL_R2P0          0x04
  72 #define L310_CACHE_ID_RTL_R3P0          0x05
  73 #define L310_CACHE_ID_RTL_R3P1          0x06
  74 #define L310_CACHE_ID_RTL_R3P1_50REL0   0x07
  75 #define L310_CACHE_ID_RTL_R3P2          0x08
  76 #define L310_CACHE_ID_RTL_R3P3          0x09
  77
  78 #define L2X0_EVENT_CNT_CTRL_ENABLE      BIT(0)
  79
  80 #define L2X0_EVENT_CNT_CFG_SRC_SHIFT    2
  81 #define L2X0_EVENT_CNT_CFG_SRC_MASK     0xf
  82 #define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
  83 #define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
  84 #define L2X0_EVENT_CNT_CFG_INT_INCR     1
  85 #define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2
  86
  87 /* L2C auxiliary control register - bits common to L2C-210/220/310 */
  88 #define L2C_AUX_CTRL_WAY_SIZE_SHIFT             17
  89 #define L2C_AUX_CTRL_WAY_SIZE_MASK              (7 << 17)
  90 #define L2C_AUX_CTRL_WAY_SIZE(n)                ((n) << 17)
  91 #define L2C_AUX_CTRL_EVTMON_ENABLE              BIT(20)
  92 #define L2C_AUX_CTRL_PARITY_ENABLE              BIT(21)
  93 #define L2C_AUX_CTRL_SHARED_OVERRIDE            BIT(22)
  94 /* L2C-210/220 common bits */
  95 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT     0
  96 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      (7 << 0)
  97 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT     3
  98 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (7 << 3)
  99 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT         6
 100 #define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (7 << 6)
 101 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT       9
 102 #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (7 << 9)
 103 #define L2X0_AUX_CTRL_ASSOC_SHIFT               13
 104 #define L2X0_AUX_CTRL_ASSOC_MASK                (15 << 13)
 105 /* L2C-210 specific bits */
 106 #define L210_AUX_CTRL_WRAP_DISABLE              BIT(12)
 107 #define L210_AUX_CTRL_WA_OVERRIDE               BIT(23)
 108 #define L210_AUX_CTRL_EXCLUSIVE_ABORT           BIT(24)
 109 /* L2C-220 specific bits */
 110 #define L220_AUX_CTRL_EXCLUSIVE_CACHE           BIT(12)
 111 #define L220_AUX_CTRL_FWA_SHIFT                 23
 112 #define L220_AUX_CTRL_FWA_MASK                  (3 << 23)
 113 #define L220_AUX_CTRL_NS_LOCKDOWN               BIT(26)
 114 #define L220_AUX_CTRL_NS_INT_CTRL               BIT(27)
 115 /* L2C-310 specific bits */
 116 #define L310_AUX_CTRL_FULL_LINE_ZERO            BIT(0)  /* R2P0+ */
 117 #define L310_AUX_CTRL_HIGHPRIO_SO_DEV           BIT(10) /* R2P0+ */
 118 #define L310_AUX_CTRL_STORE_LIMITATION          BIT(11) /* R2P0+ */
 119 #define L310_AUX_CTRL_EXCLUSIVE_CACHE           BIT(12)
 120 #define L310_AUX_CTRL_ASSOCIATIVITY_16          BIT(16)
 121 #define L310_AUX_CTRL_FWA_SHIFT                 23
 122 #define L310_AUX_CTRL_FWA_MASK                  (3 << 23)
 123 #define L310_AUX_CTRL_CACHE_REPLACE_RR          BIT(25) /* R2P0+ */
 124 #define L310_AUX_CTRL_NS_LOCKDOWN               BIT(26)
 125 #define L310_AUX_CTRL_NS_INT_CTRL               BIT(27)
 126 #define L310_AUX_CTRL_DATA_PREFETCH             BIT(28)
 127 #define L310_AUX_CTRL_INSTR_PREFETCH            BIT(29)
 128 #define L310_AUX_CTRL_EARLY_BRESP               BIT(30) /* R2P0+ */
 129
 130 #define L310_LATENCY_CTRL_SETUP(n)              ((n) << 0)
 131 #define L310_LATENCY_CTRL_RD(n)                 ((n) << 4)
 132 #define L310_LATENCY_CTRL_WR(n)                 ((n) << 8)
 133
 134 #define L310_ADDR_FILTER_EN             1
 135
 136 #define L310_PREFETCH_CTRL_OFFSET_MASK          0x1f
 137 #define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR    BIT(23)
 138 #define L310_PREFETCH_CTRL_PREFETCH_DROP        BIT(24)
 139 #define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP    BIT(27)
 140 #define L310_PREFETCH_CTRL_DATA_PREFETCH        BIT(28)
 141 #define L310_PREFETCH_CTRL_INSTR_PREFETCH       BIT(29)
 142 #define L310_PREFETCH_CTRL_DBL_LINEFILL         BIT(30)
 143
 144 #define L2X0_CTRL_EN                    1
 145
 146 #define L2X0_WAY_SIZE_SHIFT             3
 147
 148 #ifndef __ASSEMBLY__
 149 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
 150 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
 151 extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
 152 #else
 153 static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
 154 {
 155         return -ENODEV;
 156 }
 157 #endif
 158
 159 #ifdef CONFIG_CACHE_L2X0_PMU
 160 void l2x0_pmu_register(void __iomem *base, u32 part);
 161 void l2x0_pmu_suspend(void);
 162 void l2x0_pmu_resume(void);
 163 #else
 164 static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
 165 static inline void l2x0_pmu_suspend(void) {}
 166 static inline void l2x0_pmu_resume(void) {}
 167 #endif
 168
 169 struct l2x0_regs {
 170         unsigned long phy_base;
 171         unsigned long aux_ctrl;
 172         /*
 173          * Whether the following registers need to be saved/restored
 174          * depends on platform
 175          */
 176         unsigned long tag_latency;
 177         unsigned long data_latency;
 178         unsigned long filter_start;
 179         unsigned long filter_end;
 180         unsigned long prefetch_ctrl;
 181         unsigned long pwr_ctrl;
 182         unsigned long ctrl;
 183         unsigned long aux2_ctrl;
 184 };
 185
 186 extern struct l2x0_regs l2x0_saved_regs;
 187
 188 #endif /* __ASSEMBLY__ */
 189
 190 #endif