1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SPINLOCK_H
3 #define __ASM_SPINLOCK_H
5 #if __LINUX_ARM_ARCH__ < 6
6 #error SMP not supported on pre-ARMv6 CPUs
9 #include <linux/prefetch.h>
10 #include <asm/barrier.h>
11 #include <asm/processor.h>
14 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
15 * extensions, so when running on UP, we have to patch these instructions away.
17 #ifdef CONFIG_THUMB2_KERNEL
19 * For Thumb-2, special care is needed to ensure that the conditional WFE
20 * instruction really does assemble to exactly 4 bytes (as required by
21 * the SMP_ON_UP fixup code). By itself "wfene" might cause the
22 * assembler to insert a extra (16-bit) IT instruction, depending on the
23 * presence or absence of neighbouring conditional instructions.
25 * To avoid this unpredictableness, an approprite IT is inserted explicitly:
26 * the assembler won't change IT instructions which are explicitly present
29 #define WFE(cond) __ALT_SMP_ASM( \
36 #define WFE(cond) __ALT_SMP_ASM("wfe" cond, "nop")
39 #define SEV __ALT_SMP_ASM(WASM(sev), WASM(nop))
41 static inline void dsb_sev(void)
49 * ARMv6 ticket-based spin-locking.
51 * A memory barrier is required after we get a lock, and before we
52 * release it, because V6 CPUs are assumed to have weakly ordered
56 static inline void arch_spin_lock(arch_spinlock_t
*lock
)
60 arch_spinlock_t lockval
;
62 prefetchw(&lock
->slock
);
66 " strex %2, %1, [%3]\n"
69 : "=&r" (lockval
), "=&r" (newval
), "=&r" (tmp
)
70 : "r" (&lock
->slock
), "I" (1 << TICKET_SHIFT
)
73 while (lockval
.tickets
.next
!= lockval
.tickets
.owner
) {
75 lockval
.tickets
.owner
= READ_ONCE(lock
->tickets
.owner
);
81 static inline int arch_spin_trylock(arch_spinlock_t
*lock
)
83 unsigned long contended
, res
;
86 prefetchw(&lock
->slock
);
91 " subs %1, %0, %0, ror #16\n"
93 " strexeq %2, %0, [%3]"
94 : "=&r" (slock
), "=&r" (contended
), "=&r" (res
)
95 : "r" (&lock
->slock
), "I" (1 << TICKET_SHIFT
)
107 static inline void arch_spin_unlock(arch_spinlock_t
*lock
)
110 lock
->tickets
.owner
++;
114 static inline int arch_spin_value_unlocked(arch_spinlock_t lock
)
116 return lock
.tickets
.owner
== lock
.tickets
.next
;
119 static inline int arch_spin_is_locked(arch_spinlock_t
*lock
)
121 return !arch_spin_value_unlocked(READ_ONCE(*lock
));
124 static inline int arch_spin_is_contended(arch_spinlock_t
*lock
)
126 struct __raw_tickets tickets
= READ_ONCE(lock
->tickets
);
127 return (tickets
.next
- tickets
.owner
) > 1;
129 #define arch_spin_is_contended arch_spin_is_contended
135 * Write locks are easy - we just set bit 31. When unlocking, we can
136 * just write zero since the lock is exclusively held.
139 static inline void arch_write_lock(arch_rwlock_t
*rw
)
143 prefetchw(&rw
->lock
);
144 __asm__
__volatile__(
145 "1: ldrex %0, [%1]\n"
148 " strexeq %0, %2, [%1]\n"
152 : "r" (&rw
->lock
), "r" (0x80000000)
158 static inline int arch_write_trylock(arch_rwlock_t
*rw
)
160 unsigned long contended
, res
;
162 prefetchw(&rw
->lock
);
164 __asm__
__volatile__(
168 " strexeq %1, %3, [%2]"
169 : "=&r" (contended
), "=&r" (res
)
170 : "r" (&rw
->lock
), "r" (0x80000000)
182 static inline void arch_write_unlock(arch_rwlock_t
*rw
)
186 __asm__
__volatile__(
189 : "r" (&rw
->lock
), "r" (0)
196 * Read locks are a bit more hairy:
197 * - Exclusively load the lock value.
199 * - Store new lock value if positive, and we still own this location.
200 * If the value is negative, we've already failed.
201 * - If we failed to store the value, we want a negative result.
202 * - If we failed, try again.
203 * Unlocking is similarly hairy. We may have multiple read locks
204 * currently active. However, we know we won't have any write
207 static inline void arch_read_lock(arch_rwlock_t
*rw
)
209 unsigned long tmp
, tmp2
;
211 prefetchw(&rw
->lock
);
212 __asm__
__volatile__(
214 "1: ldrex %0, [%2]\n"
216 " strexpl %1, %0, [%2]\n"
218 " rsbspl %0, %1, #0\n"
220 : "=&r" (tmp
), "=&r" (tmp2
)
227 static inline void arch_read_unlock(arch_rwlock_t
*rw
)
229 unsigned long tmp
, tmp2
;
233 prefetchw(&rw
->lock
);
234 __asm__
__volatile__(
235 "1: ldrex %0, [%2]\n"
237 " strex %1, %0, [%2]\n"
240 : "=&r" (tmp
), "=&r" (tmp2
)
248 static inline int arch_read_trylock(arch_rwlock_t
*rw
)
250 unsigned long contended
, res
;
252 prefetchw(&rw
->lock
);
254 __asm__
__volatile__(
258 " strexpl %1, %0, [%2]"
259 : "=&r" (contended
), "=&r" (res
)
264 /* If the lock is negative, then it is already held for write. */
265 if (contended
< 0x80000000) {
273 #endif /* __ASM_SPINLOCK_H */