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Merge tag 'sched-urgent-2020-12-27' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / arch / arm / mach-s3c / irq-s3c24xx.c
blob79b5f19af7a52a20b9c33b236522e045a7d2961f
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * S3C24XX IRQ handling
4 *
5 * Copyright (c) 2003-2004 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
8 */
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/device.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irqchip.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24
25 #include <asm/exception.h>
26 #include <asm/mach/irq.h>
27
28 #include <mach/irqs.h>
29 #include "regs-irq.h"
30 #include "regs-gpio.h"
31
32 #include "cpu.h"
33 #include "regs-irqtype.h"
34 #include "pm.h"
35
36 #define S3C_IRQTYPE_NONE 0
37 #define S3C_IRQTYPE_EINT 1
38 #define S3C_IRQTYPE_EDGE 2
39 #define S3C_IRQTYPE_LEVEL 3
40
41 struct s3c_irq_data {
42 unsigned int type;
43 unsigned long offset;
44 unsigned long parent_irq;
45
46 /* data gets filled during init */
47 struct s3c_irq_intc *intc;
48 unsigned long sub_bits;
49 struct s3c_irq_intc *sub_intc;
50 };
51
52 /*
53 * Structure holding the controller data
54 * @reg_pending register holding pending irqs
55 * @reg_intpnd special register intpnd in main intc
56 * @reg_mask mask register
57 * @domain irq_domain of the controller
58 * @parent parent controller for ext and sub irqs
59 * @irqs irq-data, always s3c_irq_data[32]
60 */
61 struct s3c_irq_intc {
62 void __iomem *reg_pending;
63 void __iomem *reg_intpnd;
64 void __iomem *reg_mask;
65 struct irq_domain *domain;
66 struct s3c_irq_intc *parent;
67 struct s3c_irq_data *irqs;
68 };
69
70 /*
71 * Array holding pointers to the global controller structs
72 * [0] ... main_intc
73 * [1] ... sub_intc
74 * [2] ... main_intc2 on s3c2416
75 */
76 static struct s3c_irq_intc *s3c_intc[3];
77
78 static void s3c_irq_mask(struct irq_data *data)
79 {
80 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
81 struct s3c_irq_intc *intc = irq_data->intc;
82 struct s3c_irq_intc *parent_intc = intc->parent;
83 struct s3c_irq_data *parent_data;
84 unsigned long mask;
85 unsigned int irqno;
86
87 mask = readl_relaxed(intc->reg_mask);
88 mask |= (1UL << irq_data->offset);
89 writel_relaxed(mask, intc->reg_mask);
90
91 if (parent_intc) {
92 parent_data = &parent_intc->irqs[irq_data->parent_irq];
93
94 /* check to see if we need to mask the parent IRQ
95 * The parent_irq is always in main_intc, so the hwirq
96 * for find_mapping does not need an offset in any case.
97 */
98 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
99 irqno = irq_find_mapping(parent_intc->domain,
100 irq_data->parent_irq);
101 s3c_irq_mask(irq_get_irq_data(irqno));
102 }
103 }
104 }
105
106 static void s3c_irq_unmask(struct irq_data *data)
107 {
108 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
109 struct s3c_irq_intc *intc = irq_data->intc;
110 struct s3c_irq_intc *parent_intc = intc->parent;
111 unsigned long mask;
112 unsigned int irqno;
113
114 mask = readl_relaxed(intc->reg_mask);
115 mask &= ~(1UL << irq_data->offset);
116 writel_relaxed(mask, intc->reg_mask);
117
118 if (parent_intc) {
119 irqno = irq_find_mapping(parent_intc->domain,
120 irq_data->parent_irq);
121 s3c_irq_unmask(irq_get_irq_data(irqno));
122 }
123 }
124
125 static inline void s3c_irq_ack(struct irq_data *data)
126 {
127 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
128 struct s3c_irq_intc *intc = irq_data->intc;
129 unsigned long bitval = 1UL << irq_data->offset;
130
131 writel_relaxed(bitval, intc->reg_pending);
132 if (intc->reg_intpnd)
133 writel_relaxed(bitval, intc->reg_intpnd);
134 }
135
136 static int s3c_irq_type(struct irq_data *data, unsigned int type)
137 {
138 switch (type) {
139 case IRQ_TYPE_NONE:
140 break;
141 case IRQ_TYPE_EDGE_RISING:
142 case IRQ_TYPE_EDGE_FALLING:
143 case IRQ_TYPE_EDGE_BOTH:
144 irq_set_handler(data->irq, handle_edge_irq);
145 break;
146 case IRQ_TYPE_LEVEL_LOW:
147 case IRQ_TYPE_LEVEL_HIGH:
148 irq_set_handler(data->irq, handle_level_irq);
149 break;
150 default:
151 pr_err("No such irq type %d\n", type);
152 return -EINVAL;
153 }
154
155 return 0;
156 }
157
158 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
159 void __iomem *extint_reg,
160 unsigned long gpcon_offset,
161 unsigned long extint_offset,
162 unsigned int type)
163 {
164 unsigned long newvalue = 0, value;
165
166 /* Set the GPIO to external interrupt mode */
167 value = readl_relaxed(gpcon_reg);
168 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
169 writel_relaxed(value, gpcon_reg);
170
171 /* Set the external interrupt to pointed trigger type */
172 switch (type)
173 {
174 case IRQ_TYPE_NONE:
175 pr_warn("No edge setting!\n");
176 break;
177
178 case IRQ_TYPE_EDGE_RISING:
179 newvalue = S3C2410_EXTINT_RISEEDGE;
180 break;
181
182 case IRQ_TYPE_EDGE_FALLING:
183 newvalue = S3C2410_EXTINT_FALLEDGE;
184 break;
185
186 case IRQ_TYPE_EDGE_BOTH:
187 newvalue = S3C2410_EXTINT_BOTHEDGE;
188 break;
189
190 case IRQ_TYPE_LEVEL_LOW:
191 newvalue = S3C2410_EXTINT_LOWLEV;
192 break;
193
194 case IRQ_TYPE_LEVEL_HIGH:
195 newvalue = S3C2410_EXTINT_HILEV;
196 break;
197
198 default:
199 pr_err("No such irq type %d\n", type);
200 return -EINVAL;
201 }
202
203 value = readl_relaxed(extint_reg);
204 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
205 writel_relaxed(value, extint_reg);
206
207 return 0;
208 }
209
210 static int s3c_irqext_type(struct irq_data *data, unsigned int type)
211 {
212 void __iomem *extint_reg;
213 void __iomem *gpcon_reg;
214 unsigned long gpcon_offset, extint_offset;
215
216 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
217 gpcon_reg = S3C2410_GPFCON;
218 extint_reg = S3C24XX_EXTINT0;
219 gpcon_offset = (data->hwirq) * 2;
220 extint_offset = (data->hwirq) * 4;
221 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
222 gpcon_reg = S3C2410_GPGCON;
223 extint_reg = S3C24XX_EXTINT1;
224 gpcon_offset = (data->hwirq - 8) * 2;
225 extint_offset = (data->hwirq - 8) * 4;
226 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
227 gpcon_reg = S3C2410_GPGCON;
228 extint_reg = S3C24XX_EXTINT2;
229 gpcon_offset = (data->hwirq - 8) * 2;
230 extint_offset = (data->hwirq - 16) * 4;
231 } else {
232 return -EINVAL;
233 }
234
235 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
236 extint_offset, type);
237 }
238
239 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
240 {
241 void __iomem *extint_reg;
242 void __iomem *gpcon_reg;
243 unsigned long gpcon_offset, extint_offset;
244
245 if (data->hwirq <= 3) {
246 gpcon_reg = S3C2410_GPFCON;
247 extint_reg = S3C24XX_EXTINT0;
248 gpcon_offset = (data->hwirq) * 2;
249 extint_offset = (data->hwirq) * 4;
250 } else {
251 return -EINVAL;
252 }
253
254 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
255 extint_offset, type);
256 }
257
258 static struct irq_chip s3c_irq_chip = {
259 .name = "s3c",
260 .irq_ack = s3c_irq_ack,
261 .irq_mask = s3c_irq_mask,
262 .irq_unmask = s3c_irq_unmask,
263 .irq_set_type = s3c_irq_type,
264 .irq_set_wake = s3c_irq_wake
265 };
266
267 static struct irq_chip s3c_irq_level_chip = {
268 .name = "s3c-level",
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
271 .irq_ack = s3c_irq_ack,
272 .irq_set_type = s3c_irq_type,
273 };
274
275 static struct irq_chip s3c_irqext_chip = {
276 .name = "s3c-ext",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
280 .irq_set_type = s3c_irqext_type,
281 .irq_set_wake = s3c_irqext_wake
282 };
283
284 static struct irq_chip s3c_irq_eint0t4 = {
285 .name = "s3c-ext0",
286 .irq_ack = s3c_irq_ack,
287 .irq_mask = s3c_irq_mask,
288 .irq_unmask = s3c_irq_unmask,
289 .irq_set_wake = s3c_irq_wake,
290 .irq_set_type = s3c_irqext0_type,
291 };
292
293 static void s3c_irq_demux(struct irq_desc *desc)
294 {
295 struct irq_chip *chip = irq_desc_get_chip(desc);
296 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
297 struct s3c_irq_intc *intc = irq_data->intc;
298 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
299 unsigned int n, offset, irq;
300 unsigned long src, msk;
301
302 /* we're using individual domains for the non-dt case
303 * and one big domain for the dt case where the subintc
304 * starts at hwirq number 32.
305 */
306 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
307
308 chained_irq_enter(chip, desc);
309
310 src = readl_relaxed(sub_intc->reg_pending);
311 msk = readl_relaxed(sub_intc->reg_mask);
312
313 src &= ~msk;
314 src &= irq_data->sub_bits;
315
316 while (src) {
317 n = __ffs(src);
318 src &= ~(1 << n);
319 irq = irq_find_mapping(sub_intc->domain, offset + n);
320 generic_handle_irq(irq);
321 }
322
323 chained_irq_exit(chip, desc);
324 }
325
326 static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
327 struct pt_regs *regs, int intc_offset)
328 {
329 int pnd;
330 int offset;
331
332 pnd = readl_relaxed(intc->reg_intpnd);
333 if (!pnd)
334 return false;
335
336 /* non-dt machines use individual domains */
337 if (!irq_domain_get_of_node(intc->domain))
338 intc_offset = 0;
339
340 /* We have a problem that the INTOFFSET register does not always
341 * show one interrupt. Occasionally we get two interrupts through
342 * the prioritiser, and this causes the INTOFFSET register to show
343 * what looks like the logical-or of the two interrupt numbers.
344 *
345 * Thanks to Klaus, Shannon, et al for helping to debug this problem
346 */
347 offset = readl_relaxed(intc->reg_intpnd + 4);
348
349 /* Find the bit manually, when the offset is wrong.
350 * The pending register only ever contains the one bit of the next
351 * interrupt to handle.
352 */
353 if (!(pnd & (1 << offset)))
354 offset = __ffs(pnd);
355
356 handle_domain_irq(intc->domain, intc_offset + offset, regs);
357 return true;
358 }
359
360 asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
361 {
362 do {
363 if (likely(s3c_intc[0]))
364 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
365 continue;
366
367 if (s3c_intc[2])
368 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
369 continue;
370
371 break;
372 } while (1);
373 }
374
375 #ifdef CONFIG_FIQ
376 /**
377 * s3c24xx_set_fiq - set the FIQ routing
378 * @irq: IRQ number to route to FIQ on processor.
379 * @ack_ptr: pointer to a location for storing the bit mask
380 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
381 *
382 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
383 * @on is true, the @irq is checked to see if it can be routed and the
384 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
385 * routing is cleared, regardless of which @irq is specified.
386 *
387 * returns the mask value for the register.
388 */
389 int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on)
390 {
391 u32 intmod;
392 unsigned offs;
393
394 if (on) {
395 offs = irq - FIQ_START;
396 if (offs > 31)
397 return 0;
398
399 intmod = 1 << offs;
400 } else {
401 intmod = 0;
402 }
403
404 if (ack_ptr)
405 *ack_ptr = intmod;
406 writel_relaxed(intmod, S3C2410_INTMOD);
407
408 return intmod;
409 }
410
411 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
412 #endif
413
414 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
415 irq_hw_number_t hw)
416 {
417 struct s3c_irq_intc *intc = h->host_data;
418 struct s3c_irq_data *irq_data = &intc->irqs[hw];
419 struct s3c_irq_intc *parent_intc;
420 struct s3c_irq_data *parent_irq_data;
421 unsigned int irqno;
422
423 /* attach controller pointer to irq_data */
424 irq_data->intc = intc;
425 irq_data->offset = hw;
426
427 parent_intc = intc->parent;
428
429 /* set handler and flags */
430 switch (irq_data->type) {
431 case S3C_IRQTYPE_NONE:
432 return 0;
433 case S3C_IRQTYPE_EINT:
434 /* On the S3C2412, the EINT0to3 have a parent irq
435 * but need the s3c_irq_eint0t4 chip
436 */
437 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
438 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
439 handle_edge_irq);
440 else
441 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
442 handle_edge_irq);
443 break;
444 case S3C_IRQTYPE_EDGE:
445 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
446 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
447 handle_edge_irq);
448 else
449 irq_set_chip_and_handler(virq, &s3c_irq_chip,
450 handle_edge_irq);
451 break;
452 case S3C_IRQTYPE_LEVEL:
453 if (parent_intc)
454 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
455 handle_level_irq);
456 else
457 irq_set_chip_and_handler(virq, &s3c_irq_chip,
458 handle_level_irq);
459 break;
460 default:
461 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
462 return -EINVAL;
463 }
464
465 irq_set_chip_data(virq, irq_data);
466
467 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
468 if (irq_data->parent_irq > 31) {
469 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
470 irq_data->parent_irq);
471 return -EINVAL;
472 }
473
474 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
475 parent_irq_data->sub_intc = intc;
476 parent_irq_data->sub_bits |= (1UL << hw);
477
478 /* attach the demuxer to the parent irq */
479 irqno = irq_find_mapping(parent_intc->domain,
480 irq_data->parent_irq);
481 if (!irqno) {
482 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
483 irq_data->parent_irq);
484 return -EINVAL;
485 }
486 irq_set_chained_handler(irqno, s3c_irq_demux);
487 }
488
489 return 0;
490 }
491
492 static const struct irq_domain_ops s3c24xx_irq_ops = {
493 .map = s3c24xx_irq_map,
494 .xlate = irq_domain_xlate_twocell,
495 };
496
497 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
498 {
499 void __iomem *reg_source;
500 unsigned long pend;
501 unsigned long last;
502 int i;
503
504 /* if intpnd is set, read the next pending irq from there */
505 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
506
507 last = 0;
508 for (i = 0; i < 4; i++) {
509 pend = readl_relaxed(reg_source);
510
511 if (pend == 0 || pend == last)
512 break;
513
514 writel_relaxed(pend, intc->reg_pending);
515 if (intc->reg_intpnd)
516 writel_relaxed(pend, intc->reg_intpnd);
517
518 pr_info("irq: clearing pending status %08x\n", (int)pend);
519 last = pend;
520 }
521 }
522
523 static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
524 struct s3c_irq_data *irq_data,
525 struct s3c_irq_intc *parent,
526 unsigned long address)
527 {
528 struct s3c_irq_intc *intc;
529 void __iomem *base = (void *)0xf6000000; /* static mapping */
530 int irq_num;
531 int irq_start;
532 int ret;
533
534 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
535 if (!intc)
536 return ERR_PTR(-ENOMEM);
537
538 intc->irqs = irq_data;
539
540 if (parent)
541 intc->parent = parent;
542
543 /* select the correct data for the controller.
544 * Need to hard code the irq num start and offset
545 * to preserve the static mapping for now
546 */
547 switch (address) {
548 case 0x4a000000:
549 pr_debug("irq: found main intc\n");
550 intc->reg_pending = base;
551 intc->reg_mask = base + 0x08;
552 intc->reg_intpnd = base + 0x10;
553 irq_num = 32;
554 irq_start = S3C2410_IRQ(0);
555 break;
556 case 0x4a000018:
557 pr_debug("irq: found subintc\n");
558 intc->reg_pending = base + 0x18;
559 intc->reg_mask = base + 0x1c;
560 irq_num = 29;
561 irq_start = S3C2410_IRQSUB(0);
562 break;
563 case 0x4a000040:
564 pr_debug("irq: found intc2\n");
565 intc->reg_pending = base + 0x40;
566 intc->reg_mask = base + 0x48;
567 intc->reg_intpnd = base + 0x50;
568 irq_num = 8;
569 irq_start = S3C2416_IRQ(0);
570 break;
571 case 0x560000a4:
572 pr_debug("irq: found eintc\n");
573 base = (void *)0xfd000000;
574
575 intc->reg_mask = base + 0xa4;
576 intc->reg_pending = base + 0xa8;
577 irq_num = 24;
578 irq_start = S3C2410_IRQ(32);
579 break;
580 default:
581 pr_err("irq: unsupported controller address\n");
582 ret = -EINVAL;
583 goto err;
584 }
585
586 /* now that all the data is complete, init the irq-domain */
587 s3c24xx_clear_intc(intc);
588 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
589 0, &s3c24xx_irq_ops,
590 intc);
591 if (!intc->domain) {
592 pr_err("irq: could not create irq-domain\n");
593 ret = -EINVAL;
594 goto err;
595 }
596
597 set_handle_irq(s3c24xx_handle_irq);
598
599 return intc;
600
601 err:
602 kfree(intc);
603 return ERR_PTR(ret);
604 }
605
606 static struct s3c_irq_data __maybe_unused init_eint[32] = {
607 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
608 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
611 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
631 };
632
633 #ifdef CONFIG_CPU_S3C2410
634 static struct s3c_irq_data init_s3c2410base[32] = {
635 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
636 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
637 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
638 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
639 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
640 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
641 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
642 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
643 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
644 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
649 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
651 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
652 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
657 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
658 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
659 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
660 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
661 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
662 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
663 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
664 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
665 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
666 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
667 };
668
669 static struct s3c_irq_data init_s3c2410subint[32] = {
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
679 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
680 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
681 };
682
683 void __init s3c2410_init_irq(void)
684 {
685 #ifdef CONFIG_FIQ
686 init_FIQ(FIQ_START);
687 #endif
688
689 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
690 0x4a000000);
691 if (IS_ERR(s3c_intc[0])) {
692 pr_err("irq: could not create main interrupt controller\n");
693 return;
694 }
695
696 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
697 s3c_intc[0], 0x4a000018);
698 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
699 }
700 #endif
701
702 #ifdef CONFIG_CPU_S3C2412
703 static struct s3c_irq_data init_s3c2412base[32] = {
704 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
705 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
706 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
708 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
709 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
710 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
711 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
712 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
713 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
714 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
715 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
716 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
718 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
719 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
720 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
721 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
723 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
724 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
725 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
726 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
727 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
728 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
729 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
730 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
731 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
732 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
733 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
734 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
735 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
736 };
737
738 static struct s3c_irq_data init_s3c2412eint[32] = {
739 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
763 };
764
765 static struct s3c_irq_data init_s3c2412subint[32] = {
766 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
775 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
776 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
777 { .type = S3C_IRQTYPE_NONE, },
778 { .type = S3C_IRQTYPE_NONE, },
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
781 };
782
783 void __init s3c2412_init_irq(void)
784 {
785 pr_info("S3C2412: IRQ Support\n");
786
787 #ifdef CONFIG_FIQ
788 init_FIQ(FIQ_START);
789 #endif
790
791 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
792 0x4a000000);
793 if (IS_ERR(s3c_intc[0])) {
794 pr_err("irq: could not create main interrupt controller\n");
795 return;
796 }
797
798 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
799 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
800 s3c_intc[0], 0x4a000018);
801 }
802 #endif
803
804 #ifdef CONFIG_CPU_S3C2416
805 static struct s3c_irq_data init_s3c2416base[32] = {
806 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
807 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
808 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
809 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
810 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
811 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
812 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
813 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
814 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
815 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
816 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
817 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
819 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
820 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
821 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
823 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
824 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
825 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
826 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
827 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
828 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
829 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
830 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
831 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
832 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
833 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
834 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
835 { .type = S3C_IRQTYPE_NONE, },
836 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
837 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
838 };
839
840 static struct s3c_irq_data init_s3c2416subint[32] = {
841 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
842 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
850 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
851 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
852 { .type = S3C_IRQTYPE_NONE }, /* reserved */
853 { .type = S3C_IRQTYPE_NONE }, /* reserved */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
870 };
871
872 static struct s3c_irq_data init_s3c2416_second[32] = {
873 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
874 { .type = S3C_IRQTYPE_NONE }, /* reserved */
875 { .type = S3C_IRQTYPE_NONE }, /* reserved */
876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
877 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
878 { .type = S3C_IRQTYPE_NONE }, /* reserved */
879 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
880 };
881
882 void __init s3c2416_init_irq(void)
883 {
884 pr_info("S3C2416: IRQ Support\n");
885
886 #ifdef CONFIG_FIQ
887 init_FIQ(FIQ_START);
888 #endif
889
890 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
891 0x4a000000);
892 if (IS_ERR(s3c_intc[0])) {
893 pr_err("irq: could not create main interrupt controller\n");
894 return;
895 }
896
897 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
898 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
899 s3c_intc[0], 0x4a000018);
900
901 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
902 NULL, 0x4a000040);
903 }
904
905 #endif
906
907 #ifdef CONFIG_CPU_S3C2440
908 static struct s3c_irq_data init_s3c2440base[32] = {
909 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
910 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
911 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
912 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
913 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
914 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
915 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
916 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
917 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
918 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
919 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
920 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
921 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
924 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
925 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
926 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
927 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
928 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
931 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
932 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
933 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
934 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
935 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
936 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
937 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
938 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
939 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
940 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
941 };
942
943 static struct s3c_irq_data init_s3c2440subint[32] = {
944 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
953 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
954 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
955 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
956 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
959 };
960
961 void __init s3c2440_init_irq(void)
962 {
963 pr_info("S3C2440: IRQ Support\n");
964
965 #ifdef CONFIG_FIQ
966 init_FIQ(FIQ_START);
967 #endif
968
969 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
970 0x4a000000);
971 if (IS_ERR(s3c_intc[0])) {
972 pr_err("irq: could not create main interrupt controller\n");
973 return;
974 }
975
976 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
977 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
978 s3c_intc[0], 0x4a000018);
979 }
980 #endif
981
982 #ifdef CONFIG_CPU_S3C2442
983 static struct s3c_irq_data init_s3c2442base[32] = {
984 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
985 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
986 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
987 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
988 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
989 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
990 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
991 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
992 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
993 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
994 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
995 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
996 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
998 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
999 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1000 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1007 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1008 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1009 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1012 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1014 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1015 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1016 };
1017
1018 static struct s3c_irq_data init_s3c2442subint[32] = {
1019 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1028 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1029 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1030 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1031 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1032 };
1033
1034 void __init s3c2442_init_irq(void)
1035 {
1036 pr_info("S3C2442: IRQ Support\n");
1037
1038 #ifdef CONFIG_FIQ
1039 init_FIQ(FIQ_START);
1040 #endif
1041
1042 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1043 0x4a000000);
1044 if (IS_ERR(s3c_intc[0])) {
1045 pr_err("irq: could not create main interrupt controller\n");
1046 return;
1047 }
1048
1049 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1050 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1051 s3c_intc[0], 0x4a000018);
1052 }
1053 #endif
1054
1055 #ifdef CONFIG_CPU_S3C2443
1056 static struct s3c_irq_data init_s3c2443base[32] = {
1057 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1058 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1059 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1060 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1061 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1062 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1063 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1064 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1065 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1066 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1067 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1068 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1072 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1074 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1075 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1076 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1077 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1080 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1081 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1082 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1085 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1087 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1088 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1089 };
1090
1091
1092 static struct s3c_irq_data init_s3c2443subint[32] = {
1093 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1102 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1103 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1106 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1122 };
1123
1124 void __init s3c2443_init_irq(void)
1125 {
1126 pr_info("S3C2443: IRQ Support\n");
1127
1128 #ifdef CONFIG_FIQ
1129 init_FIQ(FIQ_START);
1130 #endif
1131
1132 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1133 0x4a000000);
1134 if (IS_ERR(s3c_intc[0])) {
1135 pr_err("irq: could not create main interrupt controller\n");
1136 return;
1137 }
1138
1139 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1140 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1141 s3c_intc[0], 0x4a000018);
1142 }
1143 #endif
1144
1145 #ifdef CONFIG_OF
1146 static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1147 irq_hw_number_t hw)
1148 {
1149 unsigned int ctrl_num = hw / 32;
1150 unsigned int intc_hw = hw % 32;
1151 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1152 struct s3c_irq_intc *parent_intc = intc->parent;
1153 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1154
1155 /* attach controller pointer to irq_data */
1156 irq_data->intc = intc;
1157 irq_data->offset = intc_hw;
1158
1159 if (!parent_intc)
1160 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1161 else
1162 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1163 handle_edge_irq);
1164
1165 irq_set_chip_data(virq, irq_data);
1166
1167 return 0;
1168 }
1169
1170 /* Translate our of irq notation
1171 * format: <ctrl_num ctrl_irq parent_irq type>
1172 */
1173 static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1174 const u32 *intspec, unsigned int intsize,
1175 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1176 {
1177 struct s3c_irq_intc *intc;
1178 struct s3c_irq_intc *parent_intc;
1179 struct s3c_irq_data *irq_data;
1180 struct s3c_irq_data *parent_irq_data;
1181 int irqno;
1182
1183 if (WARN_ON(intsize < 4))
1184 return -EINVAL;
1185
1186 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1187 pr_err("controller number %d invalid\n", intspec[0]);
1188 return -EINVAL;
1189 }
1190 intc = s3c_intc[intspec[0]];
1191
1192 *out_hwirq = intspec[0] * 32 + intspec[2];
1193 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1194
1195 parent_intc = intc->parent;
1196 if (parent_intc) {
1197 irq_data = &intc->irqs[intspec[2]];
1198 irq_data->parent_irq = intspec[1];
1199 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1200 parent_irq_data->sub_intc = intc;
1201 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1202
1203 /* parent_intc is always s3c_intc[0], so no offset */
1204 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1205 if (irqno < 0) {
1206 pr_err("irq: could not map parent interrupt\n");
1207 return irqno;
1208 }
1209
1210 irq_set_chained_handler(irqno, s3c_irq_demux);
1211 }
1212
1213 return 0;
1214 }
1215
1216 static const struct irq_domain_ops s3c24xx_irq_ops_of = {
1217 .map = s3c24xx_irq_map_of,
1218 .xlate = s3c24xx_irq_xlate_of,
1219 };
1220
1221 struct s3c24xx_irq_of_ctrl {
1222 char *name;
1223 unsigned long offset;
1224 struct s3c_irq_intc **handle;
1225 struct s3c_irq_intc **parent;
1226 struct irq_domain_ops *ops;
1227 };
1228
1229 static int __init s3c_init_intc_of(struct device_node *np,
1230 struct device_node *interrupt_parent,
1231 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1232 {
1233 struct s3c_irq_intc *intc;
1234 struct s3c24xx_irq_of_ctrl *ctrl;
1235 struct irq_domain *domain;
1236 void __iomem *reg_base;
1237 int i;
1238
1239 reg_base = of_iomap(np, 0);
1240 if (!reg_base) {
1241 pr_err("irq-s3c24xx: could not map irq registers\n");
1242 return -EINVAL;
1243 }
1244
1245 domain = irq_domain_add_linear(np, num_ctrl * 32,
1246 &s3c24xx_irq_ops_of, NULL);
1247 if (!domain) {
1248 pr_err("irq: could not create irq-domain\n");
1249 return -EINVAL;
1250 }
1251
1252 for (i = 0; i < num_ctrl; i++) {
1253 ctrl = &s3c_ctrl[i];
1254
1255 pr_debug("irq: found controller %s\n", ctrl->name);
1256
1257 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1258 if (!intc)
1259 return -ENOMEM;
1260
1261 intc->domain = domain;
1262 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
1263 GFP_KERNEL);
1264 if (!intc->irqs) {
1265 kfree(intc);
1266 return -ENOMEM;
1267 }
1268
1269 if (ctrl->parent) {
1270 intc->reg_pending = reg_base + ctrl->offset;
1271 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1272
1273 if (*(ctrl->parent)) {
1274 intc->parent = *(ctrl->parent);
1275 } else {
1276 pr_warn("irq: parent of %s missing\n",
1277 ctrl->name);
1278 kfree(intc->irqs);
1279 kfree(intc);
1280 continue;
1281 }
1282 } else {
1283 intc->reg_pending = reg_base + ctrl->offset;
1284 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1285 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1286 }
1287
1288 s3c24xx_clear_intc(intc);
1289 s3c_intc[i] = intc;
1290 }
1291
1292 set_handle_irq(s3c24xx_handle_irq);
1293
1294 return 0;
1295 }
1296
1297 static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1298 {
1299 .name = "intc",
1300 .offset = 0,
1301 }, {
1302 .name = "subintc",
1303 .offset = 0x18,
1304 .parent = &s3c_intc[0],
1305 }
1306 };
1307
1308 int __init s3c2410_init_intc_of(struct device_node *np,
1309 struct device_node *interrupt_parent)
1310 {
1311 return s3c_init_intc_of(np, interrupt_parent,
1312 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1313 }
1314 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1315
1316 static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1317 {
1318 .name = "intc",
1319 .offset = 0,
1320 }, {
1321 .name = "subintc",
1322 .offset = 0x18,
1323 .parent = &s3c_intc[0],
1324 }, {
1325 .name = "intc2",
1326 .offset = 0x40,
1327 }
1328 };
1329
1330 int __init s3c2416_init_intc_of(struct device_node *np,
1331 struct device_node *interrupt_parent)
1332 {
1333 return s3c_init_intc_of(np, interrupt_parent,
1334 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1335 }
1336 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
1337 #endif
Linux with added FPC-III support