| blob | 2a93fa5f4e49d8c5daf04b412b613f9bdae85adc |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Low-level exception handling code
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
8 */
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
18 #include <asm/bug.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
21 #include <asm/esr.h>
22 #include <asm/irq.h>
23 #include <asm/memory.h>
24 #include <asm/mmu.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
27 #include <asm/scs.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
32 /*
33 * Context tracking and irqflag tracing need to instrument transitions between
34 * user and kernel mode.
35 */
36 .macro user_exit_irqoff
37 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
38 bl enter_from_user_mode
39 #endif
40 .endm
42 .macro user_enter_irqoff
43 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
44 bl exit_to_user_mode
45 #endif
46 .endm
48 .macro clear_gp_regs
49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
50 mov x\n, xzr
51 .endr
52 .endm
54 /*
55 * Bad Abort numbers
56 *-----------------
57 */
58 #define BAD_SYNC 0
59 #define BAD_IRQ 1
60 #define BAD_FIQ 2
61 #define BAD_ERROR 3
63 .macro kernel_ventry, el, label, regsize = 64
64 .align 7
65 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
66 .if \el == 0
67 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
68 .if \regsize == 64
69 mrs x30, tpidrro_el0
70 msr tpidrro_el0, xzr
71 .else
72 mov x30, xzr
73 .endif
74 alternative_else_nop_endif
75 .endif
76 #endif
78 sub sp, sp, #S_FRAME_SIZE
79 #ifdef CONFIG_VMAP_STACK
80 /*
81 * Test whether the SP has overflowed, without corrupting a GPR.
82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
83 * should always be zero.
84 */
85 add sp, sp, x0 // sp' = sp + x0
86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
87 tbnz x0, #THREAD_SHIFT, 0f
88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
90 b el\()\el\()_\label
92 0:
93 /*
94 * Either we've just detected an overflow, or we've taken an exception
95 * while on the overflow stack. Either way, we won't return to
96 * userspace, and can clobber EL0 registers to free up GPRs.
97 */
99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
100 msr tpidr_el0, x0
102 /* Recover the original x0 value and stash it in tpidrro_el0 */
103 sub x0, sp, x0
104 msr tpidrro_el0, x0
106 /* Switch to the overflow stack */
107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
109 /*
110 * Check whether we were already on the overflow stack. This may happen
111 * after panic() re-enables interrupts.
112 */
113 mrs x0, tpidr_el0 // sp of interrupted context
114 sub x0, sp, x0 // delta with top of overflow stack
115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
116 b.ne __bad_stack // no? -> bad stack pointer
118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
119 sub sp, sp, x0
120 mrs x0, tpidrro_el0
121 #endif
122 b el\()\el\()_\label
123 .endm
125 .macro tramp_alias, dst, sym
126 mov_q \dst, TRAMP_VALIAS
127 add \dst, \dst, #(\sym - .entry.tramp.text)
128 .endm
130 /*
131 * This macro corrupts x0-x3. It is the caller's duty to save/restore
132 * them if required.
133 */
134 .macro apply_ssbd, state, tmp1, tmp2
135 alternative_cb spectre_v4_patch_fw_mitigation_enable
136 b .L__asm_ssbd_skip\@ // Patched to NOP
137 alternative_cb_end
138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
139 cbz \tmp2, .L__asm_ssbd_skip\@
140 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
143 mov w1, #\state
144 alternative_cb spectre_v4_patch_fw_mitigation_conduit
145 nop // Patched to SMC/HVC #0
146 alternative_cb_end
147 .L__asm_ssbd_skip\@:
148 .endm
150 /* Check for MTE asynchronous tag check faults */
151 .macro check_mte_async_tcf, flgs, tmp
152 #ifdef CONFIG_ARM64_MTE
153 alternative_if_not ARM64_MTE
154 b 1f
155 alternative_else_nop_endif
156 mrs_s \tmp, SYS_TFSRE0_EL1
157 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
158 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
159 orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT
160 str \flgs, [tsk, #TSK_TI_FLAGS]
161 msr_s SYS_TFSRE0_EL1, xzr
162 1:
163 #endif
164 .endm
166 /* Clear the MTE asynchronous tag check faults */
167 .macro clear_mte_async_tcf
168 #ifdef CONFIG_ARM64_MTE
169 alternative_if ARM64_MTE
170 dsb ish
171 msr_s SYS_TFSRE0_EL1, xzr
172 alternative_else_nop_endif
173 #endif
174 .endm
176 .macro mte_set_gcr, tmp, tmp2
177 #ifdef CONFIG_ARM64_MTE
178 /*
179 * Calculate and set the exclude mask preserving
180 * the RRND (bit[16]) setting.
181 */
182 mrs_s \tmp2, SYS_GCR_EL1
183 bfi \tmp2, \tmp, #0, #16
184 msr_s SYS_GCR_EL1, \tmp2
185 isb
186 #endif
187 .endm
189 .macro mte_set_kernel_gcr, tmp, tmp2
190 #ifdef CONFIG_KASAN_HW_TAGS
191 alternative_if_not ARM64_MTE
192 b 1f
193 alternative_else_nop_endif
194 ldr_l \tmp, gcr_kernel_excl
196 mte_set_gcr \tmp, \tmp2
197 1:
198 #endif
199 .endm
201 .macro mte_set_user_gcr, tsk, tmp, tmp2
202 #ifdef CONFIG_ARM64_MTE
203 alternative_if_not ARM64_MTE
204 b 1f
205 alternative_else_nop_endif
206 ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER]
208 mte_set_gcr \tmp, \tmp2
209 1:
210 #endif
211 .endm
213 .macro kernel_entry, el, regsize = 64
214 .if \regsize == 32
215 mov w0, w0 // zero upper 32 bits of x0
216 .endif
217 stp x0, x1, [sp, #16 * 0]
218 stp x2, x3, [sp, #16 * 1]
219 stp x4, x5, [sp, #16 * 2]
220 stp x6, x7, [sp, #16 * 3]
221 stp x8, x9, [sp, #16 * 4]
222 stp x10, x11, [sp, #16 * 5]
223 stp x12, x13, [sp, #16 * 6]
224 stp x14, x15, [sp, #16 * 7]
225 stp x16, x17, [sp, #16 * 8]
226 stp x18, x19, [sp, #16 * 9]
227 stp x20, x21, [sp, #16 * 10]
228 stp x22, x23, [sp, #16 * 11]
229 stp x24, x25, [sp, #16 * 12]
230 stp x26, x27, [sp, #16 * 13]
231 stp x28, x29, [sp, #16 * 14]
233 .if \el == 0
234 clear_gp_regs
235 mrs x21, sp_el0
236 ldr_this_cpu tsk, __entry_task, x20
237 msr sp_el0, tsk
239 /*
240 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
241 * when scheduling.
242 */
243 ldr x19, [tsk, #TSK_TI_FLAGS]
244 disable_step_tsk x19, x20
246 /* Check for asynchronous tag check faults in user space */
247 check_mte_async_tcf x19, x22
248 apply_ssbd 1, x22, x23
250 ptrauth_keys_install_kernel tsk, x20, x22, x23
252 mte_set_kernel_gcr x22, x23
254 scs_load tsk, x20
255 .else
256 add x21, sp, #S_FRAME_SIZE
257 get_current_task tsk
258 .endif /* \el == 0 */
259 mrs x22, elr_el1
260 mrs x23, spsr_el1
261 stp lr, x21, [sp, #S_LR]
263 /*
264 * In order to be able to dump the contents of struct pt_regs at the
265 * time the exception was taken (in case we attempt to walk the call
266 * stack later), chain it together with the stack frames.
267 */
268 .if \el == 0
269 stp xzr, xzr, [sp, #S_STACKFRAME]
270 .else
271 stp x29, x22, [sp, #S_STACKFRAME]
272 .endif
273 add x29, sp, #S_STACKFRAME
275 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
276 alternative_if_not ARM64_HAS_PAN
277 bl __swpan_entry_el\el
278 alternative_else_nop_endif
279 #endif
281 stp x22, x23, [sp, #S_PC]
283 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
284 .if \el == 0
285 mov w21, #NO_SYSCALL
286 str w21, [sp, #S_SYSCALLNO]
287 .endif
289 /* Save pmr */
290 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
291 mrs_s x20, SYS_ICC_PMR_EL1
292 str x20, [sp, #S_PMR_SAVE]
293 alternative_else_nop_endif
295 /* Re-enable tag checking (TCO set on exception entry) */
296 #ifdef CONFIG_ARM64_MTE
297 alternative_if ARM64_MTE
298 SET_PSTATE_TCO(0)
299 alternative_else_nop_endif
300 #endif
302 /*
303 * Registers that may be useful after this macro is invoked:
304 *
305 * x20 - ICC_PMR_EL1
306 * x21 - aborted SP
307 * x22 - aborted PC
308 * x23 - aborted PSTATE
309 */
310 .endm
312 .macro kernel_exit, el
313 .if \el != 0
314 disable_daif
315 .endif
317 /* Restore pmr */
318 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
319 ldr x20, [sp, #S_PMR_SAVE]
320 msr_s SYS_ICC_PMR_EL1, x20
321 mrs_s x21, SYS_ICC_CTLR_EL1
322 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
323 dsb sy // Ensure priority change is seen by redistributor
324 .L__skip_pmr_sync\@:
325 alternative_else_nop_endif
327 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
329 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
330 alternative_if_not ARM64_HAS_PAN
331 bl __swpan_exit_el\el
332 alternative_else_nop_endif
333 #endif
335 .if \el == 0
336 ldr x23, [sp, #S_SP] // load return stack pointer
337 msr sp_el0, x23
338 tst x22, #PSR_MODE32_BIT // native task?
339 b.eq 3f
341 #ifdef CONFIG_ARM64_ERRATUM_845719
342 alternative_if ARM64_WORKAROUND_845719
343 #ifdef CONFIG_PID_IN_CONTEXTIDR
344 mrs x29, contextidr_el1
345 msr contextidr_el1, x29
346 #else
347 msr contextidr_el1, xzr
348 #endif
349 alternative_else_nop_endif
350 #endif
351 3:
352 scs_save tsk, x0
354 /* No kernel C function calls after this as user keys are set. */
355 ptrauth_keys_install_user tsk, x0, x1, x2
357 mte_set_user_gcr tsk, x0, x1
359 apply_ssbd 0, x0, x1
360 .endif
362 msr elr_el1, x21 // set up the return data
363 msr spsr_el1, x22
364 ldp x0, x1, [sp, #16 * 0]
365 ldp x2, x3, [sp, #16 * 1]
366 ldp x4, x5, [sp, #16 * 2]
367 ldp x6, x7, [sp, #16 * 3]
368 ldp x8, x9, [sp, #16 * 4]
369 ldp x10, x11, [sp, #16 * 5]
370 ldp x12, x13, [sp, #16 * 6]
371 ldp x14, x15, [sp, #16 * 7]
372 ldp x16, x17, [sp, #16 * 8]
373 ldp x18, x19, [sp, #16 * 9]
374 ldp x20, x21, [sp, #16 * 10]
375 ldp x22, x23, [sp, #16 * 11]
376 ldp x24, x25, [sp, #16 * 12]
377 ldp x26, x27, [sp, #16 * 13]
378 ldp x28, x29, [sp, #16 * 14]
379 ldr lr, [sp, #S_LR]
380 add sp, sp, #S_FRAME_SIZE // restore sp
382 .if \el == 0
383 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
384 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
385 bne 4f
386 msr far_el1, x30
387 tramp_alias x30, tramp_exit_native
388 br x30
389 4:
390 tramp_alias x30, tramp_exit_compat
391 br x30
392 #endif
393 .else
394 /* Ensure any device/NC reads complete */
395 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
397 eret
398 .endif
399 sb
400 .endm
402 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
403 /*
404 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
405 * EL0, there is no need to check the state of TTBR0_EL1 since
406 * accesses are always enabled.
407 * Note that the meaning of this bit differs from the ARMv8.1 PAN
408 * feature as all TTBR0_EL1 accesses are disabled, not just those to
409 * user mappings.
410 */
411 SYM_CODE_START_LOCAL(__swpan_entry_el1)
412 mrs x21, ttbr0_el1
413 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
414 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
415 b.eq 1f // TTBR0 access already disabled
416 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
417 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
418 __uaccess_ttbr0_disable x21
419 1: ret
420 SYM_CODE_END(__swpan_entry_el1)
422 /*
423 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
424 * PAN bit checking.
425 */
426 SYM_CODE_START_LOCAL(__swpan_exit_el1)
427 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
428 __uaccess_ttbr0_enable x0, x1
429 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
430 ret
431 SYM_CODE_END(__swpan_exit_el1)
433 SYM_CODE_START_LOCAL(__swpan_exit_el0)
434 __uaccess_ttbr0_enable x0, x1
435 /*
436 * Enable errata workarounds only if returning to user. The only
437 * workaround currently required for TTBR0_EL1 changes are for the
438 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
439 * corruption).
440 */
441 b post_ttbr_update_workaround
442 SYM_CODE_END(__swpan_exit_el0)
443 #endif
445 .macro irq_stack_entry
446 mov x19, sp // preserve the original sp
447 #ifdef CONFIG_SHADOW_CALL_STACK
448 mov x24, scs_sp // preserve the original shadow stack
449 #endif
451 /*
452 * Compare sp with the base of the task stack.
453 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
454 * and should switch to the irq stack.
455 */
456 ldr x25, [tsk, TSK_STACK]
457 eor x25, x25, x19
458 and x25, x25, #~(THREAD_SIZE - 1)
459 cbnz x25, 9998f
461 ldr_this_cpu x25, irq_stack_ptr, x26
462 mov x26, #IRQ_STACK_SIZE
463 add x26, x25, x26
465 /* switch to the irq stack */
466 mov sp, x26
468 #ifdef CONFIG_SHADOW_CALL_STACK
469 /* also switch to the irq shadow stack */
470 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x26
471 #endif
473 9998:
474 .endm
476 /*
477 * The callee-saved regs (x19-x29) should be preserved between
478 * irq_stack_entry and irq_stack_exit, but note that kernel_entry
479 * uses x20-x23 to store data for later use.
480 */
481 .macro irq_stack_exit
482 mov sp, x19
483 #ifdef CONFIG_SHADOW_CALL_STACK
484 mov scs_sp, x24
485 #endif
486 .endm
488 /* GPRs used by entry code */
489 tsk .req x28 // current thread_info
491 /*
492 * Interrupt handling.
493 */
494 .macro irq_handler
495 ldr_l x1, handle_arch_irq
496 mov x0, sp
497 irq_stack_entry
498 blr x1
499 irq_stack_exit
500 .endm
502 #ifdef CONFIG_ARM64_PSEUDO_NMI
503 /*
504 * Set res to 0 if irqs were unmasked in interrupted context.
505 * Otherwise set res to non-0 value.
506 */
507 .macro test_irqs_unmasked res:req, pmr:req
508 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
509 sub \res, \pmr, #GIC_PRIO_IRQON
510 alternative_else
511 mov \res, xzr
512 alternative_endif
513 .endm
514 #endif
516 .macro gic_prio_kentry_setup, tmp:req
517 #ifdef CONFIG_ARM64_PSEUDO_NMI
518 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
519 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
520 msr_s SYS_ICC_PMR_EL1, \tmp
521 alternative_else_nop_endif
522 #endif
523 .endm
525 .macro gic_prio_irq_setup, pmr:req, tmp:req
526 #ifdef CONFIG_ARM64_PSEUDO_NMI
527 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
528 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET
529 msr_s SYS_ICC_PMR_EL1, \tmp
530 alternative_else_nop_endif
531 #endif
532 .endm
534 .text
536 /*
537 * Exception vectors.
538 */
539 .pushsection ".entry.text", "ax"
541 .align 11
542 SYM_CODE_START(vectors)
543 kernel_ventry 1, sync_invalid // Synchronous EL1t
544 kernel_ventry 1, irq_invalid // IRQ EL1t
545 kernel_ventry 1, fiq_invalid // FIQ EL1t
546 kernel_ventry 1, error_invalid // Error EL1t
548 kernel_ventry 1, sync // Synchronous EL1h
549 kernel_ventry 1, irq // IRQ EL1h
550 kernel_ventry 1, fiq_invalid // FIQ EL1h
551 kernel_ventry 1, error // Error EL1h
553 kernel_ventry 0, sync // Synchronous 64-bit EL0
554 kernel_ventry 0, irq // IRQ 64-bit EL0
555 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
556 kernel_ventry 0, error // Error 64-bit EL0
558 #ifdef CONFIG_COMPAT
559 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
560 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
561 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
562 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
563 #else
564 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
565 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
566 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
567 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
568 #endif
569 SYM_CODE_END(vectors)
571 #ifdef CONFIG_VMAP_STACK
572 /*
573 * We detected an overflow in kernel_ventry, which switched to the
574 * overflow stack. Stash the exception regs, and head to our overflow
575 * handler.
576 */
577 __bad_stack:
578 /* Restore the original x0 value */
579 mrs x0, tpidrro_el0
581 /*
582 * Store the original GPRs to the new stack. The orginal SP (minus
583 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
584 */
585 sub sp, sp, #S_FRAME_SIZE
586 kernel_entry 1
587 mrs x0, tpidr_el0
588 add x0, x0, #S_FRAME_SIZE
589 str x0, [sp, #S_SP]
591 /* Stash the regs for handle_bad_stack */
592 mov x0, sp
594 /* Time to die */
595 bl handle_bad_stack
596 ASM_BUG()
597 #endif /* CONFIG_VMAP_STACK */
599 /*
600 * Invalid mode handlers
601 */
602 .macro inv_entry, el, reason, regsize = 64
603 kernel_entry \el, \regsize
604 mov x0, sp
605 mov x1, #\reason
606 mrs x2, esr_el1
607 bl bad_mode
608 ASM_BUG()
609 .endm
611 SYM_CODE_START_LOCAL(el0_sync_invalid)
612 inv_entry 0, BAD_SYNC
613 SYM_CODE_END(el0_sync_invalid)
615 SYM_CODE_START_LOCAL(el0_irq_invalid)
616 inv_entry 0, BAD_IRQ
617 SYM_CODE_END(el0_irq_invalid)
619 SYM_CODE_START_LOCAL(el0_fiq_invalid)
620 inv_entry 0, BAD_FIQ
621 SYM_CODE_END(el0_fiq_invalid)
623 SYM_CODE_START_LOCAL(el0_error_invalid)
624 inv_entry 0, BAD_ERROR
625 SYM_CODE_END(el0_error_invalid)
627 #ifdef CONFIG_COMPAT
628 SYM_CODE_START_LOCAL(el0_fiq_invalid_compat)
629 inv_entry 0, BAD_FIQ, 32
630 SYM_CODE_END(el0_fiq_invalid_compat)
631 #endif
633 SYM_CODE_START_LOCAL(el1_sync_invalid)
634 inv_entry 1, BAD_SYNC
635 SYM_CODE_END(el1_sync_invalid)
637 SYM_CODE_START_LOCAL(el1_irq_invalid)
638 inv_entry 1, BAD_IRQ
639 SYM_CODE_END(el1_irq_invalid)
641 SYM_CODE_START_LOCAL(el1_fiq_invalid)
642 inv_entry 1, BAD_FIQ
643 SYM_CODE_END(el1_fiq_invalid)
645 SYM_CODE_START_LOCAL(el1_error_invalid)
646 inv_entry 1, BAD_ERROR
647 SYM_CODE_END(el1_error_invalid)
649 /*
650 * EL1 mode handlers.
651 */
652 .align 6
653 SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
654 kernel_entry 1
655 mov x0, sp
656 bl el1_sync_handler
657 kernel_exit 1
658 SYM_CODE_END(el1_sync)
660 .align 6
661 SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
662 kernel_entry 1
663 gic_prio_irq_setup pmr=x20, tmp=x1
664 enable_da_f
666 mov x0, sp
667 bl enter_el1_irq_or_nmi
669 irq_handler
671 #ifdef CONFIG_PREEMPTION
672 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count
673 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
674 /*
675 * DA_F were cleared at start of handling. If anything is set in DAIF,
676 * we come back from an NMI, so skip preemption
677 */
678 mrs x0, daif
679 orr x24, x24, x0
680 alternative_else_nop_endif
681 cbnz x24, 1f // preempt count != 0 || NMI return path
682 bl arm64_preempt_schedule_irq // irq en/disable is done inside
683 1:
684 #endif
686 mov x0, sp
687 bl exit_el1_irq_or_nmi
689 kernel_exit 1
690 SYM_CODE_END(el1_irq)
692 /*
693 * EL0 mode handlers.
694 */
695 .align 6
696 SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
697 kernel_entry 0
698 mov x0, sp
699 bl el0_sync_handler
700 b ret_to_user
701 SYM_CODE_END(el0_sync)
703 #ifdef CONFIG_COMPAT
704 .align 6
705 SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
706 kernel_entry 0, 32
707 mov x0, sp
708 bl el0_sync_compat_handler
709 b ret_to_user
710 SYM_CODE_END(el0_sync_compat)
712 .align 6
713 SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
714 kernel_entry 0, 32
715 b el0_irq_naked
716 SYM_CODE_END(el0_irq_compat)
718 SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
719 kernel_entry 0, 32
720 b el0_error_naked
721 SYM_CODE_END(el0_error_compat)
722 #endif
724 .align 6
725 SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
726 kernel_entry 0
727 el0_irq_naked:
728 gic_prio_irq_setup pmr=x20, tmp=x0
729 user_exit_irqoff
730 enable_da_f
732 tbz x22, #55, 1f
733 bl do_el0_irq_bp_hardening
734 1:
735 irq_handler
737 b ret_to_user
738 SYM_CODE_END(el0_irq)
740 SYM_CODE_START_LOCAL(el1_error)
741 kernel_entry 1
742 mrs x1, esr_el1
743 gic_prio_kentry_setup tmp=x2
744 enable_dbg
745 mov x0, sp
746 bl do_serror
747 kernel_exit 1
748 SYM_CODE_END(el1_error)
750 SYM_CODE_START_LOCAL(el0_error)
751 kernel_entry 0
752 el0_error_naked:
753 mrs x25, esr_el1
754 gic_prio_kentry_setup tmp=x2
755 user_exit_irqoff
756 enable_dbg
757 mov x0, sp
758 mov x1, x25
759 bl do_serror
760 enable_da_f
761 b ret_to_user
762 SYM_CODE_END(el0_error)
764 /*
765 * "slow" syscall return path.
766 */
767 SYM_CODE_START_LOCAL(ret_to_user)
768 disable_daif
769 gic_prio_kentry_setup tmp=x3
770 #ifdef CONFIG_TRACE_IRQFLAGS
771 bl trace_hardirqs_off
772 #endif
773 ldr x19, [tsk, #TSK_TI_FLAGS]
774 and x2, x19, #_TIF_WORK_MASK
775 cbnz x2, work_pending
776 finish_ret_to_user:
777 user_enter_irqoff
778 /* Ignore asynchronous tag check faults in the uaccess routines */
779 clear_mte_async_tcf
780 enable_step_tsk x19, x2
781 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
782 bl stackleak_erase
783 #endif
784 kernel_exit 0
786 /*
787 * Ok, we need to do extra processing, enter the slow path.
788 */
789 work_pending:
790 mov x0, sp // 'regs'
791 mov x1, x19
792 bl do_notify_resume
793 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
794 b finish_ret_to_user
795 SYM_CODE_END(ret_to_user)
797 .popsection // .entry.text
799 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
800 /*
801 * Exception vectors trampoline.
802 */
803 .pushsection ".entry.tramp.text", "ax"
805 // Move from tramp_pg_dir to swapper_pg_dir
806 .macro tramp_map_kernel, tmp
807 mrs \tmp, ttbr1_el1
808 add \tmp, \tmp, #(2 * PAGE_SIZE)
809 bic \tmp, \tmp, #USER_ASID_FLAG
810 msr ttbr1_el1, \tmp
811 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
812 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
813 /* ASID already in \tmp[63:48] */
814 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
815 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
816 /* 2MB boundary containing the vectors, so we nobble the walk cache */
817 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
818 isb
819 tlbi vae1, \tmp
820 dsb nsh
821 alternative_else_nop_endif
822 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
823 .endm
825 // Move from swapper_pg_dir to tramp_pg_dir
826 .macro tramp_unmap_kernel, tmp
827 mrs \tmp, ttbr1_el1
828 sub \tmp, \tmp, #(2 * PAGE_SIZE)
829 orr \tmp, \tmp, #USER_ASID_FLAG
830 msr ttbr1_el1, \tmp
831 /*
832 * We avoid running the post_ttbr_update_workaround here because
833 * it's only needed by Cavium ThunderX, which requires KPTI to be
834 * disabled.
835 */
836 .endm
838 .macro tramp_ventry, regsize = 64
839 .align 7
840 1:
841 .if \regsize == 64
842 msr tpidrro_el0, x30 // Restored in kernel_ventry
843 .endif
844 /*
845 * Defend against branch aliasing attacks by pushing a dummy
846 * entry onto the return stack and using a RET instruction to
847 * enter the full-fat kernel vectors.
848 */
849 bl 2f
850 b .
851 2:
852 tramp_map_kernel x30
853 #ifdef CONFIG_RANDOMIZE_BASE
854 adr x30, tramp_vectors + PAGE_SIZE
855 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
856 ldr x30, [x30]
857 #else
858 ldr x30, =vectors
859 #endif
860 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
861 prfm plil1strm, [x30, #(1b - tramp_vectors)]
862 alternative_else_nop_endif
863 msr vbar_el1, x30
864 add x30, x30, #(1b - tramp_vectors)
865 isb
866 ret
867 .endm
869 .macro tramp_exit, regsize = 64
870 adr x30, tramp_vectors
871 msr vbar_el1, x30
872 tramp_unmap_kernel x30
873 .if \regsize == 64
874 mrs x30, far_el1
875 .endif
876 eret
877 sb
878 .endm
880 .align 11
881 SYM_CODE_START_NOALIGN(tramp_vectors)
882 .space 0x400
884 tramp_ventry
885 tramp_ventry
886 tramp_ventry
887 tramp_ventry
889 tramp_ventry 32
890 tramp_ventry 32
891 tramp_ventry 32
892 tramp_ventry 32
893 SYM_CODE_END(tramp_vectors)
895 SYM_CODE_START(tramp_exit_native)
896 tramp_exit
897 SYM_CODE_END(tramp_exit_native)
899 SYM_CODE_START(tramp_exit_compat)
900 tramp_exit 32
901 SYM_CODE_END(tramp_exit_compat)
903 .ltorg
904 .popsection // .entry.tramp.text
905 #ifdef CONFIG_RANDOMIZE_BASE
906 .pushsection ".rodata", "a"
907 .align PAGE_SHIFT
908 SYM_DATA_START(__entry_tramp_data_start)
909 .quad vectors
910 SYM_DATA_END(__entry_tramp_data_start)
911 .popsection // .rodata
912 #endif /* CONFIG_RANDOMIZE_BASE */
913 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
915 /*
916 * Register switch for AArch64. The callee-saved registers need to be saved
917 * and restored. On entry:
918 * x0 = previous task_struct (must be preserved across the switch)
919 * x1 = next task_struct
920 * Previous and next are guaranteed not to be the same.
921 *
922 */
923 SYM_FUNC_START(cpu_switch_to)
924 mov x10, #THREAD_CPU_CONTEXT
925 add x8, x0, x10
926 mov x9, sp
927 stp x19, x20, [x8], #16 // store callee-saved registers
928 stp x21, x22, [x8], #16
929 stp x23, x24, [x8], #16
930 stp x25, x26, [x8], #16
931 stp x27, x28, [x8], #16
932 stp x29, x9, [x8], #16
933 str lr, [x8]
934 add x8, x1, x10
935 ldp x19, x20, [x8], #16 // restore callee-saved registers
936 ldp x21, x22, [x8], #16
937 ldp x23, x24, [x8], #16
938 ldp x25, x26, [x8], #16
939 ldp x27, x28, [x8], #16
940 ldp x29, x9, [x8], #16
941 ldr lr, [x8]
942 mov sp, x9
943 msr sp_el0, x1
944 ptrauth_keys_install_kernel x1, x8, x9, x10
945 scs_save x0, x8
946 scs_load x1, x8
947 ret
948 SYM_FUNC_END(cpu_switch_to)
949 NOKPROBE(cpu_switch_to)
951 /*
952 * This is how we return from a fork.
953 */
954 SYM_CODE_START(ret_from_fork)
955 bl schedule_tail
956 cbz x19, 1f // not a kernel thread
957 mov x0, x20
958 blr x19
959 1: get_current_task tsk
960 b ret_to_user
961 SYM_CODE_END(ret_from_fork)
962 NOKPROBE(ret_from_fork)
964 #ifdef CONFIG_ARM_SDE_INTERFACE
966 #include <asm/sdei.h>
967 #include <uapi/linux/arm_sdei.h>
969 .macro sdei_handler_exit exit_mode
970 /* On success, this call never returns... */
971 cmp \exit_mode, #SDEI_EXIT_SMC
972 b.ne 99f
973 smc #0
974 b .
975 99: hvc #0
976 b .
977 .endm
979 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
980 /*
981 * The regular SDEI entry point may have been unmapped along with the rest of
982 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
983 * argument accessible.
984 *
985 * This clobbers x4, __sdei_handler() will restore this from firmware's
986 * copy.
987 */
988 .ltorg
989 .pushsection ".entry.tramp.text", "ax"
990 SYM_CODE_START(__sdei_asm_entry_trampoline)
991 mrs x4, ttbr1_el1
992 tbz x4, #USER_ASID_BIT, 1f
994 tramp_map_kernel tmp=x4
995 isb
996 mov x4, xzr
998 /*
999 * Remember whether to unmap the kernel on exit.
1000 */
1001 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
1003 #ifdef CONFIG_RANDOMIZE_BASE
1004 adr x4, tramp_vectors + PAGE_SIZE
1005 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1006 ldr x4, [x4]
1007 #else
1008 ldr x4, =__sdei_asm_handler
1009 #endif
1010 br x4
1011 SYM_CODE_END(__sdei_asm_entry_trampoline)
1012 NOKPROBE(__sdei_asm_entry_trampoline)
1014 /*
1015 * Make the exit call and restore the original ttbr1_el1
1016 *
1017 * x0 & x1: setup for the exit API call
1018 * x2: exit_mode
1019 * x4: struct sdei_registered_event argument from registration time.
1020 */
1021 SYM_CODE_START(__sdei_asm_exit_trampoline)
1022 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
1023 cbnz x4, 1f
1025 tramp_unmap_kernel tmp=x4
1027 1: sdei_handler_exit exit_mode=x2
1028 SYM_CODE_END(__sdei_asm_exit_trampoline)
1029 NOKPROBE(__sdei_asm_exit_trampoline)
1030 .ltorg
1031 .popsection // .entry.tramp.text
1032 #ifdef CONFIG_RANDOMIZE_BASE
1033 .pushsection ".rodata", "a"
1034 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
1035 .quad __sdei_asm_handler
1036 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
1037 .popsection // .rodata
1038 #endif /* CONFIG_RANDOMIZE_BASE */
1039 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1041 /*
1042 * Software Delegated Exception entry point.
1043 *
1044 * x0: Event number
1045 * x1: struct sdei_registered_event argument from registration time.
1046 * x2: interrupted PC
1047 * x3: interrupted PSTATE
1048 * x4: maybe clobbered by the trampoline
1049 *
1050 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1051 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1052 * want them.
1053 */
1054 SYM_CODE_START(__sdei_asm_handler)
1055 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1056 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1057 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1058 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1059 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1060 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1061 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1062 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1063 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1064 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1065 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1066 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1067 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1068 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1069 mov x4, sp
1070 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1072 mov x19, x1
1074 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1075 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1076 #endif
1078 #ifdef CONFIG_VMAP_STACK
1079 /*
1080 * entry.S may have been using sp as a scratch register, find whether
1081 * this is a normal or critical event and switch to the appropriate
1082 * stack for this CPU.
1083 */
1084 cbnz w4, 1f
1085 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1086 b 2f
1087 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1088 2: mov x6, #SDEI_STACK_SIZE
1089 add x5, x5, x6
1090 mov sp, x5
1091 #endif
1093 #ifdef CONFIG_SHADOW_CALL_STACK
1094 /* Use a separate shadow call stack for normal and critical events */
1095 cbnz w4, 3f
1096 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
1097 b 4f
1098 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
1099 4:
1100 #endif
1102 /*
1103 * We may have interrupted userspace, or a guest, or exit-from or
1104 * return-to either of these. We can't trust sp_el0, restore it.
1105 */
1106 mrs x28, sp_el0
1107 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1108 msr sp_el0, x0
1110 /* If we interrupted the kernel point to the previous stack/frame. */
1111 and x0, x3, #0xc
1112 mrs x1, CurrentEL
1113 cmp x0, x1
1114 csel x29, x29, xzr, eq // fp, or zero
1115 csel x4, x2, xzr, eq // elr, or zero
1117 stp x29, x4, [sp, #-16]!
1118 mov x29, sp
1120 add x0, x19, #SDEI_EVENT_INTREGS
1121 mov x1, x19
1122 bl __sdei_handler
1124 msr sp_el0, x28
1125 /* restore regs >x17 that we clobbered */
1126 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1127 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1128 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1129 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1130 mov sp, x1
1132 mov x1, x0 // address to complete_and_resume
1133 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1134 cmp x0, #1
1135 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1136 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1137 csel x0, x2, x3, ls
1139 ldr_l x2, sdei_exit_mode
1141 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1142 sdei_handler_exit exit_mode=x2
1143 alternative_else_nop_endif
1145 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1146 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1147 br x5
1148 #endif
1149 SYM_CODE_END(__sdei_asm_handler)
1150 NOKPROBE(__sdei_asm_handler)
1151 #endif /* CONFIG_ARM_SDE_INTERFACE */