arch/arm64/kernel/module.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * AArch64 loadable module support.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  *
   7  * Author: Will Deacon <will.deacon@arm.com>
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/elf.h>
  12 #include <linux/ftrace.h>
  13 #include <linux/gfp.h>
  14 #include <linux/kasan.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/moduleloader.h>
  18 #include <linux/vmalloc.h>
  19 #include <asm/alternative.h>
  20 #include <asm/insn.h>
  21 #include <asm/sections.h>
  22
  23 void *module_alloc(unsigned long size)
  24 {
  25         u64 module_alloc_end = module_alloc_base + MODULES_VSIZE;
  26         gfp_t gfp_mask = GFP_KERNEL;
  27         void *p;
  28
  29         /* Silence the initial allocation */
  30         if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
  31                 gfp_mask |= __GFP_NOWARN;
  32
  33         if (IS_ENABLED(CONFIG_KASAN_GENERIC) ||
  34             IS_ENABLED(CONFIG_KASAN_SW_TAGS))
  35                 /* don't exceed the static module region - see below */
  36                 module_alloc_end = MODULES_END;
  37
  38         p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
  39                                 module_alloc_end, gfp_mask, PAGE_KERNEL, 0,
  40                                 NUMA_NO_NODE, __builtin_return_address(0));
  41
  42         if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
  43             !IS_ENABLED(CONFIG_KASAN_GENERIC) &&
  44             !IS_ENABLED(CONFIG_KASAN_SW_TAGS))
  45                 /*
  46                  * KASAN can only deal with module allocations being served
  47                  * from the reserved module region, since the remainder of
  48                  * the vmalloc region is already backed by zero shadow pages,
  49                  * and punching holes into it is non-trivial. Since the module
  50                  * region is not randomized when KASAN is enabled, it is even
  51                  * less likely that the module region gets exhausted, so we
  52                  * can simply omit this fallback in that case.
  53                  */
  54                 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
  55                                 module_alloc_base + SZ_2G, GFP_KERNEL,
  56                                 PAGE_KERNEL, 0, NUMA_NO_NODE,
  57                                 __builtin_return_address(0));
  58
  59         if (p && (kasan_module_alloc(p, size) < 0)) {
  60                 vfree(p);
  61                 return NULL;
  62         }
  63
  64         return p;
  65 }
  66
  67 enum aarch64_reloc_op {
  68         RELOC_OP_NONE,
  69         RELOC_OP_ABS,
  70         RELOC_OP_PREL,
  71         RELOC_OP_PAGE,
  72 };
  73
  74 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
  75 {
  76         switch (reloc_op) {
  77         case RELOC_OP_ABS:
  78                 return val;
  79         case RELOC_OP_PREL:
  80                 return val - (u64)place;
  81         case RELOC_OP_PAGE:
  82                 return (val & ~0xfff) - ((u64)place & ~0xfff);
  83         case RELOC_OP_NONE:
  84                 return 0;
  85         }
  86
  87         pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
  88         return 0;
  89 }
  90
  91 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
  92 {
  93         s64 sval = do_reloc(op, place, val);
  94
  95         /*
  96          * The ELF psABI for AArch64 documents the 16-bit and 32-bit place
  97          * relative and absolute relocations as having a range of [-2^15, 2^16)
  98          * or [-2^31, 2^32), respectively. However, in order to be able to
  99          * detect overflows reliably, we have to choose whether we interpret
 100          * such quantities as signed or as unsigned, and stick with it.
 101          * The way we organize our address space requires a signed
 102          * interpretation of 32-bit relative references, so let's use that
 103          * for all R_AARCH64_PRELxx relocations. This means our upper
 104          * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
 105          */
 106
 107         switch (len) {
 108         case 16:
 109                 *(s16 *)place = sval;
 110                 switch (op) {
 111                 case RELOC_OP_ABS:
 112                         if (sval < 0 || sval > U16_MAX)
 113                                 return -ERANGE;
 114                         break;
 115                 case RELOC_OP_PREL:
 116                         if (sval < S16_MIN || sval > S16_MAX)
 117                                 return -ERANGE;
 118                         break;
 119                 default:
 120                         pr_err("Invalid 16-bit data relocation (%d)\n", op);
 121                         return 0;
 122                 }
 123                 break;
 124         case 32:
 125                 *(s32 *)place = sval;
 126                 switch (op) {
 127                 case RELOC_OP_ABS:
 128                         if (sval < 0 || sval > U32_MAX)
 129                                 return -ERANGE;
 130                         break;
 131                 case RELOC_OP_PREL:
 132                         if (sval < S32_MIN || sval > S32_MAX)
 133                                 return -ERANGE;
 134                         break;
 135                 default:
 136                         pr_err("Invalid 32-bit data relocation (%d)\n", op);
 137                         return 0;
 138                 }
 139                 break;
 140         case 64:
 141                 *(s64 *)place = sval;
 142                 break;
 143         default:
 144                 pr_err("Invalid length (%d) for data relocation\n", len);
 145                 return 0;
 146         }
 147         return 0;
 148 }
 149
 150 enum aarch64_insn_movw_imm_type {
 151         AARCH64_INSN_IMM_MOVNZ,
 152         AARCH64_INSN_IMM_MOVKZ,
 153 };
 154
 155 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
 156                            int lsb, enum aarch64_insn_movw_imm_type imm_type)
 157 {
 158         u64 imm;
 159         s64 sval;
 160         u32 insn = le32_to_cpu(*place);
 161
 162         sval = do_reloc(op, place, val);
 163         imm = sval >> lsb;
 164
 165         if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
 166                 /*
 167                  * For signed MOVW relocations, we have to manipulate the
 168                  * instruction encoding depending on whether or not the
 169                  * immediate is less than zero.
 170                  */
 171                 insn &= ~(3 << 29);
 172                 if (sval >= 0) {
 173                         /* >=0: Set the instruction to MOVZ (opcode 10b). */
 174                         insn |= 2 << 29;
 175                 } else {
 176                         /*
 177                          * <0: Set the instruction to MOVN (opcode 00b).
 178                          *     Since we've masked the opcode already, we
 179                          *     don't need to do anything other than
 180                          *     inverting the new immediate field.
 181                          */
 182                         imm = ~imm;
 183                 }
 184         }
 185
 186         /* Update the instruction with the new encoding. */
 187         insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
 188         *place = cpu_to_le32(insn);
 189
 190         if (imm > U16_MAX)
 191                 return -ERANGE;
 192
 193         return 0;
 194 }
 195
 196 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
 197                           int lsb, int len, enum aarch64_insn_imm_type imm_type)
 198 {
 199         u64 imm, imm_mask;
 200         s64 sval;
 201         u32 insn = le32_to_cpu(*place);
 202
 203         /* Calculate the relocation value. */
 204         sval = do_reloc(op, place, val);
 205         sval >>= lsb;
 206
 207         /* Extract the value bits and shift them to bit 0. */
 208         imm_mask = (BIT(lsb + len) - 1) >> lsb;
 209         imm = sval & imm_mask;
 210
 211         /* Update the instruction's immediate field. */
 212         insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
 213         *place = cpu_to_le32(insn);
 214
 215         /*
 216          * Extract the upper value bits (including the sign bit) and
 217          * shift them to bit 0.
 218          */
 219         sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
 220
 221         /*
 222          * Overflow has occurred if the upper bits are not all equal to
 223          * the sign bit of the value.
 224          */
 225         if ((u64)(sval + 1) >= 2)
 226                 return -ERANGE;
 227
 228         return 0;
 229 }
 230
 231 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
 232                            __le32 *place, u64 val)
 233 {
 234         u32 insn;
 235
 236         if (!is_forbidden_offset_for_adrp(place))
 237                 return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
 238                                       AARCH64_INSN_IMM_ADR);
 239
 240         /* patch ADRP to ADR if it is in range */
 241         if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
 242                             AARCH64_INSN_IMM_ADR)) {
 243                 insn = le32_to_cpu(*place);
 244                 insn &= ~BIT(31);
 245         } else {
 246                 /* out of range for ADR -> emit a veneer */
 247                 val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
 248                 if (!val)
 249                         return -ENOEXEC;
 250                 insn = aarch64_insn_gen_branch_imm((u64)place, val,
 251                                                    AARCH64_INSN_BRANCH_NOLINK);
 252         }
 253
 254         *place = cpu_to_le32(insn);
 255         return 0;
 256 }
 257
 258 int apply_relocate_add(Elf64_Shdr *sechdrs,
 259                        const char *strtab,
 260                        unsigned int symindex,
 261                        unsigned int relsec,
 262                        struct module *me)
 263 {
 264         unsigned int i;
 265         int ovf;
 266         bool overflow_check;
 267         Elf64_Sym *sym;
 268         void *loc;
 269         u64 val;
 270         Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
 271
 272         for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
 273                 /* loc corresponds to P in the AArch64 ELF document. */
 274                 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
 275                         + rel[i].r_offset;
 276
 277                 /* sym is the ELF symbol we're referring to. */
 278                 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
 279                         + ELF64_R_SYM(rel[i].r_info);
 280
 281                 /* val corresponds to (S + A) in the AArch64 ELF document. */
 282                 val = sym->st_value + rel[i].r_addend;
 283
 284                 /* Check for overflow by default. */
 285                 overflow_check = true;
 286
 287                 /* Perform the static relocation. */
 288                 switch (ELF64_R_TYPE(rel[i].r_info)) {
 289                 /* Null relocations. */
 290                 case R_ARM_NONE:
 291                 case R_AARCH64_NONE:
 292                         ovf = 0;
 293                         break;
 294
 295                 /* Data relocations. */
 296                 case R_AARCH64_ABS64:
 297                         overflow_check = false;
 298                         ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
 299                         break;
 300                 case R_AARCH64_ABS32:
 301                         ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
 302                         break;
 303                 case R_AARCH64_ABS16:
 304                         ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
 305                         break;
 306                 case R_AARCH64_PREL64:
 307                         overflow_check = false;
 308                         ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
 309                         break;
 310                 case R_AARCH64_PREL32:
 311                         ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
 312                         break;
 313                 case R_AARCH64_PREL16:
 314                         ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
 315                         break;
 316
 317                 /* MOVW instruction relocations. */
 318                 case R_AARCH64_MOVW_UABS_G0_NC:
 319                         overflow_check = false;
 320                         fallthrough;
 321                 case R_AARCH64_MOVW_UABS_G0:
 322                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
 323                                               AARCH64_INSN_IMM_MOVKZ);
 324                         break;
 325                 case R_AARCH64_MOVW_UABS_G1_NC:
 326                         overflow_check = false;
 327                         fallthrough;
 328                 case R_AARCH64_MOVW_UABS_G1:
 329                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
 330                                               AARCH64_INSN_IMM_MOVKZ);
 331                         break;
 332                 case R_AARCH64_MOVW_UABS_G2_NC:
 333                         overflow_check = false;
 334                         fallthrough;
 335                 case R_AARCH64_MOVW_UABS_G2:
 336                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
 337                                               AARCH64_INSN_IMM_MOVKZ);
 338                         break;
 339                 case R_AARCH64_MOVW_UABS_G3:
 340                         /* We're using the top bits so we can't overflow. */
 341                         overflow_check = false;
 342                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
 343                                               AARCH64_INSN_IMM_MOVKZ);
 344                         break;
 345                 case R_AARCH64_MOVW_SABS_G0:
 346                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
 347                                               AARCH64_INSN_IMM_MOVNZ);
 348                         break;
 349                 case R_AARCH64_MOVW_SABS_G1:
 350                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
 351                                               AARCH64_INSN_IMM_MOVNZ);
 352                         break;
 353                 case R_AARCH64_MOVW_SABS_G2:
 354                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
 355                                               AARCH64_INSN_IMM_MOVNZ);
 356                         break;
 357                 case R_AARCH64_MOVW_PREL_G0_NC:
 358                         overflow_check = false;
 359                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
 360                                               AARCH64_INSN_IMM_MOVKZ);
 361                         break;
 362                 case R_AARCH64_MOVW_PREL_G0:
 363                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
 364                                               AARCH64_INSN_IMM_MOVNZ);
 365                         break;
 366                 case R_AARCH64_MOVW_PREL_G1_NC:
 367                         overflow_check = false;
 368                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
 369                                               AARCH64_INSN_IMM_MOVKZ);
 370                         break;
 371                 case R_AARCH64_MOVW_PREL_G1:
 372                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
 373                                               AARCH64_INSN_IMM_MOVNZ);
 374                         break;
 375                 case R_AARCH64_MOVW_PREL_G2_NC:
 376                         overflow_check = false;
 377                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
 378                                               AARCH64_INSN_IMM_MOVKZ);
 379                         break;
 380                 case R_AARCH64_MOVW_PREL_G2:
 381                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
 382                                               AARCH64_INSN_IMM_MOVNZ);
 383                         break;
 384                 case R_AARCH64_MOVW_PREL_G3:
 385                         /* We're using the top bits so we can't overflow. */
 386                         overflow_check = false;
 387                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
 388                                               AARCH64_INSN_IMM_MOVNZ);
 389                         break;
 390
 391                 /* Immediate instruction relocations. */
 392                 case R_AARCH64_LD_PREL_LO19:
 393                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
 394                                              AARCH64_INSN_IMM_19);
 395                         break;
 396                 case R_AARCH64_ADR_PREL_LO21:
 397                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
 398                                              AARCH64_INSN_IMM_ADR);
 399                         break;
 400                 case R_AARCH64_ADR_PREL_PG_HI21_NC:
 401                         overflow_check = false;
 402                         fallthrough;
 403                 case R_AARCH64_ADR_PREL_PG_HI21:
 404                         ovf = reloc_insn_adrp(me, sechdrs, loc, val);
 405                         if (ovf && ovf != -ERANGE)
 406                                 return ovf;
 407                         break;
 408                 case R_AARCH64_ADD_ABS_LO12_NC:
 409                 case R_AARCH64_LDST8_ABS_LO12_NC:
 410                         overflow_check = false;
 411                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
 412                                              AARCH64_INSN_IMM_12);
 413                         break;
 414                 case R_AARCH64_LDST16_ABS_LO12_NC:
 415                         overflow_check = false;
 416                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
 417                                              AARCH64_INSN_IMM_12);
 418                         break;
 419                 case R_AARCH64_LDST32_ABS_LO12_NC:
 420                         overflow_check = false;
 421                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
 422                                              AARCH64_INSN_IMM_12);
 423                         break;
 424                 case R_AARCH64_LDST64_ABS_LO12_NC:
 425                         overflow_check = false;
 426                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
 427                                              AARCH64_INSN_IMM_12);
 428                         break;
 429                 case R_AARCH64_LDST128_ABS_LO12_NC:
 430                         overflow_check = false;
 431                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
 432                                              AARCH64_INSN_IMM_12);
 433                         break;
 434                 case R_AARCH64_TSTBR14:
 435                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
 436                                              AARCH64_INSN_IMM_14);
 437                         break;
 438                 case R_AARCH64_CONDBR19:
 439                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
 440                                              AARCH64_INSN_IMM_19);
 441                         break;
 442                 case R_AARCH64_JUMP26:
 443                 case R_AARCH64_CALL26:
 444                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
 445                                              AARCH64_INSN_IMM_26);
 446
 447                         if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
 448                             ovf == -ERANGE) {
 449                                 val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
 450                                 if (!val)
 451                                         return -ENOEXEC;
 452                                 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
 453                                                      26, AARCH64_INSN_IMM_26);
 454                         }
 455                         break;
 456
 457                 default:
 458                         pr_err("module %s: unsupported RELA relocation: %llu\n",
 459                                me->name, ELF64_R_TYPE(rel[i].r_info));
 460                         return -ENOEXEC;
 461                 }
 462
 463                 if (overflow_check && ovf == -ERANGE)
 464                         goto overflow;
 465
 466         }
 467
 468         return 0;
 469
 470 overflow:
 471         pr_err("module %s: overflow in relocation type %d val %Lx\n",
 472                me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
 473         return -ENOEXEC;
 474 }
 475
 476 static const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
 477                                     const Elf_Shdr *sechdrs,
 478                                     const char *name)
 479 {
 480         const Elf_Shdr *s, *se;
 481         const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
 482
 483         for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
 484                 if (strcmp(name, secstrs + s->sh_name) == 0)
 485                         return s;
 486         }
 487
 488         return NULL;
 489 }
 490
 491 static inline void __init_plt(struct plt_entry *plt, unsigned long addr)
 492 {
 493         *plt = get_plt_entry(addr, plt);
 494 }
 495
 496 static int module_init_ftrace_plt(const Elf_Ehdr *hdr,
 497                                   const Elf_Shdr *sechdrs,
 498                                   struct module *mod)
 499 {
 500 #if defined(CONFIG_ARM64_MODULE_PLTS) && defined(CONFIG_DYNAMIC_FTRACE)
 501         const Elf_Shdr *s;
 502         struct plt_entry *plts;
 503
 504         s = find_section(hdr, sechdrs, ".text.ftrace_trampoline");
 505         if (!s)
 506                 return -ENOEXEC;
 507
 508         plts = (void *)s->sh_addr;
 509
 510         __init_plt(&plts[FTRACE_PLT_IDX], FTRACE_ADDR);
 511
 512         if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS))
 513                 __init_plt(&plts[FTRACE_REGS_PLT_IDX], FTRACE_REGS_ADDR);
 514
 515         mod->arch.ftrace_trampolines = plts;
 516 #endif
 517         return 0;
 518 }
 519
 520 int module_finalize(const Elf_Ehdr *hdr,
 521                     const Elf_Shdr *sechdrs,
 522                     struct module *me)
 523 {
 524         const Elf_Shdr *s;
 525         s = find_section(hdr, sechdrs, ".altinstructions");
 526         if (s)
 527                 apply_alternatives_module((void *)s->sh_addr, s->sh_size);
 528
 529         return module_init_ftrace_plt(hdr, sechdrs, me);
 530 }