arch/hexagon/include/asm/pgtable.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Page table support for the Hexagon architecture
   4  *
   5  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef _ASM_PGTABLE_H
   9 #define _ASM_PGTABLE_H
  10
  11 /*
  12  * Page table definitions for Qualcomm Hexagon processor.
  13  */
  14 #include <asm/page.h>
  15 #include <asm-generic/pgtable-nopmd.h>
  16
  17 /* A handy thing to have if one has the RAM. Declared in head.S */
  18 extern unsigned long empty_zero_page;
  19
  20 /*
  21  * The PTE model described here is that of the Hexagon Virtual Machine,
  22  * which autonomously walks 2-level page tables.  At a lower level, we
  23  * also describe the RISCish software-loaded TLB entry structure of
  24  * the underlying Hexagon processor. A kernel built to run on the
  25  * virtual machine has no need to know about the underlying hardware.
  26  */
  27 #include <asm/vm_mmu.h>
  28
  29 /*
  30  * To maximize the comfort level for the PTE manipulation macros,
  31  * define the "well known" architecture-specific bits.
  32  */
  33 #define _PAGE_READ      __HVM_PTE_R
  34 #define _PAGE_WRITE     __HVM_PTE_W
  35 #define _PAGE_EXECUTE   __HVM_PTE_X
  36 #define _PAGE_USER      __HVM_PTE_U
  37
  38 /*
  39  * We have a total of 4 "soft" bits available in the abstract PTE.
  40  * The two mandatory software bits are Dirty and Accessed.
  41  * To make nonlinear swap work according to the more recent
  42  * model, we want a low order "Present" bit to indicate whether
  43  * the PTE describes MMU programming or swap space.
  44  */
  45 #define _PAGE_PRESENT   (1<<0)
  46 #define _PAGE_DIRTY     (1<<1)
  47 #define _PAGE_ACCESSED  (1<<2)
  48
  49 /*
  50  * For now, let's say that Valid and Present are the same thing.
  51  * Alternatively, we could say that it's the "or" of R, W, and X
  52  * permissions.
  53  */
  54 #define _PAGE_VALID     _PAGE_PRESENT
  55
  56 /*
  57  * We're not defining _PAGE_GLOBAL here, since there's no concept
  58  * of global pages or ASIDs exposed to the Hexagon Virtual Machine,
  59  * and we want to use the same page table structures and macros in
  60  * the native kernel as we do in the virtual machine kernel.
  61  * So we'll put up with a bit of inefficiency for now...
  62  */
  63
  64 /*
  65  * Top "FOURTH" level (pgd), which for the Hexagon VM is really
  66  * only the second from the bottom, pgd and pud both being collapsed.
  67  * Each entry represents 4MB of virtual address space, 4K of table
  68  * thus maps the full 4GB.
  69  */
  70 #define PGDIR_SHIFT 22
  71 #define PTRS_PER_PGD 1024
  72
  73 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
  74 #define PGDIR_MASK (~(PGDIR_SIZE-1))
  75
  76 #ifdef CONFIG_PAGE_SIZE_4KB
  77 #define PTRS_PER_PTE 1024
  78 #endif
  79
  80 #ifdef CONFIG_PAGE_SIZE_16KB
  81 #define PTRS_PER_PTE 256
  82 #endif
  83
  84 #ifdef CONFIG_PAGE_SIZE_64KB
  85 #define PTRS_PER_PTE 64
  86 #endif
  87
  88 #ifdef CONFIG_PAGE_SIZE_256KB
  89 #define PTRS_PER_PTE 16
  90 #endif
  91
  92 #ifdef CONFIG_PAGE_SIZE_1MB
  93 #define PTRS_PER_PTE 4
  94 #endif
  95
  96 /*  Any bigger and the PTE disappears.  */
  97 #define pgd_ERROR(e) \
  98         printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\
  99                 pgd_val(e))
 100
 101 /*
 102  * Page Protection Constants. Includes (in this variant) cache attributes.
 103  */
 104 extern unsigned long _dflt_cache_att;
 105
 106 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 107                                 _dflt_cache_att)
 108 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 109                                 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
 110 #define PAGE_COPY       PAGE_READONLY
 111 #define PAGE_EXEC       __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 112                                 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
 113 #define PAGE_COPY_EXEC  PAGE_EXEC
 114 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 115                                 _PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att)
 116 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_READ | \
 117                                 _PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att)
 118
 119
 120 /*
 121  * Aliases for mapping mmap() protection bits to page protections.
 122  * These get used for static initialization, so using the _dflt_cache_att
 123  * variable for the default cache attribute isn't workable. If the
 124  * default gets changed at boot time, the boot option code has to
 125  * update data structures like the protaction_map[] array.
 126  */
 127 #define CACHEDEF        (CACHE_DEFAULT << 6)
 128
 129 /* Private (copy-on-write) page protections. */
 130 #define __P000 __pgprot(_PAGE_PRESENT | _PAGE_USER | CACHEDEF)
 131 #define __P001 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | CACHEDEF)
 132 #define __P010 __P000   /* Write-only copy-on-write */
 133 #define __P011 __P001   /* Read/Write copy-on-write */
 134 #define __P100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 135                         _PAGE_EXECUTE | CACHEDEF)
 136 #define __P101 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_EXECUTE | \
 137                         _PAGE_READ | CACHEDEF)
 138 #define __P110 __P100   /* Write/execute copy-on-write */
 139 #define __P111 __P101   /* Read/Write/Execute, copy-on-write */
 140
 141 /* Shared page protections. */
 142 #define __S000 __P000
 143 #define __S001 __P001
 144 #define __S010 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 145                         _PAGE_WRITE | CACHEDEF)
 146 #define __S011 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 147                         _PAGE_WRITE | CACHEDEF)
 148 #define __S100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 149                         _PAGE_EXECUTE | CACHEDEF)
 150 #define __S101 __P101
 151 #define __S110 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 152                         _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF)
 153 #define __S111 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 154                         _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF)
 155
 156 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];  /* located in head.S */
 157
 158 /* Seems to be zero even in architectures where the zero page is firewalled? */
 159 #define FIRST_USER_ADDRESS 0UL
 160
 161 /*  HUGETLB not working currently  */
 162 #ifdef CONFIG_HUGETLB_PAGE
 163 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE)
 164 #endif
 165
 166 /*
 167  * For now, assume that higher-level code will do TLB/MMU invalidations
 168  * and don't insert that overhead into this low-level function.
 169  */
 170 extern void sync_icache_dcache(pte_t pte);
 171
 172 #define pte_present_exec_user(pte) \
 173         ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \
 174         (_PAGE_EXECUTE | _PAGE_USER))
 175
 176 static inline void set_pte(pte_t *ptep, pte_t pteval)
 177 {
 178         /*  should really be using pte_exec, if it weren't declared later. */
 179         if (pte_present_exec_user(pteval))
 180                 sync_icache_dcache(pteval);
 181
 182         *ptep = pteval;
 183 }
 184
 185 /*
 186  * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid
 187  * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE
 188  * (Linux PTE), the key is to have bits 11..9 all zero.  We'd use 0x7
 189  * as a universal null entry, but some of those least significant bits
 190  * are interpreted by software.
 191  */
 192 #define _NULL_PMD       0x7
 193 #define _NULL_PTE       0x0
 194
 195 static inline void pmd_clear(pmd_t *pmd_entry_ptr)
 196 {
 197          pmd_val(*pmd_entry_ptr) = _NULL_PMD;
 198 }
 199
 200 /*
 201  * Conveniently, a null PTE value is invalid.
 202  */
 203 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 204                                 pte_t *ptep)
 205 {
 206         pte_val(*ptep) = _NULL_PTE;
 207 }
 208
 209 /**
 210  * pmd_none - check if pmd_entry is mapped
 211  * @pmd_entry:  pmd entry
 212  *
 213  * MIPS checks it against that "invalid pte table" thing.
 214  */
 215 static inline int pmd_none(pmd_t pmd)
 216 {
 217         return pmd_val(pmd) == _NULL_PMD;
 218 }
 219
 220 /**
 221  * pmd_present - is there a page table behind this?
 222  * Essentially the inverse of pmd_none.  We maybe
 223  * save an inline instruction by defining it this
 224  * way, instead of simply "!pmd_none".
 225  */
 226 static inline int pmd_present(pmd_t pmd)
 227 {
 228         return pmd_val(pmd) != (unsigned long)_NULL_PMD;
 229 }
 230
 231 /**
 232  * pmd_bad - check if a PMD entry is "bad". That might mean swapped out.
 233  * As we have no known cause of badness, it's null, as it is for many
 234  * architectures.
 235  */
 236 static inline int pmd_bad(pmd_t pmd)
 237 {
 238         return 0;
 239 }
 240
 241 /*
 242  * pmd_page - converts a PMD entry to a page pointer
 243  */
 244 #define pmd_page(pmd)  (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 245 #define pmd_pgtable(pmd) pmd_page(pmd)
 246
 247 /**
 248  * pte_none - check if pte is mapped
 249  * @pte: pte_t entry
 250  */
 251 static inline int pte_none(pte_t pte)
 252 {
 253         return pte_val(pte) == _NULL_PTE;
 254 };
 255
 256 /*
 257  * pte_present - check if page is present
 258  */
 259 static inline int pte_present(pte_t pte)
 260 {
 261         return pte_val(pte) & _PAGE_PRESENT;
 262 }
 263
 264 /* mk_pte - make a PTE out of a page pointer and protection bits */
 265 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
 266
 267 /* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */
 268 #define pte_page(x) pfn_to_page(pte_pfn(x))
 269
 270 /* pte_mkold - mark PTE as not recently accessed */
 271 static inline pte_t pte_mkold(pte_t pte)
 272 {
 273         pte_val(pte) &= ~_PAGE_ACCESSED;
 274         return pte;
 275 }
 276
 277 /* pte_mkyoung - mark PTE as recently accessed */
 278 static inline pte_t pte_mkyoung(pte_t pte)
 279 {
 280         pte_val(pte) |= _PAGE_ACCESSED;
 281         return pte;
 282 }
 283
 284 /* pte_mkclean - mark page as in sync with backing store */
 285 static inline pte_t pte_mkclean(pte_t pte)
 286 {
 287         pte_val(pte) &= ~_PAGE_DIRTY;
 288         return pte;
 289 }
 290
 291 /* pte_mkdirty - mark page as modified */
 292 static inline pte_t pte_mkdirty(pte_t pte)
 293 {
 294         pte_val(pte) |= _PAGE_DIRTY;
 295         return pte;
 296 }
 297
 298 /* pte_young - "is PTE marked as accessed"? */
 299 static inline int pte_young(pte_t pte)
 300 {
 301         return pte_val(pte) & _PAGE_ACCESSED;
 302 }
 303
 304 /* pte_dirty - "is PTE dirty?" */
 305 static inline int pte_dirty(pte_t pte)
 306 {
 307         return pte_val(pte) & _PAGE_DIRTY;
 308 }
 309
 310 /* pte_modify - set protection bits on PTE */
 311 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
 312 {
 313         pte_val(pte) &= PAGE_MASK;
 314         pte_val(pte) |= pgprot_val(prot);
 315         return pte;
 316 }
 317
 318 /* pte_wrprotect - mark page as not writable */
 319 static inline pte_t pte_wrprotect(pte_t pte)
 320 {
 321         pte_val(pte) &= ~_PAGE_WRITE;
 322         return pte;
 323 }
 324
 325 /* pte_mkwrite - mark page as writable */
 326 static inline pte_t pte_mkwrite(pte_t pte)
 327 {
 328         pte_val(pte) |= _PAGE_WRITE;
 329         return pte;
 330 }
 331
 332 /* pte_mkexec - mark PTE as executable */
 333 static inline pte_t pte_mkexec(pte_t pte)
 334 {
 335         pte_val(pte) |= _PAGE_EXECUTE;
 336         return pte;
 337 }
 338
 339 /* pte_read - "is PTE marked as readable?" */
 340 static inline int pte_read(pte_t pte)
 341 {
 342         return pte_val(pte) & _PAGE_READ;
 343 }
 344
 345 /* pte_write - "is PTE marked as writable?" */
 346 static inline int pte_write(pte_t pte)
 347 {
 348         return pte_val(pte) & _PAGE_WRITE;
 349 }
 350
 351
 352 /* pte_exec - "is PTE marked as executable?" */
 353 static inline int pte_exec(pte_t pte)
 354 {
 355         return pte_val(pte) & _PAGE_EXECUTE;
 356 }
 357
 358 /* __pte_to_swp_entry - extract swap entry from PTE */
 359 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 360
 361 /* __swp_entry_to_pte - extract PTE from swap entry */
 362 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
 363
 364 /* pfn_pte - convert page number and protection value to page table entry */
 365 #define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot))
 366
 367 /* pte_pfn - convert pte to page frame number */
 368 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
 369 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
 370
 371 /*
 372  * set_pte_at - update page table and do whatever magic may be
 373  * necessary to make the underlying hardware/firmware take note.
 374  *
 375  * VM may require a virtual instruction to alert the MMU.
 376  */
 377 #define set_pte_at(mm, addr, ptep, pte) set_pte(ptep, pte)
 378
 379 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 380 {
 381         return (unsigned long)__va(pmd_val(pmd) & PAGE_MASK);
 382 }
 383
 384 /* ZERO_PAGE - returns the globally shared zero page */
 385 #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
 386
 387 /*
 388  * Swap/file PTE definitions.  If _PAGE_PRESENT is zero, the rest of the PTE is
 389  * interpreted as swap information.  The remaining free bits are interpreted as
 390  * swap type/offset tuple.  Rather than have the TLB fill handler test
 391  * _PAGE_PRESENT, we're going to reserve the permissions bits and set them to
 392  * all zeros for swap entries, which speeds up the miss handler at the cost of
 393  * 3 bits of offset.  That trade-off can be revisited if necessary, but Hexagon
 394  * processor architecture and target applications suggest a lot of TLB misses
 395  * and not much swap space.
 396  *
 397  * Format of swap PTE:
 398  *      bit     0:      Present (zero)
 399  *      bits    1-5:    swap type (arch independent layer uses 5 bits max)
 400  *      bits    6-9:    bits 3:0 of offset
 401  *      bits    10-12:  effectively _PAGE_PROTNONE (all zero)
 402  *      bits    13-31:  bits 22:4 of swap offset
 403  *
 404  * The split offset makes some of the following macros a little gnarly,
 405  * but there's plenty of precedent for this sort of thing.
 406  */
 407
 408 /* Used for swap PTEs */
 409 #define __swp_type(swp_pte)             (((swp_pte).val >> 1) & 0x1f)
 410
 411 #define __swp_offset(swp_pte) \
 412         ((((swp_pte).val >> 6) & 0xf) | (((swp_pte).val >> 9) & 0x7ffff0))
 413
 414 #define __swp_entry(type, offset) \
 415         ((swp_entry_t)  { \
 416                 ((type << 1) | \
 417                  ((offset & 0x7ffff0) << 9) | ((offset & 0xf) << 6)) })
 418
 419 #endif