arch/m68k/q40/config.c

   1 /*
   2  *  arch/m68k/q40/config.c
   3  *
   4  *  Copyright (C) 1999 Richard Zidlicky
   5  *
   6  * originally based on:
   7  *
   8  *  linux/bvme/config.c
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file README.legal in the main directory of this archive
  12  * for more details.
  13  */
  14
  15 #include <linux/errno.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mm.h>
  19 #include <linux/tty.h>
  20 #include <linux/console.h>
  21 #include <linux/linkage.h>
  22 #include <linux/init.h>
  23 #include <linux/major.h>
  24 #include <linux/serial_reg.h>
  25 #include <linux/rtc.h>
  26 #include <linux/vt_kern.h>
  27 #include <linux/bcd.h>
  28 #include <linux/platform_device.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/bootinfo.h>
  32 #include <asm/setup.h>
  33 #include <asm/irq.h>
  34 #include <asm/traps.h>
  35 #include <asm/machdep.h>
  36 #include <asm/q40_master.h>
  37
  38 extern void q40_init_IRQ(void);
  39 static void q40_get_model(char *model);
  40 extern void q40_sched_init(void);
  41
  42 static int q40_hwclk(int, struct rtc_time *);
  43 static unsigned int q40_get_ss(void);
  44 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
  45 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
  46
  47 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
  48
  49 static void q40_mem_console_write(struct console *co, const char *b,
  50                                   unsigned int count);
  51
  52 extern int ql_ticks;
  53
  54 static struct console q40_console_driver = {
  55         .name   = "debug",
  56         .write  = q40_mem_console_write,
  57         .flags  = CON_PRINTBUFFER,
  58         .index  = -1,
  59 };
  60
  61
  62 /* early debugging function:*/
  63 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
  64 static int _cpleft;
  65
  66 static void q40_mem_console_write(struct console *co, const char *s,
  67                                   unsigned int count)
  68 {
  69         const char *p = s;
  70
  71         if (count < _cpleft) {
  72                 while (count-- > 0) {
  73                         *q40_mem_cptr = *p++;
  74                         q40_mem_cptr += 4;
  75                         _cpleft--;
  76                 }
  77         }
  78 }
  79
  80 static int __init q40_debug_setup(char *arg)
  81 {
  82         /* useful for early debugging stages - writes kernel messages into SRAM */
  83         if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
  84                 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
  85                 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
  86                 register_console(&q40_console_driver);
  87         }
  88         return 0;
  89 }
  90
  91 early_param("debug", q40_debug_setup);
  92
  93 #if 0
  94 void printq40(char *str)
  95 {
  96         int l = strlen(str);
  97         char *p = q40_mem_cptr;
  98
  99         while (l-- > 0 && _cpleft-- > 0) {
 100                 *p = *str++;
 101                 p += 4;
 102         }
 103         q40_mem_cptr = p;
 104 }
 105 #endif
 106
 107 static int halted;
 108
 109 #ifdef CONFIG_HEARTBEAT
 110 static void q40_heartbeat(int on)
 111 {
 112         if (halted)
 113                 return;
 114
 115         if (on)
 116                 Q40_LED_ON();
 117         else
 118                 Q40_LED_OFF();
 119 }
 120 #endif
 121
 122 static void q40_reset(void)
 123 {
 124         halted = 1;
 125         pr_info("*******************************************\n"
 126                 "Called q40_reset : press the RESET button!!\n"
 127                 "*******************************************\n");
 128         Q40_LED_ON();
 129         while (1)
 130                 ;
 131 }
 132
 133 static void q40_halt(void)
 134 {
 135         halted = 1;
 136         pr_info("*******************\n"
 137                 "  Called q40_halt\n"
 138                 "*******************\n");
 139         Q40_LED_ON();
 140         while (1)
 141                 ;
 142 }
 143
 144 static void q40_get_model(char *model)
 145 {
 146         sprintf(model, "Q40");
 147 }
 148
 149 static unsigned int serports[] =
 150 {
 151         0x3f8,0x2f8,0x3e8,0x2e8,0
 152 };
 153
 154 static void __init q40_disable_irqs(void)
 155 {
 156         unsigned i, j;
 157
 158         j = 0;
 159         while ((i = serports[j++]))
 160                 outb(0, i + UART_IER);
 161         master_outb(0, EXT_ENABLE_REG);
 162         master_outb(0, KEY_IRQ_ENABLE_REG);
 163 }
 164
 165 void __init config_q40(void)
 166 {
 167         mach_sched_init = q40_sched_init;
 168
 169         mach_init_IRQ = q40_init_IRQ;
 170         mach_hwclk = q40_hwclk;
 171         mach_get_ss = q40_get_ss;
 172         mach_get_rtc_pll = q40_get_rtc_pll;
 173         mach_set_rtc_pll = q40_set_rtc_pll;
 174
 175         mach_reset = q40_reset;
 176         mach_get_model = q40_get_model;
 177
 178 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
 179         mach_beep = q40_mksound;
 180 #endif
 181 #ifdef CONFIG_HEARTBEAT
 182         mach_heartbeat = q40_heartbeat;
 183 #endif
 184         mach_halt = q40_halt;
 185
 186         /* disable a few things that SMSQ might have left enabled */
 187         q40_disable_irqs();
 188 }
 189
 190
 191 int __init q40_parse_bootinfo(const struct bi_record *rec)
 192 {
 193         return 1;
 194 }
 195
 196 /*
 197  * Looks like op is non-zero for setting the clock, and zero for
 198  * reading the clock.
 199  *
 200  *  struct hwclk_time {
 201  *         unsigned        sec;       0..59
 202  *         unsigned        min;       0..59
 203  *         unsigned        hour;      0..23
 204  *         unsigned        day;       1..31
 205  *         unsigned        mon;       0..11
 206  *         unsigned        year;      00...
 207  *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
 208  * };
 209  */
 210
 211 static int q40_hwclk(int op, struct rtc_time *t)
 212 {
 213         if (op) {
 214                 /* Write.... */
 215                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 216
 217                 Q40_RTC_SECS = bin2bcd(t->tm_sec);
 218                 Q40_RTC_MINS = bin2bcd(t->tm_min);
 219                 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
 220                 Q40_RTC_DATE = bin2bcd(t->tm_mday);
 221                 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
 222                 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
 223                 if (t->tm_wday >= 0)
 224                         Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
 225
 226                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 227         } else {
 228                 /* Read....  */
 229                 Q40_RTC_CTRL |= Q40_RTC_READ;
 230
 231                 t->tm_year = bcd2bin (Q40_RTC_YEAR);
 232                 t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
 233                 t->tm_mday = bcd2bin (Q40_RTC_DATE);
 234                 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
 235                 t->tm_min  = bcd2bin (Q40_RTC_MINS);
 236                 t->tm_sec  = bcd2bin (Q40_RTC_SECS);
 237
 238                 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 239
 240                 if (t->tm_year < 70)
 241                         t->tm_year += 100;
 242                 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static unsigned int q40_get_ss(void)
 249 {
 250         return bcd2bin(Q40_RTC_SECS);
 251 }
 252
 253 /* get and set PLL calibration of RTC clock */
 254 #define Q40_RTC_PLL_MASK ((1<<5)-1)
 255 #define Q40_RTC_PLL_SIGN (1<<5)
 256
 257 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
 258 {
 259         int tmp = Q40_RTC_CTRL;
 260
 261         pll->pll_ctrl = 0;
 262         pll->pll_value = tmp & Q40_RTC_PLL_MASK;
 263         if (tmp & Q40_RTC_PLL_SIGN)
 264                 pll->pll_value = -pll->pll_value;
 265         pll->pll_max = 31;
 266         pll->pll_min = -31;
 267         pll->pll_posmult = 512;
 268         pll->pll_negmult = 256;
 269         pll->pll_clock = 125829120;
 270
 271         return 0;
 272 }
 273
 274 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
 275 {
 276         if (!pll->pll_ctrl) {
 277                 /* the docs are a bit unclear so I am doublesetting */
 278                 /* RTC_WRITE here ... */
 279                 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
 280                           Q40_RTC_WRITE;
 281                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 282                 Q40_RTC_CTRL = tmp;
 283                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 284                 return 0;
 285         } else
 286                 return -EINVAL;
 287 }
 288
 289 static __init int q40_add_kbd_device(void)
 290 {
 291         struct platform_device *pdev;
 292
 293         if (!MACH_IS_Q40)
 294                 return -ENODEV;
 295
 296         pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
 297         return PTR_ERR_OR_ZERO(pdev);
 298 }
 299 arch_initcall(q40_add_kbd_device);