2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/sched.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched_clock.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/timecounter.h>
22 #include <asm/cpuinfo.h>
24 static void __iomem
*timer_baseaddr
;
26 static unsigned int freq_div_hz
;
27 static unsigned int timer_clock_freq
;
36 #define TCSR_MDT (1<<0)
37 #define TCSR_UDT (1<<1)
38 #define TCSR_GENT (1<<2)
39 #define TCSR_CAPT (1<<3)
40 #define TCSR_ARHT (1<<4)
41 #define TCSR_LOAD (1<<5)
42 #define TCSR_ENIT (1<<6)
43 #define TCSR_ENT (1<<7)
44 #define TCSR_TINT (1<<8)
45 #define TCSR_PWMA (1<<9)
46 #define TCSR_ENALL (1<<10)
48 static unsigned int (*read_fn
)(void __iomem
*);
49 static void (*write_fn
)(u32
, void __iomem
*);
51 static void timer_write32(u32 val
, void __iomem
*addr
)
56 static unsigned int timer_read32(void __iomem
*addr
)
58 return ioread32(addr
);
61 static void timer_write32_be(u32 val
, void __iomem
*addr
)
63 iowrite32be(val
, addr
);
66 static unsigned int timer_read32_be(void __iomem
*addr
)
68 return ioread32be(addr
);
71 static inline void xilinx_timer0_stop(void)
73 write_fn(read_fn(timer_baseaddr
+ TCSR0
) & ~TCSR_ENT
,
74 timer_baseaddr
+ TCSR0
);
77 static inline void xilinx_timer0_start_periodic(unsigned long load_val
)
81 /* loading value to timer reg */
82 write_fn(load_val
, timer_baseaddr
+ TLR0
);
84 /* load the initial value */
85 write_fn(TCSR_LOAD
, timer_baseaddr
+ TCSR0
);
87 /* see timer data sheet for detail
88 * !ENALL - don't enable 'em all
90 * TINT - clear interrupt status
91 * ENT- enable timer itself
92 * ENIT - enable interrupt
93 * !LOAD - clear the bit to let go
95 * !CAPT - no external trigger
96 * !GENT - no external signal
97 * UDT - set the timer as down counter
98 * !MDT0 - generate mode
100 write_fn(TCSR_TINT
|TCSR_ENIT
|TCSR_ENT
|TCSR_ARHT
|TCSR_UDT
,
101 timer_baseaddr
+ TCSR0
);
104 static inline void xilinx_timer0_start_oneshot(unsigned long load_val
)
108 /* loading value to timer reg */
109 write_fn(load_val
, timer_baseaddr
+ TLR0
);
111 /* load the initial value */
112 write_fn(TCSR_LOAD
, timer_baseaddr
+ TCSR0
);
114 write_fn(TCSR_TINT
|TCSR_ENIT
|TCSR_ENT
|TCSR_ARHT
|TCSR_UDT
,
115 timer_baseaddr
+ TCSR0
);
118 static int xilinx_timer_set_next_event(unsigned long delta
,
119 struct clock_event_device
*dev
)
121 pr_debug("%s: next event, delta %x\n", __func__
, (u32
)delta
);
122 xilinx_timer0_start_oneshot(delta
);
126 static int xilinx_timer_shutdown(struct clock_event_device
*evt
)
128 pr_info("%s\n", __func__
);
129 xilinx_timer0_stop();
133 static int xilinx_timer_set_periodic(struct clock_event_device
*evt
)
135 pr_info("%s\n", __func__
);
136 xilinx_timer0_start_periodic(freq_div_hz
);
140 static struct clock_event_device clockevent_xilinx_timer
= {
141 .name
= "xilinx_clockevent",
142 .features
= CLOCK_EVT_FEAT_ONESHOT
|
143 CLOCK_EVT_FEAT_PERIODIC
,
146 .set_next_event
= xilinx_timer_set_next_event
,
147 .set_state_shutdown
= xilinx_timer_shutdown
,
148 .set_state_periodic
= xilinx_timer_set_periodic
,
151 static inline void timer_ack(void)
153 write_fn(read_fn(timer_baseaddr
+ TCSR0
), timer_baseaddr
+ TCSR0
);
156 static irqreturn_t
timer_interrupt(int irq
, void *dev_id
)
158 struct clock_event_device
*evt
= &clockevent_xilinx_timer
;
160 evt
->event_handler(evt
);
164 static __init
int xilinx_clockevent_init(void)
166 clockevent_xilinx_timer
.mult
=
167 div_sc(timer_clock_freq
, NSEC_PER_SEC
,
168 clockevent_xilinx_timer
.shift
);
169 clockevent_xilinx_timer
.max_delta_ns
=
170 clockevent_delta2ns((u32
)~0, &clockevent_xilinx_timer
);
171 clockevent_xilinx_timer
.max_delta_ticks
= (u32
)~0;
172 clockevent_xilinx_timer
.min_delta_ns
=
173 clockevent_delta2ns(1, &clockevent_xilinx_timer
);
174 clockevent_xilinx_timer
.min_delta_ticks
= 1;
175 clockevent_xilinx_timer
.cpumask
= cpumask_of(0);
176 clockevents_register_device(&clockevent_xilinx_timer
);
181 static u64
xilinx_clock_read(void)
183 return read_fn(timer_baseaddr
+ TCR1
);
186 static u64
xilinx_read(struct clocksource
*cs
)
188 /* reading actual value of timer 1 */
189 return (u64
)xilinx_clock_read();
192 static struct timecounter xilinx_tc
= {
196 static u64
xilinx_cc_read(const struct cyclecounter
*cc
)
198 return xilinx_read(NULL
);
201 static struct cyclecounter xilinx_cc
= {
202 .read
= xilinx_cc_read
,
203 .mask
= CLOCKSOURCE_MASK(32),
207 static int __init
init_xilinx_timecounter(void)
209 xilinx_cc
.mult
= div_sc(timer_clock_freq
, NSEC_PER_SEC
,
212 timecounter_init(&xilinx_tc
, &xilinx_cc
, sched_clock());
217 static struct clocksource clocksource_microblaze
= {
218 .name
= "xilinx_clocksource",
221 .mask
= CLOCKSOURCE_MASK(32),
222 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
225 static int __init
xilinx_clocksource_init(void)
229 ret
= clocksource_register_hz(&clocksource_microblaze
,
232 pr_err("failed to register clocksource");
237 write_fn(read_fn(timer_baseaddr
+ TCSR1
) & ~TCSR_ENT
,
238 timer_baseaddr
+ TCSR1
);
239 /* start timer1 - up counting without interrupt */
240 write_fn(TCSR_TINT
|TCSR_ENT
|TCSR_ARHT
, timer_baseaddr
+ TCSR1
);
242 /* register timecounter - for ftrace support */
243 return init_xilinx_timecounter();
246 static int __init
xilinx_timer_init(struct device_node
*timer
)
249 static int initialized
;
259 timer_baseaddr
= of_iomap(timer
, 0);
260 if (!timer_baseaddr
) {
261 pr_err("ERROR: invalid timer base address\n");
265 write_fn
= timer_write32
;
266 read_fn
= timer_read32
;
268 write_fn(TCSR_MDT
, timer_baseaddr
+ TCSR0
);
269 if (!(read_fn(timer_baseaddr
+ TCSR0
) & TCSR_MDT
)) {
270 write_fn
= timer_write32_be
;
271 read_fn
= timer_read32_be
;
274 irq
= irq_of_parse_and_map(timer
, 0);
276 pr_err("Failed to parse and map irq");
280 of_property_read_u32(timer
, "xlnx,one-timer-only", &timer_num
);
282 pr_err("Please enable two timers in HW\n");
286 pr_info("%pOF: irq=%d\n", timer
, irq
);
288 clk
= of_clk_get(timer
, 0);
290 pr_err("ERROR: timer CCF input clock not found\n");
291 /* If there is clock-frequency property than use it */
292 of_property_read_u32(timer
, "clock-frequency",
295 timer_clock_freq
= clk_get_rate(clk
);
298 if (!timer_clock_freq
) {
299 pr_err("ERROR: Using CPU clock frequency\n");
300 timer_clock_freq
= cpuinfo
.cpu_clock_freq
;
303 freq_div_hz
= timer_clock_freq
/ HZ
;
305 ret
= request_irq(irq
, timer_interrupt
, IRQF_TIMER
, "timer",
306 &clockevent_xilinx_timer
);
308 pr_err("Failed to setup IRQ");
312 ret
= xilinx_clocksource_init();
316 ret
= xilinx_clockevent_init();
320 sched_clock_register(xilinx_clock_read
, 32, timer_clock_freq
);
325 TIMER_OF_DECLARE(xilinx_timer
, "xlnx,xps-timer-1.00.a",