arch/mips/alchemy/devboards/db1550.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Alchemy Db1550/Pb1550 board support
   4  *
   5  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/gpio.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/platnand.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/spi/flash.h>
  21 #include <asm/bootinfo.h>
  22 #include <asm/mach-au1x00/au1000.h>
  23 #include <asm/mach-au1x00/gpio-au1000.h>
  24 #include <asm/mach-au1x00/au1xxx_eth.h>
  25 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  26 #include <asm/mach-au1x00/au1xxx_psc.h>
  27 #include <asm/mach-au1x00/au1550_spi.h>
  28 #include <asm/mach-au1x00/au1550nd.h>
  29 #include <asm/mach-db1x00/bcsr.h>
  30 #include <prom.h>
  31 #include "platform.h"
  32
  33 static void __init db1550_hw_setup(void)
  34 {
  35         void __iomem *base;
  36         unsigned long v;
  37
  38         /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
  39          * as well as PSC1_SYNC for AC97 on PB1550.
  40          */
  41         v = alchemy_rdsys(AU1000_SYS_PINFUNC);
  42         alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
  43
  44         /* reset the AC97 codec now, the reset time in the psc-ac97 driver
  45          * is apparently too short although it's ridiculous as it is.
  46          */
  47         base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
  48         __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
  49                      base + PSC_SEL_OFFSET);
  50         __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
  51         wmb();
  52         __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
  53         wmb();
  54 }
  55
  56 int __init db1550_board_setup(void)
  57 {
  58         unsigned short whoami;
  59
  60         bcsr_init(DB1550_BCSR_PHYS_ADDR,
  61                   DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
  62
  63         whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
  64         switch (BCSR_WHOAMI_BOARD(whoami)) {
  65         case BCSR_WHOAMI_PB1550_SDR:
  66         case BCSR_WHOAMI_PB1550_DDR:
  67                 bcsr_init(PB1550_BCSR_PHYS_ADDR,
  68                           PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
  69         case BCSR_WHOAMI_DB1550:
  70                 break;
  71         default:
  72                 return -ENODEV;
  73         }
  74
  75         pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "       \
  76                 "Daughtercard ID %d\n", get_system_type(),
  77                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
  78
  79         db1550_hw_setup();
  80         return 0;
  81 }
  82
  83 /*****************************************************************************/
  84
  85 static u64 au1550_all_dmamask = DMA_BIT_MASK(32);
  86
  87 static struct mtd_partition db1550_spiflash_parts[] = {
  88         {
  89                 .name   = "spi_flash",
  90                 .offset = 0,
  91                 .size   = MTDPART_SIZ_FULL,
  92         },
  93 };
  94
  95 static struct flash_platform_data db1550_spiflash_data = {
  96         .name           = "s25fl010",
  97         .parts          = db1550_spiflash_parts,
  98         .nr_parts       = ARRAY_SIZE(db1550_spiflash_parts),
  99         .type           = "m25p10",
 100 };
 101
 102 static struct spi_board_info db1550_spi_devs[] __initdata = {
 103         {
 104                 /* TI TMP121AIDBVR temp sensor */
 105                 .modalias       = "tmp121",
 106                 .max_speed_hz   = 2400000,
 107                 .bus_num        = 0,
 108                 .chip_select    = 0,
 109                 .mode           = SPI_MODE_0,
 110         },
 111         {
 112                 /* Spansion S25FL001D0FMA SPI flash */
 113                 .modalias       = "m25p80",
 114                 .max_speed_hz   = 2400000,
 115                 .bus_num        = 0,
 116                 .chip_select    = 1,
 117                 .mode           = SPI_MODE_0,
 118                 .platform_data  = &db1550_spiflash_data,
 119         },
 120 };
 121
 122 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
 123         { I2C_BOARD_INFO("24c04",  0x52),}, /* AT24C04-10 I2C eeprom */
 124         { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
 125         { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
 126 };
 127
 128 /**********************************************************************/
 129
 130 static void au1550_nand_cmd_ctrl(struct nand_chip *this, int cmd,
 131                                  unsigned int ctrl)
 132 {
 133         unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
 134
 135         ioaddr &= 0xffffff00;
 136
 137         if (ctrl & NAND_CLE) {
 138                 ioaddr += MEM_STNAND_CMD;
 139         } else if (ctrl & NAND_ALE) {
 140                 ioaddr += MEM_STNAND_ADDR;
 141         } else {
 142                 /* assume we want to r/w real data  by default */
 143                 ioaddr += MEM_STNAND_DATA;
 144         }
 145         this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
 146         if (cmd != NAND_CMD_NONE) {
 147                 __raw_writeb(cmd, this->legacy.IO_ADDR_W);
 148                 wmb();
 149         }
 150 }
 151
 152 static int au1550_nand_device_ready(struct nand_chip *this)
 153 {
 154         return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 155 }
 156
 157 static struct mtd_partition db1550_nand_parts[] = {
 158         {
 159                 .name   = "NAND FS 0",
 160                 .offset = 0,
 161                 .size   = 8 * 1024 * 1024,
 162         },
 163         {
 164                 .name   = "NAND FS 1",
 165                 .offset = MTDPART_OFS_APPEND,
 166                 .size   = MTDPART_SIZ_FULL
 167         },
 168 };
 169
 170 struct platform_nand_data db1550_nand_platdata = {
 171         .chip = {
 172                 .nr_chips       = 1,
 173                 .chip_offset    = 0,
 174                 .nr_partitions  = ARRAY_SIZE(db1550_nand_parts),
 175                 .partitions     = db1550_nand_parts,
 176                 .chip_delay     = 20,
 177         },
 178         .ctrl = {
 179                 .dev_ready      = au1550_nand_device_ready,
 180                 .cmd_ctrl       = au1550_nand_cmd_ctrl,
 181         },
 182 };
 183
 184 static struct resource db1550_nand_res[] = {
 185         [0] = {
 186                 .start  = 0x20000000,
 187                 .end    = 0x200000ff,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190 };
 191
 192 static struct platform_device db1550_nand_dev = {
 193         .name           = "gen_nand",
 194         .num_resources  = ARRAY_SIZE(db1550_nand_res),
 195         .resource       = db1550_nand_res,
 196         .id             = -1,
 197         .dev            = {
 198                 .platform_data = &db1550_nand_platdata,
 199         }
 200 };
 201
 202 static struct au1550nd_platdata pb1550_nand_pd = {
 203         .parts          = db1550_nand_parts,
 204         .num_parts      = ARRAY_SIZE(db1550_nand_parts),
 205         .devwidth       = 0,    /* x8 NAND default, needs fixing up */
 206 };
 207
 208 static struct platform_device pb1550_nand_dev = {
 209         .name           = "au1550-nand",
 210         .id             = -1,
 211         .resource       = db1550_nand_res,
 212         .num_resources  = ARRAY_SIZE(db1550_nand_res),
 213         .dev            = {
 214                 .platform_data  = &pb1550_nand_pd,
 215         },
 216 };
 217
 218 static void __init pb1550_nand_setup(void)
 219 {
 220         int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
 221                             ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
 222
 223         gpio_direction_input(206);      /* de-assert NAND CS# */
 224         switch (boot_swapboot) {
 225         case 0: case 2: case 8: case 0xC: case 0xD:
 226                 /* x16 NAND Flash */
 227                 pb1550_nand_pd.devwidth = 1;
 228                 fallthrough;
 229         case 1: case 3: case 9: case 0xE: case 0xF:
 230                 /* x8 NAND, already set up */
 231                 platform_device_register(&pb1550_nand_dev);
 232         }
 233 }
 234
 235 /**********************************************************************/
 236
 237 static struct resource au1550_psc0_res[] = {
 238         [0] = {
 239                 .start  = AU1550_PSC0_PHYS_ADDR,
 240                 .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = AU1550_PSC0_INT,
 245                 .end    = AU1550_PSC0_INT,
 246                 .flags  = IORESOURCE_IRQ,
 247         },
 248         [2] = {
 249                 .start  = AU1550_DSCR_CMD0_PSC0_TX,
 250                 .end    = AU1550_DSCR_CMD0_PSC0_TX,
 251                 .flags  = IORESOURCE_DMA,
 252         },
 253         [3] = {
 254                 .start  = AU1550_DSCR_CMD0_PSC0_RX,
 255                 .end    = AU1550_DSCR_CMD0_PSC0_RX,
 256                 .flags  = IORESOURCE_DMA,
 257         },
 258 };
 259
 260 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
 261 {
 262         if (cs)
 263                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
 264         else
 265                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
 266 }
 267
 268 static struct au1550_spi_info db1550_spi_platdata = {
 269         .mainclk_hz     = 48000000,     /* PSC0 clock: max. 2.4MHz SPI clk */
 270         .num_chipselect = 2,
 271         .activate_cs    = db1550_spi_cs_en,
 272 };
 273
 274
 275 static struct platform_device db1550_spi_dev = {
 276         .dev    = {
 277                 .dma_mask               = &au1550_all_dmamask,
 278                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 279                 .platform_data          = &db1550_spi_platdata,
 280         },
 281         .name           = "au1550-spi",
 282         .id             = 0,    /* bus number */
 283         .num_resources  = ARRAY_SIZE(au1550_psc0_res),
 284         .resource       = au1550_psc0_res,
 285 };
 286
 287 /**********************************************************************/
 288
 289 static struct resource au1550_psc1_res[] = {
 290         [0] = {
 291                 .start  = AU1550_PSC1_PHYS_ADDR,
 292                 .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
 293                 .flags  = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start  = AU1550_PSC1_INT,
 297                 .end    = AU1550_PSC1_INT,
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300         [2] = {
 301                 .start  = AU1550_DSCR_CMD0_PSC1_TX,
 302                 .end    = AU1550_DSCR_CMD0_PSC1_TX,
 303                 .flags  = IORESOURCE_DMA,
 304         },
 305         [3] = {
 306                 .start  = AU1550_DSCR_CMD0_PSC1_RX,
 307                 .end    = AU1550_DSCR_CMD0_PSC1_RX,
 308                 .flags  = IORESOURCE_DMA,
 309         },
 310 };
 311
 312 static struct platform_device db1550_ac97_dev = {
 313         .name           = "au1xpsc_ac97",
 314         .id             = 1,    /* PSC ID */
 315         .num_resources  = ARRAY_SIZE(au1550_psc1_res),
 316         .resource       = au1550_psc1_res,
 317 };
 318
 319
 320 static struct resource au1550_psc2_res[] = {
 321         [0] = {
 322                 .start  = AU1550_PSC2_PHYS_ADDR,
 323                 .end    = AU1550_PSC2_PHYS_ADDR + 0xfff,
 324                 .flags  = IORESOURCE_MEM,
 325         },
 326         [1] = {
 327                 .start  = AU1550_PSC2_INT,
 328                 .end    = AU1550_PSC2_INT,
 329                 .flags  = IORESOURCE_IRQ,
 330         },
 331         [2] = {
 332                 .start  = AU1550_DSCR_CMD0_PSC2_TX,
 333                 .end    = AU1550_DSCR_CMD0_PSC2_TX,
 334                 .flags  = IORESOURCE_DMA,
 335         },
 336         [3] = {
 337                 .start  = AU1550_DSCR_CMD0_PSC2_RX,
 338                 .end    = AU1550_DSCR_CMD0_PSC2_RX,
 339                 .flags  = IORESOURCE_DMA,
 340         },
 341 };
 342
 343 static struct platform_device db1550_i2c_dev = {
 344         .name           = "au1xpsc_smbus",
 345         .id             = 0,    /* bus number */
 346         .num_resources  = ARRAY_SIZE(au1550_psc2_res),
 347         .resource       = au1550_psc2_res,
 348 };
 349
 350 /**********************************************************************/
 351
 352 static struct resource au1550_psc3_res[] = {
 353         [0] = {
 354                 .start  = AU1550_PSC3_PHYS_ADDR,
 355                 .end    = AU1550_PSC3_PHYS_ADDR + 0xfff,
 356                 .flags  = IORESOURCE_MEM,
 357         },
 358         [1] = {
 359                 .start  = AU1550_PSC3_INT,
 360                 .end    = AU1550_PSC3_INT,
 361                 .flags  = IORESOURCE_IRQ,
 362         },
 363         [2] = {
 364                 .start  = AU1550_DSCR_CMD0_PSC3_TX,
 365                 .end    = AU1550_DSCR_CMD0_PSC3_TX,
 366                 .flags  = IORESOURCE_DMA,
 367         },
 368         [3] = {
 369                 .start  = AU1550_DSCR_CMD0_PSC3_RX,
 370                 .end    = AU1550_DSCR_CMD0_PSC3_RX,
 371                 .flags  = IORESOURCE_DMA,
 372         },
 373 };
 374
 375 static struct platform_device db1550_i2s_dev = {
 376         .name           = "au1xpsc_i2s",
 377         .id             = 3,    /* PSC ID */
 378         .num_resources  = ARRAY_SIZE(au1550_psc3_res),
 379         .resource       = au1550_psc3_res,
 380 };
 381
 382 /**********************************************************************/
 383
 384 static struct platform_device db1550_stac_dev = {
 385         .name           = "ac97-codec",
 386         .id             = 1,    /* on PSC1 */
 387 };
 388
 389 static struct platform_device db1550_ac97dma_dev = {
 390         .name           = "au1xpsc-pcm",
 391         .id             = 1,    /* on PSC3 */
 392 };
 393
 394 static struct platform_device db1550_i2sdma_dev = {
 395         .name           = "au1xpsc-pcm",
 396         .id             = 3,    /* on PSC3 */
 397 };
 398
 399 static struct platform_device db1550_sndac97_dev = {
 400         .name           = "db1550-ac97",
 401         .dev = {
 402                 .dma_mask               = &au1550_all_dmamask,
 403                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 404         },
 405 };
 406
 407 static struct platform_device db1550_sndi2s_dev = {
 408         .name           = "db1550-i2s",
 409         .dev = {
 410                 .dma_mask               = &au1550_all_dmamask,
 411                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 412         },
 413 };
 414
 415 /**********************************************************************/
 416
 417 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 418 {
 419         if ((slot < 11) || (slot > 13) || pin == 0)
 420                 return -1;
 421         if (slot == 11)
 422                 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
 423         if (slot == 12) {
 424                 switch (pin) {
 425                 case 1: return AU1550_PCI_INTB;
 426                 case 2: return AU1550_PCI_INTC;
 427                 case 3: return AU1550_PCI_INTD;
 428                 case 4: return AU1550_PCI_INTA;
 429                 }
 430         }
 431         if (slot == 13) {
 432                 switch (pin) {
 433                 case 1: return AU1550_PCI_INTA;
 434                 case 2: return AU1550_PCI_INTB;
 435                 case 3: return AU1550_PCI_INTC;
 436                 case 4: return AU1550_PCI_INTD;
 437                 }
 438         }
 439         return -1;
 440 }
 441
 442 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 443 {
 444         if ((slot < 12) || (slot > 13) || pin == 0)
 445                 return -1;
 446         if (slot == 12) {
 447                 switch (pin) {
 448                 case 1: return AU1500_PCI_INTB;
 449                 case 2: return AU1500_PCI_INTC;
 450                 case 3: return AU1500_PCI_INTD;
 451                 case 4: return AU1500_PCI_INTA;
 452                 }
 453         }
 454         if (slot == 13) {
 455                 switch (pin) {
 456                 case 1: return AU1500_PCI_INTA;
 457                 case 2: return AU1500_PCI_INTB;
 458                 case 3: return AU1500_PCI_INTC;
 459                 case 4: return AU1500_PCI_INTD;
 460                 }
 461         }
 462         return -1;
 463 }
 464
 465 static struct resource alchemy_pci_host_res[] = {
 466         [0] = {
 467                 .start  = AU1500_PCI_PHYS_ADDR,
 468                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 469                 .flags  = IORESOURCE_MEM,
 470         },
 471 };
 472
 473 static struct alchemy_pci_platdata db1550_pci_pd = {
 474         .board_map_irq  = db1550_map_pci_irq,
 475 };
 476
 477 static struct platform_device db1550_pci_host_dev = {
 478         .dev.platform_data = &db1550_pci_pd,
 479         .name           = "alchemy-pci",
 480         .id             = 0,
 481         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 482         .resource       = alchemy_pci_host_res,
 483 };
 484
 485 /**********************************************************************/
 486
 487 static struct platform_device *db1550_devs[] __initdata = {
 488         &db1550_i2c_dev,
 489         &db1550_ac97_dev,
 490         &db1550_spi_dev,
 491         &db1550_i2s_dev,
 492         &db1550_stac_dev,
 493         &db1550_ac97dma_dev,
 494         &db1550_i2sdma_dev,
 495         &db1550_sndac97_dev,
 496         &db1550_sndi2s_dev,
 497 };
 498
 499 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
 500 int __init db1550_pci_setup(int id)
 501 {
 502         if (id)
 503                 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
 504         return platform_device_register(&db1550_pci_host_dev);
 505 }
 506
 507 static void __init db1550_devices(void)
 508 {
 509         alchemy_gpio_direction_output(203, 0);  /* red led on */
 510
 511         irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
 512         irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
 513         irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
 514         irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
 515         irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
 516         irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
 517
 518         db1x_register_pcmcia_socket(
 519                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 520                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 521                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 522                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 523                 AU1000_PCMCIA_IO_PHYS_ADDR,
 524                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 525                 AU1550_GPIO3_INT, 0,
 526                 /*AU1550_GPIO21_INT*/0, 0, 0);
 527
 528         db1x_register_pcmcia_socket(
 529                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 530                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 531                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 532                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 533                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 534                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 535                 AU1550_GPIO5_INT, 1,
 536                 /*AU1550_GPIO22_INT*/0, 0, 1);
 537
 538         platform_device_register(&db1550_nand_dev);
 539
 540         alchemy_gpio_direction_output(202, 0);  /* green led on */
 541 }
 542
 543 static void __init pb1550_devices(void)
 544 {
 545         irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
 546         irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
 547         irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
 548
 549         /* enable both PCMCIA card irqs in the shared line */
 550         alchemy_gpio2_enable_int(201);  /* socket 0 card irq */
 551         alchemy_gpio2_enable_int(202);  /* socket 1 card irq */
 552
 553         /* Pb1550, like all others, also has statuschange irqs; however they're
 554         * wired up on one of the Au1550's shared GPIO201_205 line, which also
 555         * services the PCMCIA card interrupts.  So we ignore statuschange and
 556         * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
 557         * drivers are used to shared irqs and b) statuschange isn't really use-
 558         * ful anyway.
 559         */
 560         db1x_register_pcmcia_socket(
 561                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 562                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 563                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 564                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 565                 AU1000_PCMCIA_IO_PHYS_ADDR,
 566                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 567                 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
 568
 569         db1x_register_pcmcia_socket(
 570                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
 571                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
 572                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
 573                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
 574                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008000000,
 575                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
 576                 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
 577
 578         pb1550_nand_setup();
 579 }
 580
 581 int __init db1550_dev_setup(void)
 582 {
 583         int swapped, id;
 584         struct clk *c;
 585
 586         id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
 587
 588         i2c_register_board_info(0, db1550_i2c_devs,
 589                                 ARRAY_SIZE(db1550_i2c_devs));
 590         spi_register_board_info(db1550_spi_devs,
 591                                 ARRAY_SIZE(db1550_i2c_devs));
 592
 593         c = clk_get(NULL, "psc0_intclk");
 594         if (!IS_ERR(c)) {
 595                 clk_set_rate(c, 50000000);
 596                 clk_prepare_enable(c);
 597                 clk_put(c);
 598         }
 599         c = clk_get(NULL, "psc2_intclk");
 600         if (!IS_ERR(c)) {
 601                 clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
 602                 clk_prepare_enable(c);
 603                 clk_put(c);
 604         }
 605
 606         /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
 607         __raw_writel(PSC_SEL_CLK_SERCLK,
 608             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
 609         wmb();
 610         __raw_writel(PSC_SEL_CLK_SERCLK,
 611             (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
 612         wmb();
 613         /* SPI/I2C use internally supplied 50MHz source */
 614         __raw_writel(PSC_SEL_CLK_INTCLK,
 615             (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
 616         wmb();
 617         __raw_writel(PSC_SEL_CLK_INTCLK,
 618             (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
 619         wmb();
 620
 621         id ? pb1550_devices() : db1550_devices();
 622
 623         swapped = bcsr_read(BCSR_STATUS) &
 624                (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
 625         db1x_register_norflash(128 << 20, 4, swapped);
 626
 627         return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
 628 }