arch/mips/fw/arc/promlib.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
   7  * Compatibility with board caches, Ulf Carlsson
   8  */
   9 #include <linux/kernel.h>
  10 #include <asm/sgialib.h>
  11 #include <asm/bcache.h>
  12 #include <asm/setup.h>
  13
  14 #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
  15 /*
  16  * For 64bit kernels working with a 32bit ARC PROM pointer arguments
  17  * for ARC calls need to reside in CKEG0/1. But as soon as the kernel
  18  * switches to it's first kernel thread stack is set to an address in
  19  * XKPHYS, so anything on stack can't be used anymore. This is solved
  20  * by using a * static declartion variables are put into BSS, which is
  21  * linked to a CKSEG0 address. Since this is only used on UP platforms
  22  * there is not spinlock needed
  23  */
  24 #define O32_STATIC      static
  25 #else
  26 #define O32_STATIC
  27 #endif
  28
  29 /*
  30  * IP22 boardcache is not compatible with board caches.  Thus we disable it
  31  * during romvec action.  Since r4xx0.c is always compiled and linked with your
  32  * kernel, this shouldn't cause any harm regardless what MIPS processor you
  33  * have.
  34  *
  35  * The ARC write and read functions seem to interfere with the serial lines
  36  * in some way. You should be careful with them.
  37  */
  38
  39 void prom_putchar(char c)
  40 {
  41         O32_STATIC ULONG cnt;
  42         O32_STATIC CHAR it;
  43
  44         it = c;
  45
  46         bc_disable();
  47         ArcWrite(1, &it, 1, &cnt);
  48         bc_enable();
  49 }
  50
  51 char prom_getchar(void)
  52 {
  53         O32_STATIC ULONG cnt;
  54         O32_STATIC CHAR c;
  55
  56         bc_disable();
  57         ArcRead(0, &c, 1, &cnt);
  58         bc_enable();
  59
  60         return c;
  61 }