| blob | fdd4d274c2459dde9afc9824fdc0d9562d3299ab |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Kernel execution entry point code.
4 *
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Rewritten for PReP
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 */
29 #include <linux/init.h>
30 #include <linux/threads.h>
31 #include <linux/pgtable.h>
32 #include <asm/processor.h>
33 #include <asm/page.h>
34 #include <asm/mmu.h>
35 #include <asm/cputable.h>
36 #include <asm/thread_info.h>
37 #include <asm/ppc_asm.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/cache.h>
40 #include <asm/ptrace.h>
41 #include <asm/export.h>
42 #include <asm/feature-fixups.h>
43 #include "head_booke.h"
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 __HEAD
57 _ENTRY(_stext);
58 _ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
65 /* Translate device tree address to physical, save in r30/r31 */
66 bl get_phys_addr
67 mr r30,r3
68 mr r31,r4
70 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */
72 li r23,0 /* phys kernel start (high) */
74 #ifdef CONFIG_RELOCATABLE
75 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
77 /* Translate _stext address to physical, save in r23/r25 */
78 bl get_phys_addr
79 mr r23,r3
80 mr r25,r4
82 bl 0f
83 0: mflr r8
84 addis r3,r8,(is_second_reloc - 0b)@ha
85 lwz r19,(is_second_reloc - 0b)@l(r3)
87 /* Check if this is the second relocation. */
88 cmpwi r19,1
89 bne 1f
91 /*
92 * For the second relocation, we already get the real memstart_addr
93 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94 * then the virtual address of start kernel should be:
95 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
96 * Since the offset between kernstart_addr and memstart_addr should
97 * never be beyond 1G, so we can just use the lower 32bit of them
98 * for the calculation.
99 */
100 lis r3,PAGE_OFFSET@h
102 addis r4,r8,(kernstart_addr - 0b)@ha
103 addi r4,r4,(kernstart_addr - 0b)@l
104 lwz r5,4(r4)
106 addis r6,r8,(memstart_addr - 0b)@ha
107 addi r6,r6,(memstart_addr - 0b)@l
108 lwz r7,4(r6)
110 subf r5,r7,r5
111 add r3,r3,r5
112 b 2f
114 1:
115 /*
116 * We have the runtime (virutal) address of our base.
117 * We calculate our shift of offset from a 64M page.
118 * We could map the 64M page we belong to at PAGE_OFFSET and
119 * get going from there.
120 */
121 lis r4,KERNELBASE@h
122 ori r4,r4,KERNELBASE@l
123 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
124 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
125 subf r3,r5,r6 /* r3 = r6 - r5 */
126 add r3,r4,r3 /* Required Virtual Address */
128 2: bl relocate
130 /*
131 * For the second relocation, we already set the right tlb entries
132 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
133 */
134 cmpwi r19,1
135 beq set_ivor
136 #endif
138 /* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs. We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory. Any boot info passed from the
142 * bootloader needs to live in this first 64M.
143 *
144 * Requirement on bootloader:
145 * - The page we're executing in needs to reside in TLB1 and
146 * have IPROT=1. If not an invalidate broadcast could
147 * evict the entry we're currently executing in.
148 *
149 * r3 = Index of TLB1 were executing in
150 * r4 = Current MSR[IS]
151 * r5 = Index of TLB1 temp mapping
152 *
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
154 * if needed
155 */
157 _ENTRY(__early_start)
158 LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr)
159 lwz r20,0(r20)
161 #define ENTRY_MAPPING_BOOT_SETUP
162 #include "fsl_booke_entry_mapping.S"
163 #undef ENTRY_MAPPING_BOOT_SETUP
165 set_ivor:
166 /* Establish the interrupt vector offsets */
167 SET_IVOR(0, CriticalInput);
168 SET_IVOR(1, MachineCheck);
169 SET_IVOR(2, DataStorage);
170 SET_IVOR(3, InstructionStorage);
171 SET_IVOR(4, ExternalInput);
172 SET_IVOR(5, Alignment);
173 SET_IVOR(6, Program);
174 SET_IVOR(7, FloatingPointUnavailable);
175 SET_IVOR(8, SystemCall);
176 SET_IVOR(9, AuxillaryProcessorUnavailable);
177 SET_IVOR(10, Decrementer);
178 SET_IVOR(11, FixedIntervalTimer);
179 SET_IVOR(12, WatchdogTimer);
180 SET_IVOR(13, DataTLBError);
181 SET_IVOR(14, InstructionTLBError);
182 SET_IVOR(15, DebugCrit);
184 /* Establish the interrupt vector base */
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
188 /* Setup the defaults for TLB entries */
189 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
190 mtspr SPRN_MAS4, r2
192 #if !defined(CONFIG_BDI_SWITCH)
193 /*
194 * The Abatron BDI JTAG debugger does not tolerate others
195 * mucking with the debug registers.
196 */
197 lis r2,DBCR0_IDM@h
198 mtspr SPRN_DBCR0,r2
199 isync
200 /* clear any residual debug events */
201 li r2,-1
202 mtspr SPRN_DBSR,r2
203 #endif
205 #ifdef CONFIG_SMP
206 /* Check to see if we're the second processor, and jump
207 * to the secondary_start code if so
208 */
209 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
210 lwz r24, 0(r24)
211 cmpwi r24, -1
212 mfspr r24,SPRN_PIR
213 bne __secondary_start
214 #endif
216 /*
217 * This is where the main kernel code starts.
218 */
220 /* ptr to current */
221 lis r2,init_task@h
222 ori r2,r2,init_task@l
224 /* ptr to current thread */
225 addi r4,r2,THREAD /* init task's THREAD */
226 mtspr SPRN_SPRG_THREAD,r4
228 /* stack */
229 lis r1,init_thread_union@h
230 ori r1,r1,init_thread_union@l
231 li r0,0
232 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
234 #ifdef CONFIG_SMP
235 stw r24, TASK_CPU(r2)
236 #endif
238 bl early_init
240 #ifdef CONFIG_KASAN
241 bl kasan_early_init
242 #endif
243 #ifdef CONFIG_RELOCATABLE
244 mr r3,r30
245 mr r4,r31
246 #ifdef CONFIG_PHYS_64BIT
247 mr r5,r23
248 mr r6,r25
249 #else
250 mr r5,r25
251 #endif
252 bl relocate_init
253 #endif
255 #ifdef CONFIG_DYNAMIC_MEMSTART
256 lis r3,kernstart_addr@ha
257 la r3,kernstart_addr@l(r3)
258 #ifdef CONFIG_PHYS_64BIT
259 stw r23,0(r3)
260 stw r25,4(r3)
261 #else
262 stw r25,0(r3)
263 #endif
264 #endif
266 /*
267 * Decide what sort of machine this is and initialize the MMU.
268 */
269 mr r3,r30
270 mr r4,r31
271 bl machine_init
272 bl MMU_init
274 /* Setup PTE pointers for the Abatron bdiGDB */
275 lis r6, swapper_pg_dir@h
276 ori r6, r6, swapper_pg_dir@l
277 lis r5, abatron_pteptrs@h
278 ori r5, r5, abatron_pteptrs@l
279 lis r3, kernstart_virt_addr@ha
280 lwz r4, kernstart_virt_addr@l(r3)
281 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
282 stw r6, 0(r5)
284 /* Let's move on */
285 lis r4,start_kernel@h
286 ori r4,r4,start_kernel@l
287 lis r3,MSR_KERNEL@h
288 ori r3,r3,MSR_KERNEL@l
289 mtspr SPRN_SRR0,r4
290 mtspr SPRN_SRR1,r3
291 rfi /* change context and jump to start_kernel */
293 /* Macros to hide the PTE size differences
294 *
295 * FIND_PTE -- walks the page tables given EA & pgdir pointer
296 * r10 -- EA of fault
297 * r11 -- PGDIR pointer
298 * r12 -- free
299 * label 2: is the bailout case
300 *
301 * if we find the pte (fall through):
302 * r11 is low pte word
303 * r12 is pointer to the pte
304 * r10 is the pshift from the PGD, if we're a hugepage
305 */
306 #ifdef CONFIG_PTE_64BIT
307 #ifdef CONFIG_HUGETLB_PAGE
308 #define FIND_PTE \
309 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
310 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
311 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
312 blt 1000f; /* Normal non-huge page */ \
313 beq 2f; /* Bail if no table */ \
314 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
315 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
316 xor r12, r10, r11; /* drop size bits from pointer */ \
317 b 1001f; \
318 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
319 li r10, 0; /* clear r10 */ \
320 1001: lwz r11, 4(r12); /* Get pte entry */
321 #else
322 #define FIND_PTE \
323 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
324 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
325 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
326 beq 2f; /* Bail if no table */ \
327 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
328 lwz r11, 4(r12); /* Get pte entry */
329 #endif /* HUGEPAGE */
330 #else /* !PTE_64BIT */
331 #define FIND_PTE \
332 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
333 lwz r11, 0(r11); /* Get L1 entry */ \
334 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
335 beq 2f; /* Bail if no table */ \
336 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
337 lwz r11, 0(r12); /* Get Linux PTE */
338 #endif
340 /*
341 * Interrupt vector entry code
342 *
343 * The Book E MMUs are always on so we don't need to handle
344 * interrupts in real mode as with previous PPC processors. In
345 * this case we handle interrupts in the kernel virtual address
346 * space.
347 *
348 * Interrupt vectors are dynamically placed relative to the
349 * interrupt prefix as determined by the address of interrupt_base.
350 * The interrupt vectors offsets are programmed using the labels
351 * for each interrupt vector entry.
352 *
353 * Interrupt vectors must be aligned on a 16 byte boundary.
354 * We align on a 32 byte cache line boundary for good measure.
355 */
357 interrupt_base:
358 /* Critical Input Interrupt */
359 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
361 /* Machine Check Interrupt */
362 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
364 /* Data Storage Interrupt */
365 START_EXCEPTION(DataStorage)
366 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
367 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
368 stw r5,_ESR(r11)
369 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
370 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
371 bne 1f
372 stw r4, _DEAR(r11)
373 EXC_XFER_LITE(0x0300, handle_page_fault)
374 1:
375 addi r3,r1,STACK_FRAME_OVERHEAD
376 EXC_XFER_LITE(0x0300, CacheLockingException)
378 /* Instruction Storage Interrupt */
379 INSTRUCTION_STORAGE_EXCEPTION
381 /* External Input Interrupt */
382 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
384 /* Alignment Interrupt */
385 ALIGNMENT_EXCEPTION
387 /* Program Interrupt */
388 PROGRAM_EXCEPTION
390 /* Floating Point Unavailable Interrupt */
391 #ifdef CONFIG_PPC_FPU
392 FP_UNAVAILABLE_EXCEPTION
393 #else
394 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
395 unknown_exception, EXC_XFER_STD)
396 #endif
398 /* System Call Interrupt */
399 START_EXCEPTION(SystemCall)
400 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
402 /* Auxiliary Processor Unavailable Interrupt */
403 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
404 unknown_exception, EXC_XFER_STD)
406 /* Decrementer Interrupt */
407 DECREMENTER_EXCEPTION
409 /* Fixed Internal Timer Interrupt */
410 /* TODO: Add FIT support */
411 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
412 unknown_exception, EXC_XFER_STD)
414 /* Watchdog Timer Interrupt */
415 #ifdef CONFIG_BOOKE_WDT
416 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
417 #else
418 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
419 #endif
421 /* Data TLB Error Interrupt */
422 START_EXCEPTION(DataTLBError)
423 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
424 mfspr r10, SPRN_SPRG_THREAD
425 stw r11, THREAD_NORMSAVE(0)(r10)
426 #ifdef CONFIG_KVM_BOOKE_HV
427 BEGIN_FTR_SECTION
428 mfspr r11, SPRN_SRR1
429 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
430 #endif
431 stw r12, THREAD_NORMSAVE(1)(r10)
432 stw r13, THREAD_NORMSAVE(2)(r10)
433 mfcr r13
434 stw r13, THREAD_NORMSAVE(3)(r10)
435 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
436 START_BTB_FLUSH_SECTION
437 mfspr r11, SPRN_SRR1
438 andi. r10,r11,MSR_PR
439 beq 1f
440 BTB_FLUSH(r10)
441 1:
442 END_BTB_FLUSH_SECTION
443 mfspr r10, SPRN_DEAR /* Get faulting address */
445 /* If we are faulting a kernel address, we have to use the
446 * kernel page tables.
447 */
448 lis r11, PAGE_OFFSET@h
449 cmplw 5, r10, r11
450 blt 5, 3f
451 lis r11, swapper_pg_dir@h
452 ori r11, r11, swapper_pg_dir@l
454 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
455 rlwinm r12,r12,0,16,1
456 mtspr SPRN_MAS1,r12
458 b 4f
460 /* Get the PGD for the current thread */
461 3:
462 mfspr r11,SPRN_SPRG_THREAD
463 lwz r11,PGDIR(r11)
465 4:
466 /* Mask of required permission bits. Note that while we
467 * do copy ESR:ST to _PAGE_RW position as trying to write
468 * to an RO page is pretty common, we don't do it with
469 * _PAGE_DIRTY. We could do it, but it's a fairly rare
470 * event so I'd rather take the overhead when it happens
471 * rather than adding an instruction here. We should measure
472 * whether the whole thing is worth it in the first place
473 * as we could avoid loading SPRN_ESR completely in the first
474 * place...
475 *
476 * TODO: Is it worth doing that mfspr & rlwimi in the first
477 * place or can we save a couple of instructions here ?
478 */
479 mfspr r12,SPRN_ESR
480 #ifdef CONFIG_PTE_64BIT
481 li r13,_PAGE_PRESENT
482 oris r13,r13,_PAGE_ACCESSED@h
483 #else
484 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
485 #endif
486 rlwimi r13,r12,11,29,29
488 FIND_PTE
489 andc. r13,r13,r11 /* Check permission */
491 #ifdef CONFIG_PTE_64BIT
492 #ifdef CONFIG_SMP
493 subf r13,r11,r12 /* create false data dep */
494 lwzx r13,r11,r13 /* Get upper pte bits */
495 #else
496 lwz r13,0(r12) /* Get upper pte bits */
497 #endif
498 #endif
500 bne 2f /* Bail if permission/valid mismach */
502 /* Jump to common tlb load */
503 b finish_tlb_load
504 2:
505 /* The bailout. Restore registers to pre-exception conditions
506 * and call the heavyweights to help us out.
507 */
508 mfspr r10, SPRN_SPRG_THREAD
509 lwz r11, THREAD_NORMSAVE(3)(r10)
510 mtcr r11
511 lwz r13, THREAD_NORMSAVE(2)(r10)
512 lwz r12, THREAD_NORMSAVE(1)(r10)
513 lwz r11, THREAD_NORMSAVE(0)(r10)
514 mfspr r10, SPRN_SPRG_RSCRATCH0
515 b DataStorage
517 /* Instruction TLB Error Interrupt */
518 /*
519 * Nearly the same as above, except we get our
520 * information from different registers and bailout
521 * to a different point.
522 */
523 START_EXCEPTION(InstructionTLBError)
524 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
525 mfspr r10, SPRN_SPRG_THREAD
526 stw r11, THREAD_NORMSAVE(0)(r10)
527 #ifdef CONFIG_KVM_BOOKE_HV
528 BEGIN_FTR_SECTION
529 mfspr r11, SPRN_SRR1
530 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
531 #endif
532 stw r12, THREAD_NORMSAVE(1)(r10)
533 stw r13, THREAD_NORMSAVE(2)(r10)
534 mfcr r13
535 stw r13, THREAD_NORMSAVE(3)(r10)
536 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
537 START_BTB_FLUSH_SECTION
538 mfspr r11, SPRN_SRR1
539 andi. r10,r11,MSR_PR
540 beq 1f
541 BTB_FLUSH(r10)
542 1:
543 END_BTB_FLUSH_SECTION
545 mfspr r10, SPRN_SRR0 /* Get faulting address */
547 /* If we are faulting a kernel address, we have to use the
548 * kernel page tables.
549 */
550 lis r11, PAGE_OFFSET@h
551 cmplw 5, r10, r11
552 blt 5, 3f
553 lis r11, swapper_pg_dir@h
554 ori r11, r11, swapper_pg_dir@l
556 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
557 rlwinm r12,r12,0,16,1
558 mtspr SPRN_MAS1,r12
560 /* Make up the required permissions for kernel code */
561 #ifdef CONFIG_PTE_64BIT
562 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
563 oris r13,r13,_PAGE_ACCESSED@h
564 #else
565 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
566 #endif
567 b 4f
569 /* Get the PGD for the current thread */
570 3:
571 mfspr r11,SPRN_SPRG_THREAD
572 lwz r11,PGDIR(r11)
574 /* Make up the required permissions for user code */
575 #ifdef CONFIG_PTE_64BIT
576 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
577 oris r13,r13,_PAGE_ACCESSED@h
578 #else
579 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
580 #endif
582 4:
583 FIND_PTE
584 andc. r13,r13,r11 /* Check permission */
586 #ifdef CONFIG_PTE_64BIT
587 #ifdef CONFIG_SMP
588 subf r13,r11,r12 /* create false data dep */
589 lwzx r13,r11,r13 /* Get upper pte bits */
590 #else
591 lwz r13,0(r12) /* Get upper pte bits */
592 #endif
593 #endif
595 bne 2f /* Bail if permission mismach */
597 /* Jump to common TLB load point */
598 b finish_tlb_load
600 2:
601 /* The bailout. Restore registers to pre-exception conditions
602 * and call the heavyweights to help us out.
603 */
604 mfspr r10, SPRN_SPRG_THREAD
605 lwz r11, THREAD_NORMSAVE(3)(r10)
606 mtcr r11
607 lwz r13, THREAD_NORMSAVE(2)(r10)
608 lwz r12, THREAD_NORMSAVE(1)(r10)
609 lwz r11, THREAD_NORMSAVE(0)(r10)
610 mfspr r10, SPRN_SPRG_RSCRATCH0
611 b InstructionStorage
613 /* Define SPE handlers for e500v2 */
614 #ifdef CONFIG_SPE
615 /* SPE Unavailable */
616 START_EXCEPTION(SPEUnavailable)
617 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
618 beq 1f
619 bl load_up_spe
620 b fast_exception_return
621 1: addi r3,r1,STACK_FRAME_OVERHEAD
622 EXC_XFER_LITE(0x2010, KernelSPE)
623 #elif defined(CONFIG_SPE_POSSIBLE)
624 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
625 unknown_exception, EXC_XFER_STD)
626 #endif /* CONFIG_SPE_POSSIBLE */
628 /* SPE Floating Point Data */
629 #ifdef CONFIG_SPE
630 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
631 SPEFloatingPointException, EXC_XFER_STD)
633 /* SPE Floating Point Round */
634 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
635 SPEFloatingPointRoundException, EXC_XFER_STD)
636 #elif defined(CONFIG_SPE_POSSIBLE)
637 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
638 unknown_exception, EXC_XFER_STD)
639 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
640 unknown_exception, EXC_XFER_STD)
641 #endif /* CONFIG_SPE_POSSIBLE */
644 /* Performance Monitor */
645 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
646 performance_monitor_exception, EXC_XFER_STD)
648 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
650 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
651 CriticalDoorbell, unknown_exception)
653 /* Debug Interrupt */
654 DEBUG_DEBUG_EXCEPTION
655 DEBUG_CRIT_EXCEPTION
657 GUEST_DOORBELL_EXCEPTION
659 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
660 unknown_exception)
662 /* Hypercall */
663 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
665 /* Embedded Hypervisor Privilege */
666 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
668 interrupt_end:
670 /*
671 * Local functions
672 */
674 /*
675 * Both the instruction and data TLB miss get to this
676 * point to load the TLB.
677 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
678 * r11 - TLB (info from Linux PTE)
679 * r12 - available to use
680 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
681 * CR5 - results of addr >= PAGE_OFFSET
682 * MAS0, MAS1 - loaded with proper value when we get here
683 * MAS2, MAS3 - will need additional info from Linux PTE
684 * Upon exit, we reload everything and RFI.
685 */
686 finish_tlb_load:
687 #ifdef CONFIG_HUGETLB_PAGE
688 cmpwi 6, r10, 0 /* check for huge page */
689 beq 6, finish_tlb_load_cont /* !huge */
691 /* Alas, we need more scratch registers for hugepages */
692 mfspr r12, SPRN_SPRG_THREAD
693 stw r14, THREAD_NORMSAVE(4)(r12)
694 stw r15, THREAD_NORMSAVE(5)(r12)
695 stw r16, THREAD_NORMSAVE(6)(r12)
696 stw r17, THREAD_NORMSAVE(7)(r12)
698 /* Get the next_tlbcam_idx percpu var */
699 #ifdef CONFIG_SMP
700 lwz r15, TASK_CPU-THREAD(r12)
701 lis r14, __per_cpu_offset@h
702 ori r14, r14, __per_cpu_offset@l
703 rlwinm r15, r15, 2, 0, 29
704 lwzx r16, r14, r15
705 #else
706 li r16, 0
707 #endif
708 lis r17, next_tlbcam_idx@h
709 ori r17, r17, next_tlbcam_idx@l
710 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
711 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
713 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
714 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
715 mtspr SPRN_MAS0, r14
717 /* Extract TLB1CFG(NENTRY) */
718 mfspr r16, SPRN_TLB1CFG
719 andi. r16, r16, 0xfff
721 /* Update next_tlbcam_idx, wrapping when necessary */
722 addi r15, r15, 1
723 cmpw r15, r16
724 blt 100f
725 lis r14, tlbcam_index@h
726 ori r14, r14, tlbcam_index@l
727 lwz r15, 0(r14)
728 100: stw r15, 0(r17)
730 /*
731 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
732 * tlb_enc = (pshift - 10).
733 */
734 subi r15, r10, 10
735 mfspr r16, SPRN_MAS1
736 rlwimi r16, r15, 7, 20, 24
737 mtspr SPRN_MAS1, r16
739 /* copy the pshift for use later */
740 mr r14, r10
742 /* fall through */
744 #endif /* CONFIG_HUGETLB_PAGE */
746 /*
747 * We set execute, because we don't have the granularity to
748 * properly set this at the page level (Linux problem).
749 * Many of these bits are software only. Bits we don't set
750 * here we (properly should) assume have the appropriate value.
751 */
752 finish_tlb_load_cont:
753 #ifdef CONFIG_PTE_64BIT
754 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
755 andi. r10, r11, _PAGE_DIRTY
756 bne 1f
757 li r10, MAS3_SW | MAS3_UW
758 andc r12, r12, r10
759 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
760 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
761 2: mtspr SPRN_MAS3, r12
762 BEGIN_MMU_FTR_SECTION
763 srwi r10, r13, 12 /* grab RPN[12:31] */
764 mtspr SPRN_MAS7, r10
765 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
766 #else
767 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
768 mr r13, r11
769 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
770 and r12, r11, r10
771 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
772 slwi r10, r12, 1
773 or r10, r10, r12
774 iseleq r12, r12, r10
775 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
776 mtspr SPRN_MAS3, r13
777 #endif
779 mfspr r12, SPRN_MAS2
780 #ifdef CONFIG_PTE_64BIT
781 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
782 #else
783 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
784 #endif
785 #ifdef CONFIG_HUGETLB_PAGE
786 beq 6, 3f /* don't mask if page isn't huge */
787 li r13, 1
788 slw r13, r13, r14
789 subi r13, r13, 1
790 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
791 andc r12, r12, r13 /* mask off ea bits within the page */
792 #endif
793 3: mtspr SPRN_MAS2, r12
795 tlb_write_entry:
796 tlbwe
798 /* Done...restore registers and get out of here. */
799 mfspr r10, SPRN_SPRG_THREAD
800 #ifdef CONFIG_HUGETLB_PAGE
801 beq 6, 8f /* skip restore for 4k page faults */
802 lwz r14, THREAD_NORMSAVE(4)(r10)
803 lwz r15, THREAD_NORMSAVE(5)(r10)
804 lwz r16, THREAD_NORMSAVE(6)(r10)
805 lwz r17, THREAD_NORMSAVE(7)(r10)
806 #endif
807 8: lwz r11, THREAD_NORMSAVE(3)(r10)
808 mtcr r11
809 lwz r13, THREAD_NORMSAVE(2)(r10)
810 lwz r12, THREAD_NORMSAVE(1)(r10)
811 lwz r11, THREAD_NORMSAVE(0)(r10)
812 mfspr r10, SPRN_SPRG_RSCRATCH0
813 rfi /* Force context change */
815 #ifdef CONFIG_SPE
816 /* Note that the SPE support is closely modeled after the AltiVec
817 * support. Changes to one are likely to be applicable to the
818 * other! */
819 _GLOBAL(load_up_spe)
820 /*
821 * Disable SPE for the task which had SPE previously,
822 * and save its SPE registers in its thread_struct.
823 * Enables SPE for use in the kernel on return.
824 * On SMP we know the SPE units are free, since we give it up every
825 * switch. -- Kumar
826 */
827 mfmsr r5
828 oris r5,r5,MSR_SPE@h
829 mtmsr r5 /* enable use of SPE now */
830 isync
831 /* enable use of SPE after return */
832 oris r9,r9,MSR_SPE@h
833 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
834 li r4,1
835 li r10,THREAD_ACC
836 stw r4,THREAD_USED_SPE(r5)
837 evlddx evr4,r10,r5
838 evmra evr4,evr4
839 REST_32EVRS(0,r10,r5,THREAD_EVR0)
840 blr
842 /*
843 * SPE unavailable trap from kernel - print a message, but let
844 * the task use SPE in the kernel until it returns to user mode.
845 */
846 KernelSPE:
847 lwz r3,_MSR(r1)
848 oris r3,r3,MSR_SPE@h
849 stw r3,_MSR(r1) /* enable use of SPE after return */
850 #ifdef CONFIG_PRINTK
851 lis r3,87f@h
852 ori r3,r3,87f@l
853 mr r4,r2 /* current */
854 lwz r5,_NIP(r1)
855 bl printk
856 #endif
857 b ret_from_except
858 #ifdef CONFIG_PRINTK
859 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
860 #endif
861 .align 4,0
863 #endif /* CONFIG_SPE */
865 /*
866 * Translate the effec addr in r3 to phys addr. The phys addr will be put
867 * into r3(higher 32bit) and r4(lower 32bit)
868 */
869 get_phys_addr:
870 mfmsr r8
871 mfspr r9,SPRN_PID
872 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
873 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
874 mtspr SPRN_MAS6,r9
876 tlbsx 0,r3 /* must succeed */
878 mfspr r8,SPRN_MAS1
879 mfspr r12,SPRN_MAS3
880 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
881 li r10,1024
882 slw r10,r10,r9 /* r10 = page size */
883 addi r10,r10,-1
884 and r11,r3,r10 /* r11 = page offset */
885 andc r4,r12,r10 /* r4 = page base */
886 or r4,r4,r11 /* r4 = devtree phys addr */
887 #ifdef CONFIG_PHYS_64BIT
888 mfspr r3,SPRN_MAS7
889 #endif
890 blr
892 /*
893 * Global functions
894 */
896 #ifdef CONFIG_E500
897 #ifndef CONFIG_PPC_E500MC
898 /* Adjust or setup IVORs for e500v1/v2 */
899 _GLOBAL(__setup_e500_ivors)
900 li r3,DebugCrit@l
901 mtspr SPRN_IVOR15,r3
902 li r3,SPEUnavailable@l
903 mtspr SPRN_IVOR32,r3
904 li r3,SPEFloatingPointData@l
905 mtspr SPRN_IVOR33,r3
906 li r3,SPEFloatingPointRound@l
907 mtspr SPRN_IVOR34,r3
908 li r3,PerformanceMonitor@l
909 mtspr SPRN_IVOR35,r3
910 sync
911 blr
912 #else
913 /* Adjust or setup IVORs for e500mc */
914 _GLOBAL(__setup_e500mc_ivors)
915 li r3,DebugDebug@l
916 mtspr SPRN_IVOR15,r3
917 li r3,PerformanceMonitor@l
918 mtspr SPRN_IVOR35,r3
919 li r3,Doorbell@l
920 mtspr SPRN_IVOR36,r3
921 li r3,CriticalDoorbell@l
922 mtspr SPRN_IVOR37,r3
923 sync
924 blr
926 /* setup ehv ivors for */
927 _GLOBAL(__setup_ehv_ivors)
928 li r3,GuestDoorbell@l
929 mtspr SPRN_IVOR38,r3
930 li r3,CriticalGuestDoorbell@l
931 mtspr SPRN_IVOR39,r3
932 li r3,Hypercall@l
933 mtspr SPRN_IVOR40,r3
934 li r3,Ehvpriv@l
935 mtspr SPRN_IVOR41,r3
936 sync
937 blr
938 #endif /* CONFIG_PPC_E500MC */
939 #endif /* CONFIG_E500 */
941 #ifdef CONFIG_SPE
942 /*
943 * extern void __giveup_spe(struct task_struct *prev)
944 *
945 */
946 _GLOBAL(__giveup_spe)
947 addi r3,r3,THREAD /* want THREAD of task */
948 lwz r5,PT_REGS(r3)
949 cmpi 0,r5,0
950 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
951 evxor evr6, evr6, evr6 /* clear out evr6 */
952 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
953 li r4,THREAD_ACC
954 evstddx evr6, r4, r3 /* save off accumulator */
955 beq 1f
956 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
957 lis r3,MSR_SPE@h
958 andc r4,r4,r3 /* disable SPE for previous task */
959 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
960 1:
961 blr
962 #endif /* CONFIG_SPE */
964 /*
965 * extern void abort(void)
966 *
967 * At present, this routine just applies a system reset.
968 */
969 _GLOBAL(abort)
970 li r13,0
971 mtspr SPRN_DBCR0,r13 /* disable all debug events */
972 isync
973 mfmsr r13
974 ori r13,r13,MSR_DE@l /* Enable Debug Events */
975 mtmsr r13
976 isync
977 mfspr r13,SPRN_DBCR0
978 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
979 mtspr SPRN_DBCR0,r13
980 isync
982 _GLOBAL(set_context)
984 #ifdef CONFIG_BDI_SWITCH
985 /* Context switch the PTE pointer for the Abatron BDI2000.
986 * The PGDIR is the second parameter.
987 */
988 lis r5, abatron_pteptrs@h
989 ori r5, r5, abatron_pteptrs@l
990 stw r4, 0x4(r5)
991 #endif
992 mtspr SPRN_PID,r3
993 isync /* Force context change */
994 blr
996 #ifdef CONFIG_SMP
997 /* When we get here, r24 needs to hold the CPU # */
998 .globl __secondary_start
999 __secondary_start:
1000 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1001 lwz r3,0(r3)
1002 mtctr r3
1003 li r26,0 /* r26 safe? */
1005 bl switch_to_as1
1006 mr r27,r3 /* tlb entry */
1007 /* Load each CAM entry */
1008 1: mr r3,r26
1009 bl loadcam_entry
1010 addi r26,r26,1
1011 bdnz 1b
1012 mr r3,r27 /* tlb entry */
1013 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1014 lwz r4,0(r4)
1015 mr r5,r25 /* phys kernel start */
1016 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1017 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1018 lis r7,KERNELBASE@h
1019 ori r7,r7,KERNELBASE@l
1020 cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */
1021 beq 2f
1022 li r4,0
1023 2: li r5,0 /* no device tree */
1024 li r6,0 /* not boot cpu */
1025 bl restore_to_as0
1028 lis r3,__secondary_hold_acknowledge@h
1029 ori r3,r3,__secondary_hold_acknowledge@l
1030 stw r24,0(r3)
1032 li r3,0
1033 mr r4,r24 /* Why? */
1034 bl call_setup_cpu
1036 /* get current's stack and current */
1037 lis r2,secondary_current@ha
1038 lwz r2,secondary_current@l(r2)
1039 lwz r1,TASK_STACK(r2)
1041 /* stack */
1042 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1043 li r0,0
1044 stw r0,0(r1)
1046 /* ptr to current thread */
1047 addi r4,r2,THREAD /* address of our thread_struct */
1048 mtspr SPRN_SPRG_THREAD,r4
1050 /* Setup the defaults for TLB entries */
1051 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1052 mtspr SPRN_MAS4,r4
1054 /* Jump to start_secondary */
1055 lis r4,MSR_KERNEL@h
1056 ori r4,r4,MSR_KERNEL@l
1057 lis r3,start_secondary@h
1058 ori r3,r3,start_secondary@l
1059 mtspr SPRN_SRR0,r3
1060 mtspr SPRN_SRR1,r4
1061 sync
1062 rfi
1063 sync
1065 .globl __secondary_hold_acknowledge
1066 __secondary_hold_acknowledge:
1067 .long -1
1068 #endif
1070 /*
1071 * Create a 64M tlb by address and entry
1072 * r3 - entry
1073 * r4 - virtual address
1074 * r5/r6 - physical address
1075 */
1076 _GLOBAL(create_kaslr_tlb_entry)
1077 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
1078 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1079 mtspr SPRN_MAS0,r7 /* Write MAS0 */
1081 lis r3,(MAS1_VALID|MAS1_IPROT)@h
1082 ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
1083 mtspr SPRN_MAS1,r3 /* Write MAS1 */
1085 lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
1086 ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
1087 and r3,r3,r4
1088 ori r3,r3,MAS2_M_IF_NEEDED@l
1089 mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */
1091 #ifdef CONFIG_PHYS_64BIT
1092 ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX)
1093 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1094 mtspr SPRN_MAS7,r5
1095 #else
1096 ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX)
1097 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1098 #endif
1100 tlbwe /* Write TLB */
1101 isync
1102 sync
1103 blr
1105 /*
1106 * Return to the start of the relocated kernel and run again
1107 * r3 - virtual address of fdt
1108 * r4 - entry of the kernel
1109 */
1110 _GLOBAL(reloc_kernel_entry)
1111 mfmsr r7
1112 rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS)
1114 mtspr SPRN_SRR0,r4
1115 mtspr SPRN_SRR1,r7
1116 rfi
1118 /*
1119 * Create a tlb entry with the same effective and physical address as
1120 * the tlb entry used by the current running code. But set the TS to 1.
1121 * Then switch to the address space 1. It will return with the r3 set to
1122 * the ESEL of the new created tlb.
1123 */
1124 _GLOBAL(switch_to_as1)
1125 mflr r5
1127 /* Find a entry not used */
1128 mfspr r3,SPRN_TLB1CFG
1129 andi. r3,r3,0xfff
1130 mfspr r4,SPRN_PID
1131 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1132 mtspr SPRN_MAS6,r4
1133 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1134 addi r3,r3,-1
1135 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1136 mtspr SPRN_MAS0,r4
1137 tlbre
1138 mfspr r4,SPRN_MAS1
1139 andis. r4,r4,MAS1_VALID@h
1140 bne 1b
1142 /* Get the tlb entry used by the current running code */
1143 bl 0f
1144 0: mflr r4
1145 tlbsx 0,r4
1147 mfspr r4,SPRN_MAS1
1148 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1149 mtspr SPRN_MAS1,r4
1151 mfspr r4,SPRN_MAS0
1152 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1153 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1154 mtspr SPRN_MAS0,r4
1155 tlbwe
1156 isync
1157 sync
1159 mfmsr r4
1160 ori r4,r4,MSR_IS | MSR_DS
1161 mtspr SPRN_SRR0,r5
1162 mtspr SPRN_SRR1,r4
1163 sync
1164 rfi
1166 /*
1167 * Restore to the address space 0 and also invalidate the tlb entry created
1168 * by switch_to_as1.
1169 * r3 - the tlb entry which should be invalidated
1170 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1171 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1172 * r6 - boot cpu
1173 */
1174 _GLOBAL(restore_to_as0)
1175 mflr r0
1177 bl 0f
1178 0: mflr r9
1179 addi r9,r9,1f - 0b
1181 /*
1182 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1183 * so we need calculate the right jump and device tree address based
1184 * on the offset passed by r4.
1185 */
1186 add r9,r9,r4
1187 add r5,r5,r4
1188 add r0,r0,r4
1190 2: mfmsr r7
1191 li r8,(MSR_IS | MSR_DS)
1192 andc r7,r7,r8
1194 mtspr SPRN_SRR0,r9
1195 mtspr SPRN_SRR1,r7
1196 sync
1197 rfi
1199 /* Invalidate the temporary tlb entry for AS1 */
1200 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1201 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1202 mtspr SPRN_MAS0,r9
1203 tlbre
1204 mfspr r9,SPRN_MAS1
1205 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1206 mtspr SPRN_MAS1,r9
1207 tlbwe
1208 isync
1210 cmpwi r4,0
1211 cmpwi cr1,r6,0
1212 cror eq,4*cr1+eq,eq
1213 bne 3f /* offset != 0 && is_boot_cpu */
1214 mtlr r0
1215 blr
1217 /*
1218 * The PAGE_OFFSET will map to a different physical address,
1219 * jump to _start to do another relocation again.
1220 */
1221 3: mr r3,r5
1222 bl _start
1224 /*
1225 * We put a few things here that have to be page-aligned. This stuff
1226 * goes at the beginning of the data segment, which is page-aligned.
1227 */
1228 .data
1229 .align 12
1230 .globl sdata
1231 sdata:
1232 .globl empty_zero_page
1233 empty_zero_page:
1234 .space 4096
1235 EXPORT_SYMBOL(empty_zero_page)
1236 .globl swapper_pg_dir
1237 swapper_pg_dir:
1238 .space PGD_TABLE_SIZE
1240 /*
1241 * Room for two PTE pointers, usually the kernel and current user pointers
1242 * to their respective root page table.
1243 */
1244 abatron_pteptrs:
1245 .space 8