arch/powerpc/kernel/ptrace/ptrace-adv.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include <linux/regset.h>
   4 #include <linux/hw_breakpoint.h>
   5
   6 #include "ptrace-decl.h"
   7
   8 void user_enable_single_step(struct task_struct *task)
   9 {
  10         struct pt_regs *regs = task->thread.regs;
  11
  12         if (regs != NULL) {
  13                 task->thread.debug.dbcr0 &= ~DBCR0_BT;
  14                 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
  15                 regs->msr |= MSR_DE;
  16         }
  17         set_tsk_thread_flag(task, TIF_SINGLESTEP);
  18 }
  19
  20 void user_enable_block_step(struct task_struct *task)
  21 {
  22         struct pt_regs *regs = task->thread.regs;
  23
  24         if (regs != NULL) {
  25                 task->thread.debug.dbcr0 &= ~DBCR0_IC;
  26                 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
  27                 regs->msr |= MSR_DE;
  28         }
  29         set_tsk_thread_flag(task, TIF_SINGLESTEP);
  30 }
  31
  32 void user_disable_single_step(struct task_struct *task)
  33 {
  34         struct pt_regs *regs = task->thread.regs;
  35
  36         if (regs != NULL) {
  37                 /*
  38                  * The logic to disable single stepping should be as
  39                  * simple as turning off the Instruction Complete flag.
  40                  * And, after doing so, if all debug flags are off, turn
  41                  * off DBCR0(IDM) and MSR(DE) .... Torez
  42                  */
  43                 task->thread.debug.dbcr0 &= ~(DBCR0_IC | DBCR0_BT);
  44                 /*
  45                  * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
  46                  */
  47                 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
  48                                         task->thread.debug.dbcr1)) {
  49                         /*
  50                          * All debug events were off.....
  51                          */
  52                         task->thread.debug.dbcr0 &= ~DBCR0_IDM;
  53                         regs->msr &= ~MSR_DE;
  54                 }
  55         }
  56         clear_tsk_thread_flag(task, TIF_SINGLESTEP);
  57 }
  58
  59 void ppc_gethwdinfo(struct ppc_debug_info *dbginfo)
  60 {
  61         dbginfo->version = 1;
  62         dbginfo->num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
  63         dbginfo->num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
  64         dbginfo->num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
  65         dbginfo->data_bp_alignment = 4;
  66         dbginfo->sizeof_condition = 4;
  67         dbginfo->features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
  68                             PPC_DEBUG_FEATURE_INSN_BP_MASK;
  69         if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_DAC_RANGE))
  70                 dbginfo->features |= PPC_DEBUG_FEATURE_DATA_BP_RANGE |
  71                                      PPC_DEBUG_FEATURE_DATA_BP_MASK;
  72 }
  73
  74 int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
  75                         unsigned long __user *datalp)
  76 {
  77         /* We only support one DABR and no IABRS at the moment */
  78         if (addr > 0)
  79                 return -EINVAL;
  80         return put_user(child->thread.debug.dac1, datalp);
  81 }
  82
  83 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data)
  84 {
  85 #ifdef CONFIG_HAVE_HW_BREAKPOINT
  86         int ret;
  87         struct thread_struct *thread = &task->thread;
  88         struct perf_event *bp;
  89         struct perf_event_attr attr;
  90 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  91
  92         /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
  93          *  For embedded processors we support one DAC and no IAC's at the
  94          *  moment.
  95          */
  96         if (addr > 0)
  97                 return -EINVAL;
  98
  99         /* The bottom 3 bits in dabr are flags */
 100         if ((data & ~0x7UL) >= TASK_SIZE)
 101                 return -EIO;
 102
 103         /* As described above, it was assumed 3 bits were passed with the data
 104          *  address, but we will assume only the mode bits will be passed
 105          *  as to not cause alignment restrictions for DAC-based processors.
 106          */
 107
 108         /* DAC's hold the whole address without any mode flags */
 109         task->thread.debug.dac1 = data & ~0x3UL;
 110
 111         if (task->thread.debug.dac1 == 0) {
 112                 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
 113                 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
 114                                         task->thread.debug.dbcr1)) {
 115                         task->thread.regs->msr &= ~MSR_DE;
 116                         task->thread.debug.dbcr0 &= ~DBCR0_IDM;
 117                 }
 118                 return 0;
 119         }
 120
 121         /* Read or Write bits must be set */
 122
 123         if (!(data & 0x3UL))
 124                 return -EINVAL;
 125
 126         /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 register */
 127         task->thread.debug.dbcr0 |= DBCR0_IDM;
 128
 129         /* Check for write and read flags and set DBCR0 accordingly */
 130         dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
 131         if (data & 0x1UL)
 132                 dbcr_dac(task) |= DBCR_DAC1R;
 133         if (data & 0x2UL)
 134                 dbcr_dac(task) |= DBCR_DAC1W;
 135         task->thread.regs->msr |= MSR_DE;
 136         return 0;
 137 }
 138
 139 static long set_instruction_bp(struct task_struct *child,
 140                                struct ppc_hw_breakpoint *bp_info)
 141 {
 142         int slot;
 143         int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
 144         int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
 145         int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
 146         int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
 147
 148         if (dbcr_iac_range(child) & DBCR_IAC12MODE)
 149                 slot2_in_use = 1;
 150         if (dbcr_iac_range(child) & DBCR_IAC34MODE)
 151                 slot4_in_use = 1;
 152
 153         if (bp_info->addr >= TASK_SIZE)
 154                 return -EIO;
 155
 156         if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
 157                 /* Make sure range is valid. */
 158                 if (bp_info->addr2 >= TASK_SIZE)
 159                         return -EIO;
 160
 161                 /* We need a pair of IAC regsisters */
 162                 if (!slot1_in_use && !slot2_in_use) {
 163                         slot = 1;
 164                         child->thread.debug.iac1 = bp_info->addr;
 165                         child->thread.debug.iac2 = bp_info->addr2;
 166                         child->thread.debug.dbcr0 |= DBCR0_IAC1;
 167                         if (bp_info->addr_mode ==
 168                                         PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
 169                                 dbcr_iac_range(child) |= DBCR_IAC12X;
 170                         else
 171                                 dbcr_iac_range(child) |= DBCR_IAC12I;
 172 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 173                 } else if ((!slot3_in_use) && (!slot4_in_use)) {
 174                         slot = 3;
 175                         child->thread.debug.iac3 = bp_info->addr;
 176                         child->thread.debug.iac4 = bp_info->addr2;
 177                         child->thread.debug.dbcr0 |= DBCR0_IAC3;
 178                         if (bp_info->addr_mode ==
 179                                         PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
 180                                 dbcr_iac_range(child) |= DBCR_IAC34X;
 181                         else
 182                                 dbcr_iac_range(child) |= DBCR_IAC34I;
 183 #endif
 184                 } else {
 185                         return -ENOSPC;
 186                 }
 187         } else {
 188                 /* We only need one.  If possible leave a pair free in
 189                  * case a range is needed later
 190                  */
 191                 if (!slot1_in_use) {
 192                         /*
 193                          * Don't use iac1 if iac1-iac2 are free and either
 194                          * iac3 or iac4 (but not both) are free
 195                          */
 196                         if (slot2_in_use || slot3_in_use == slot4_in_use) {
 197                                 slot = 1;
 198                                 child->thread.debug.iac1 = bp_info->addr;
 199                                 child->thread.debug.dbcr0 |= DBCR0_IAC1;
 200                                 goto out;
 201                         }
 202                 }
 203                 if (!slot2_in_use) {
 204                         slot = 2;
 205                         child->thread.debug.iac2 = bp_info->addr;
 206                         child->thread.debug.dbcr0 |= DBCR0_IAC2;
 207 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 208                 } else if (!slot3_in_use) {
 209                         slot = 3;
 210                         child->thread.debug.iac3 = bp_info->addr;
 211                         child->thread.debug.dbcr0 |= DBCR0_IAC3;
 212                 } else if (!slot4_in_use) {
 213                         slot = 4;
 214                         child->thread.debug.iac4 = bp_info->addr;
 215                         child->thread.debug.dbcr0 |= DBCR0_IAC4;
 216 #endif
 217                 } else {
 218                         return -ENOSPC;
 219                 }
 220         }
 221 out:
 222         child->thread.debug.dbcr0 |= DBCR0_IDM;
 223         child->thread.regs->msr |= MSR_DE;
 224
 225         return slot;
 226 }
 227
 228 static int del_instruction_bp(struct task_struct *child, int slot)
 229 {
 230         switch (slot) {
 231         case 1:
 232                 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
 233                         return -ENOENT;
 234
 235                 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
 236                         /* address range - clear slots 1 & 2 */
 237                         child->thread.debug.iac2 = 0;
 238                         dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
 239                 }
 240                 child->thread.debug.iac1 = 0;
 241                 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
 242                 break;
 243         case 2:
 244                 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
 245                         return -ENOENT;
 246
 247                 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
 248                         /* used in a range */
 249                         return -EINVAL;
 250                 child->thread.debug.iac2 = 0;
 251                 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
 252                 break;
 253 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 254         case 3:
 255                 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
 256                         return -ENOENT;
 257
 258                 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
 259                         /* address range - clear slots 3 & 4 */
 260                         child->thread.debug.iac4 = 0;
 261                         dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
 262                 }
 263                 child->thread.debug.iac3 = 0;
 264                 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
 265                 break;
 266         case 4:
 267                 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
 268                         return -ENOENT;
 269
 270                 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
 271                         /* Used in a range */
 272                         return -EINVAL;
 273                 child->thread.debug.iac4 = 0;
 274                 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
 275                 break;
 276 #endif
 277         default:
 278                 return -EINVAL;
 279         }
 280         return 0;
 281 }
 282
 283 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
 284 {
 285         int byte_enable =
 286                 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
 287                 & 0xf;
 288         int condition_mode =
 289                 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
 290         int slot;
 291
 292         if (byte_enable && condition_mode == 0)
 293                 return -EINVAL;
 294
 295         if (bp_info->addr >= TASK_SIZE)
 296                 return -EIO;
 297
 298         if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
 299                 slot = 1;
 300                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
 301                         dbcr_dac(child) |= DBCR_DAC1R;
 302                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
 303                         dbcr_dac(child) |= DBCR_DAC1W;
 304                 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
 305 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 306                 if (byte_enable) {
 307                         child->thread.debug.dvc1 =
 308                                 (unsigned long)bp_info->condition_value;
 309                         child->thread.debug.dbcr2 |=
 310                                 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
 311                                  (condition_mode << DBCR2_DVC1M_SHIFT));
 312                 }
 313 #endif
 314 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
 315         } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
 316                 /* Both dac1 and dac2 are part of a range */
 317                 return -ENOSPC;
 318 #endif
 319         } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
 320                 slot = 2;
 321                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
 322                         dbcr_dac(child) |= DBCR_DAC2R;
 323                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
 324                         dbcr_dac(child) |= DBCR_DAC2W;
 325                 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
 326 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 327                 if (byte_enable) {
 328                         child->thread.debug.dvc2 =
 329                                 (unsigned long)bp_info->condition_value;
 330                         child->thread.debug.dbcr2 |=
 331                                 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
 332                                  (condition_mode << DBCR2_DVC2M_SHIFT));
 333                 }
 334 #endif
 335         } else {
 336                 return -ENOSPC;
 337         }
 338         child->thread.debug.dbcr0 |= DBCR0_IDM;
 339         child->thread.regs->msr |= MSR_DE;
 340
 341         return slot + 4;
 342 }
 343
 344 static int del_dac(struct task_struct *child, int slot)
 345 {
 346         if (slot == 1) {
 347                 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
 348                         return -ENOENT;
 349
 350                 child->thread.debug.dac1 = 0;
 351                 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
 352 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
 353                 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
 354                         child->thread.debug.dac2 = 0;
 355                         child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
 356                 }
 357                 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
 358 #endif
 359 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 360                 child->thread.debug.dvc1 = 0;
 361 #endif
 362         } else if (slot == 2) {
 363                 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
 364                         return -ENOENT;
 365
 366 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
 367                 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
 368                         /* Part of a range */
 369                         return -EINVAL;
 370                 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
 371 #endif
 372 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 373                 child->thread.debug.dvc2 = 0;
 374 #endif
 375                 child->thread.debug.dac2 = 0;
 376                 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
 377         } else {
 378                 return -EINVAL;
 379         }
 380
 381         return 0;
 382 }
 383
 384 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
 385 static int set_dac_range(struct task_struct *child,
 386                          struct ppc_hw_breakpoint *bp_info)
 387 {
 388         int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
 389
 390         /* We don't allow range watchpoints to be used with DVC */
 391         if (bp_info->condition_mode)
 392                 return -EINVAL;
 393
 394         /*
 395          * Best effort to verify the address range.  The user/supervisor bits
 396          * prevent trapping in kernel space, but let's fail on an obvious bad
 397          * range.  The simple test on the mask is not fool-proof, and any
 398          * exclusive range will spill over into kernel space.
 399          */
 400         if (bp_info->addr >= TASK_SIZE)
 401                 return -EIO;
 402         if (mode == PPC_BREAKPOINT_MODE_MASK) {
 403                 /*
 404                  * dac2 is a bitmask.  Don't allow a mask that makes a
 405                  * kernel space address from a valid dac1 value
 406                  */
 407                 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
 408                         return -EIO;
 409         } else {
 410                 /*
 411                  * For range breakpoints, addr2 must also be a valid address
 412                  */
 413                 if (bp_info->addr2 >= TASK_SIZE)
 414                         return -EIO;
 415         }
 416
 417         if (child->thread.debug.dbcr0 &
 418             (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
 419                 return -ENOSPC;
 420
 421         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
 422                 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
 423         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
 424                 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
 425         child->thread.debug.dac1 = bp_info->addr;
 426         child->thread.debug.dac2 = bp_info->addr2;
 427         if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
 428                 child->thread.debug.dbcr2  |= DBCR2_DAC12M;
 429         else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
 430                 child->thread.debug.dbcr2  |= DBCR2_DAC12MX;
 431         else    /* PPC_BREAKPOINT_MODE_MASK */
 432                 child->thread.debug.dbcr2  |= DBCR2_DAC12MM;
 433         child->thread.regs->msr |= MSR_DE;
 434
 435         return 5;
 436 }
 437 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
 438
 439 long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
 440 {
 441         if (bp_info->version != 1)
 442                 return -ENOTSUPP;
 443         /*
 444          * Check for invalid flags and combinations
 445          */
 446         if (bp_info->trigger_type == 0 ||
 447             (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
 448                                        PPC_BREAKPOINT_TRIGGER_RW)) ||
 449             (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
 450             (bp_info->condition_mode &
 451              ~(PPC_BREAKPOINT_CONDITION_MODE |
 452                PPC_BREAKPOINT_CONDITION_BE_ALL)))
 453                 return -EINVAL;
 454 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
 455         if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
 456                 return -EINVAL;
 457 #endif
 458
 459         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
 460                 if (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE ||
 461                     bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
 462                         return -EINVAL;
 463                 return set_instruction_bp(child, bp_info);
 464         }
 465         if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
 466                 return set_dac(child, bp_info);
 467
 468 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
 469         return set_dac_range(child, bp_info);
 470 #else
 471         return -EINVAL;
 472 #endif
 473 }
 474
 475 long ppc_del_hwdebug(struct task_struct *child, long data)
 476 {
 477         int rc;
 478
 479         if (data <= 4)
 480                 rc = del_instruction_bp(child, (int)data);
 481         else
 482                 rc = del_dac(child, (int)data - 4);
 483
 484         if (!rc) {
 485                 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
 486                                         child->thread.debug.dbcr1)) {
 487                         child->thread.debug.dbcr0 &= ~DBCR0_IDM;
 488                         child->thread.regs->msr &= ~MSR_DE;
 489                 }
 490         }
 491         return rc;
 492 }