Merge tag 'sched-urgent-2020-12-27' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / arch / powerpc / kernel / vdso32 / sigtramp.S
blob0bcc5e5fe7893a1f1a5988f92f10c00b25951405
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Signal trampolines for 32 bits processes in a ppc64 kernel for
4  * use in the vDSO
5  *
6  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
7  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
8  */
9 #include <asm/processor.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/unistd.h>
12 #include <asm/vdso.h>
14         .text
16 /* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
17    the return address to get an address in the middle of the presumed
18    call instruction.  Since we don't have a call here, we artificially
19    extend the range covered by the unwind info by adding a nop before
20    the real start.  */
21         nop
22 V_FUNCTION_BEGIN(__kernel_sigtramp32)
23 .Lsig_start = . - 4
24         li      r0,__NR_sigreturn
25         sc
26 .Lsig_end:
27 V_FUNCTION_END(__kernel_sigtramp32)
29 .Lsigrt_start:
30         nop
31 V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
32         li      r0,__NR_rt_sigreturn
33         sc
34 .Lsigrt_end:
35 V_FUNCTION_END(__kernel_sigtramp_rt32)
37         .section .eh_frame,"a",@progbits
39 /* Register r1 can be found at offset 4 of a pt_regs structure.
40    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
41 #define cfa_save \
42   .byte 0x0f;                   /* DW_CFA_def_cfa_expression */         \
43   .uleb128 9f - 1f;             /*   length */                          \
44 1:                                                                      \
45   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
46   .byte 0x06;                   /*     DW_OP_deref */                   \
47   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */             \
48   .byte 0x06;                   /*     DW_OP_deref */                   \
51 /* Register REGNO can be found at offset OFS of a pt_regs structure.
52    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
53 #define rsave(regno, ofs) \
54   .byte 0x10;                   /* DW_CFA_expression */                 \
55   .uleb128 regno;               /*   regno */                           \
56   .uleb128 9f - 1f;             /*   length */                          \
57 1:                                                                      \
58   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
59   .byte 0x06;                   /*     DW_OP_deref */                   \
60   .ifne ofs;                                                            \
61     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */             \
62   .endif;                                                               \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
66    of the VMX reg struct.  The VMX reg struct is at offset VREGS of
67    the pt_regs struct.  This macro is for REGNO == 0, and contains
68    'subroutines' that the other macros jump to.  */
69 #define vsave_msr0(regno) \
70   .byte 0x10;                   /* DW_CFA_expression */                 \
71   .uleb128 regno + 77;          /*   regno */                           \
72   .uleb128 9f - 1f;             /*   length */                          \
73 1:                                                                      \
74   .byte 0x30 + regno;           /*     DW_OP_lit0 */                    \
75 2:                                                                      \
76   .byte 0x40;                   /*     DW_OP_lit16 */                   \
77   .byte 0x1e;                   /*     DW_OP_mul */                     \
78 3:                                                                      \
79   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
80   .byte 0x06;                   /*     DW_OP_deref */                   \
81   .byte 0x12;                   /*     DW_OP_dup */                     \
82   .byte 0x23;                   /*     DW_OP_plus_uconst */             \
83     .uleb128 33*RSIZE;          /*       msr offset */                  \
84   .byte 0x06;                   /*     DW_OP_deref */                   \
85   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */                 \
86   .byte 0x1a;                   /*     DW_OP_and */                     \
87   .byte 0x12;                   /*     DW_OP_dup, ret 0 if bra taken */ \
88   .byte 0x30;                   /*     DW_OP_lit0 */                    \
89   .byte 0x29;                   /*     DW_OP_eq */                      \
90   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */              \
91   .byte 0x13;                   /*     DW_OP_drop, pop the 0 */         \
92   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
93   .byte 0x22;                   /*     DW_OP_plus */                    \
94   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */             \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
98    of the VMX reg struct.  REGNO is 1 thru 31.  */
99 #define vsave_msr1(regno) \
100   .byte 0x10;                   /* DW_CFA_expression */                 \
101   .uleb128 regno + 77;          /*   regno */                           \
102   .uleb128 9f - 1f;             /*   length */                          \
103 1:                                                                      \
104   .byte 0x30 + regno;           /*     DW_OP_lit n */                   \
105   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */                    \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
109    the VMX save block.  */
110 #define vsave_msr2(regno, ofs) \
111   .byte 0x10;                   /* DW_CFA_expression */                 \
112   .uleb128 regno + 77;          /*   regno */                           \
113   .uleb128 9f - 1f;             /*   length */                          \
114 1:                                                                      \
115   .byte 0x0a; .short ofs;       /*     DW_OP_const2u */                 \
116   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */                    \
119 /* VMX register REGNO is at offset OFS of the VMX save area.  */
120 #define vsave(regno, ofs) \
121   .byte 0x10;                   /* DW_CFA_expression */                 \
122   .uleb128 regno + 77;          /*   regno */                           \
123   .uleb128 9f - 1f;             /*   length */                          \
124 1:                                                                      \
125   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
126   .byte 0x06;                   /*     DW_OP_deref */                   \
127   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
128   .byte 0x23; .uleb128 ofs;     /*     DW_OP_plus_uconst */             \
131 /* This is where the pt_regs pointer can be found on the stack.  */
132 #define PTREGS 64+28
134 /* Size of regs.  */
135 #define RSIZE 4
137 /* This is the offset of the VMX regs.  */
138 #define VREGS 48*RSIZE+34*8
140 /* Describe where general purpose regs are saved.  */
141 #define EH_FRAME_GEN \
142   cfa_save;                                                             \
143   rsave ( 0,  0*RSIZE);                                                 \
144   rsave ( 2,  2*RSIZE);                                                 \
145   rsave ( 3,  3*RSIZE);                                                 \
146   rsave ( 4,  4*RSIZE);                                                 \
147   rsave ( 5,  5*RSIZE);                                                 \
148   rsave ( 6,  6*RSIZE);                                                 \
149   rsave ( 7,  7*RSIZE);                                                 \
150   rsave ( 8,  8*RSIZE);                                                 \
151   rsave ( 9,  9*RSIZE);                                                 \
152   rsave (10, 10*RSIZE);                                                 \
153   rsave (11, 11*RSIZE);                                                 \
154   rsave (12, 12*RSIZE);                                                 \
155   rsave (13, 13*RSIZE);                                                 \
156   rsave (14, 14*RSIZE);                                                 \
157   rsave (15, 15*RSIZE);                                                 \
158   rsave (16, 16*RSIZE);                                                 \
159   rsave (17, 17*RSIZE);                                                 \
160   rsave (18, 18*RSIZE);                                                 \
161   rsave (19, 19*RSIZE);                                                 \
162   rsave (20, 20*RSIZE);                                                 \
163   rsave (21, 21*RSIZE);                                                 \
164   rsave (22, 22*RSIZE);                                                 \
165   rsave (23, 23*RSIZE);                                                 \
166   rsave (24, 24*RSIZE);                                                 \
167   rsave (25, 25*RSIZE);                                                 \
168   rsave (26, 26*RSIZE);                                                 \
169   rsave (27, 27*RSIZE);                                                 \
170   rsave (28, 28*RSIZE);                                                 \
171   rsave (29, 29*RSIZE);                                                 \
172   rsave (30, 30*RSIZE);                                                 \
173   rsave (31, 31*RSIZE);                                                 \
174   rsave (67, 32*RSIZE);         /* ap, used as temp for nip */          \
175   rsave (65, 36*RSIZE);         /* lr */                                \
176   rsave (70, 38*RSIZE)          /* cr */
178 /* Describe where the FP regs are saved.  */
179 #define EH_FRAME_FP \
180   rsave (32, 48*RSIZE +  0*8);                                          \
181   rsave (33, 48*RSIZE +  1*8);                                          \
182   rsave (34, 48*RSIZE +  2*8);                                          \
183   rsave (35, 48*RSIZE +  3*8);                                          \
184   rsave (36, 48*RSIZE +  4*8);                                          \
185   rsave (37, 48*RSIZE +  5*8);                                          \
186   rsave (38, 48*RSIZE +  6*8);                                          \
187   rsave (39, 48*RSIZE +  7*8);                                          \
188   rsave (40, 48*RSIZE +  8*8);                                          \
189   rsave (41, 48*RSIZE +  9*8);                                          \
190   rsave (42, 48*RSIZE + 10*8);                                          \
191   rsave (43, 48*RSIZE + 11*8);                                          \
192   rsave (44, 48*RSIZE + 12*8);                                          \
193   rsave (45, 48*RSIZE + 13*8);                                          \
194   rsave (46, 48*RSIZE + 14*8);                                          \
195   rsave (47, 48*RSIZE + 15*8);                                          \
196   rsave (48, 48*RSIZE + 16*8);                                          \
197   rsave (49, 48*RSIZE + 17*8);                                          \
198   rsave (50, 48*RSIZE + 18*8);                                          \
199   rsave (51, 48*RSIZE + 19*8);                                          \
200   rsave (52, 48*RSIZE + 20*8);                                          \
201   rsave (53, 48*RSIZE + 21*8);                                          \
202   rsave (54, 48*RSIZE + 22*8);                                          \
203   rsave (55, 48*RSIZE + 23*8);                                          \
204   rsave (56, 48*RSIZE + 24*8);                                          \
205   rsave (57, 48*RSIZE + 25*8);                                          \
206   rsave (58, 48*RSIZE + 26*8);                                          \
207   rsave (59, 48*RSIZE + 27*8);                                          \
208   rsave (60, 48*RSIZE + 28*8);                                          \
209   rsave (61, 48*RSIZE + 29*8);                                          \
210   rsave (62, 48*RSIZE + 30*8);                                          \
211   rsave (63, 48*RSIZE + 31*8)
213 /* Describe where the VMX regs are saved.  */
214 #ifdef CONFIG_ALTIVEC
215 #define EH_FRAME_VMX \
216   vsave_msr0 ( 0);                                                      \
217   vsave_msr1 ( 1);                                                      \
218   vsave_msr1 ( 2);                                                      \
219   vsave_msr1 ( 3);                                                      \
220   vsave_msr1 ( 4);                                                      \
221   vsave_msr1 ( 5);                                                      \
222   vsave_msr1 ( 6);                                                      \
223   vsave_msr1 ( 7);                                                      \
224   vsave_msr1 ( 8);                                                      \
225   vsave_msr1 ( 9);                                                      \
226   vsave_msr1 (10);                                                      \
227   vsave_msr1 (11);                                                      \
228   vsave_msr1 (12);                                                      \
229   vsave_msr1 (13);                                                      \
230   vsave_msr1 (14);                                                      \
231   vsave_msr1 (15);                                                      \
232   vsave_msr1 (16);                                                      \
233   vsave_msr1 (17);                                                      \
234   vsave_msr1 (18);                                                      \
235   vsave_msr1 (19);                                                      \
236   vsave_msr1 (20);                                                      \
237   vsave_msr1 (21);                                                      \
238   vsave_msr1 (22);                                                      \
239   vsave_msr1 (23);                                                      \
240   vsave_msr1 (24);                                                      \
241   vsave_msr1 (25);                                                      \
242   vsave_msr1 (26);                                                      \
243   vsave_msr1 (27);                                                      \
244   vsave_msr1 (28);                                                      \
245   vsave_msr1 (29);                                                      \
246   vsave_msr1 (30);                                                      \
247   vsave_msr1 (31);                                                      \
248   vsave_msr2 (33, 32*16+12);                                            \
249   vsave      (32, 32*16)
250 #else
251 #define EH_FRAME_VMX
252 #endif
254 .Lcie:
255         .long .Lcie_end - .Lcie_start
256 .Lcie_start:
257         .long 0                 /* CIE ID */
258         .byte 1                 /* Version number */
259         .string "zRS"           /* NUL-terminated augmentation string */
260         .uleb128 4              /* Code alignment factor */
261         .sleb128 -4             /* Data alignment factor */
262         .byte 67                /* Return address register column, ap */
263         .uleb128 1              /* Augmentation value length */
264         .byte 0x1b              /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
265         .byte 0x0c,1,0          /* DW_CFA_def_cfa: r1 ofs 0 */
266         .balign 4
267 .Lcie_end:
269         .long .Lfde0_end - .Lfde0_start
270 .Lfde0_start:
271         .long .Lfde0_start - .Lcie      /* CIE pointer. */
272         .long .Lsig_start - .           /* PC start, length */
273         .long .Lsig_end - .Lsig_start
274         .uleb128 0                      /* Augmentation */
275         EH_FRAME_GEN
276         EH_FRAME_FP
277         EH_FRAME_VMX
278         .balign 4
279 .Lfde0_end:
281 /* We have a different stack layout for rt_sigreturn.  */
282 #undef PTREGS
283 #define PTREGS 64+16+128+20+28
285         .long .Lfde1_end - .Lfde1_start
286 .Lfde1_start:
287         .long .Lfde1_start - .Lcie      /* CIE pointer. */
288         .long .Lsigrt_start - .         /* PC start, length */
289         .long .Lsigrt_end - .Lsigrt_start
290         .uleb128 0                      /* Augmentation */
291         EH_FRAME_GEN
292         EH_FRAME_FP
293         EH_FRAME_VMX
294         .balign 4
295 .Lfde1_end: