1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains assembly-language implementations
4 * of IP-style 1's complement checksum routines.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au).
11 #include <linux/sys.h>
12 #include <asm/processor.h>
13 #include <asm/errno.h>
14 #include <asm/ppc_asm.h>
15 #include <asm/export.h>
18 * Computes the checksum of a memory block at buff, length len,
19 * and adds in "sum" (32-bit).
21 * __csum_partial(r3=buff, r4=len, r5=sum)
23 _GLOBAL(__csum_partial)
24 addic r0,r5,0 /* clear carry */
26 srdi. r6,r4,3 /* less than 8 bytes? */
30 * If only halfword aligned, align to a double word. Since odd
31 * aligned addresses should be rare and they would require more
32 * work to calculate the correct checksum, we ignore that case
33 * and take the potential slowdown of unaligned loads.
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
43 lhz r6,0(r3) /* align to doubleword */
51 * We unroll the loop such that each iteration is 64 bytes with an
52 * entry and exit limb of 64 bytes, meaning a minimum size of
56 beq .Lcsum_tail_doublewords /* len < 128 */
62 stdu r1,-STACKFRAMESIZE(r1)
63 std r14,STK_REG(R14)(r1)
64 std r15,STK_REG(R15)(r1)
65 std r16,STK_REG(R16)(r1)
74 * On POWER6 and POWER7 back to back adde instructions take 2 cycles
75 * because of the XER dependency. This means the fastest this loop can
76 * go is 16 cycles per iteration. The scheduling of the loop below has
77 * been shown to hit this on both POWER6 and POWER7.
124 ld r14,STK_REG(R14)(r1)
125 ld r15,STK_REG(R15)(r1)
126 ld r16,STK_REG(R16)(r1)
127 addi r1,r1,STACKFRAMESIZE
131 .Lcsum_tail_doublewords: /* Up to 127 bytes to go */
144 .Lcsum_tail_word: /* Up to 7 bytes to go */
146 beq .Lcsum_tail_halfword
153 .Lcsum_tail_halfword: /* Up to 3 bytes to go */
162 .Lcsum_tail_byte: /* Up to 1 byte to go */
167 #ifdef __BIG_ENDIAN__
168 sldi r9,r6,8 /* Pad the byte out to 16 bits */
175 addze r0,r0 /* add in final carry */
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
180 EXPORT_SYMBOL(__csum_partial)
185 EX_TABLE(100b,.Lerror_nr)
190 EX_TABLE(150b,.Lerror)
195 EX_TABLE(200b,.Lerror_nr)
200 EX_TABLE(250b,.Lerror)
204 * Computes the checksum of a memory block at src, length len,
205 * and adds in 0xffffffff (32-bit), while copying the block to dst.
206 * If an access exception occurs, it returns 0.
208 * csum_partial_copy_generic(r3=src, r4=dst, r5=len)
210 _GLOBAL(csum_partial_copy_generic)
212 addic r0,r6,0 /* clear carry */
214 srdi. r6,r5,3 /* less than 8 bytes? */
218 * If only halfword aligned, align to a double word. Since odd
219 * aligned addresses should be rare and they would require more
220 * work to calculate the correct checksum, we ignore that case
221 * and take the potential slowdown of unaligned loads.
223 * If the source and destination are relatively unaligned we only
224 * align the source. This keeps things simple.
226 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
234 srcnr; lhz r6,0(r3) /* align to doubleword */
244 * We unroll the loop such that each iteration is 64 bytes with an
245 * entry and exit limb of 64 bytes, meaning a minimum size of
249 beq .Lcopy_tail_doublewords /* len < 128 */
255 stdu r1,-STACKFRAMESIZE(r1)
256 std r14,STK_REG(R14)(r1)
257 std r15,STK_REG(R15)(r1)
258 std r16,STK_REG(R16)(r1)
263 source; ld r10,16(r3)
264 source; ld r11,24(r3)
267 * On POWER6 and POWER7 back to back adde instructions take 2 cycles
268 * because of the XER dependency. This means the fastest this loop can
269 * go is 16 cycles per iteration. The scheduling of the loop below has
270 * been shown to hit this on both POWER6 and POWER7.
275 source; ld r12,32(r3)
276 source; ld r14,40(r3)
279 source; ld r15,48(r3)
280 source; ld r16,56(r3)
305 source; ld r10,16(r3)
306 source; ld r11,24(r3)
311 source; ld r12,32(r3)
312 source; ld r14,40(r3)
315 source; ld r15,48(r3)
316 source; ld r16,56(r3)
339 ld r14,STK_REG(R14)(r1)
340 ld r15,STK_REG(R15)(r1)
341 ld r16,STK_REG(R16)(r1)
342 addi r1,r1,STACKFRAMESIZE
346 .Lcopy_tail_doublewords: /* Up to 127 bytes to go */
361 .Lcopy_tail_word: /* Up to 7 bytes to go */
363 beq .Lcopy_tail_halfword
372 .Lcopy_tail_halfword: /* Up to 3 bytes to go */
383 .Lcopy_tail_byte: /* Up to 1 byte to go */
388 #ifdef __BIG_ENDIAN__
389 sldi r9,r6,8 /* Pad the byte out to 16 bits */
397 addze r0,r0 /* add in final carry */
398 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
404 ld r14,STK_REG(R14)(r1)
405 ld r15,STK_REG(R15)(r1)
406 ld r16,STK_REG(R16)(r1)
407 addi r1,r1,STACKFRAMESIZE
412 EXPORT_SYMBOL(csum_partial_copy_generic)
415 * __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
416 * const struct in6_addr *daddr,
417 * __u32 len, __u8 proto, __wsum sum)
420 _GLOBAL(csum_ipv6_magic)
427 #ifdef CONFIG_CPU_LITTLE_ENDIAN
435 rotldi r3, r0, 32 /* fold two 32 bit halves together */
438 rotlwi r3, r0, 16 /* fold two 16 bit halves together */
441 rlwinm r3, r3, 16, 16, 31
443 EXPORT_SYMBOL(csum_ipv6_magic)