arch/powerpc/perf/power6-pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Performance counter support for POWER6 processors.
   4  *
   5  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/perf_event.h>
   9 #include <linux/string.h>
  10 #include <asm/reg.h>
  11 #include <asm/cputable.h>
  12
  13 #include "internal.h"
  14
  15 /*
  16  * Bits in event code for POWER6
  17  */
  18 #define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
  19 #define PM_PMC_MSK      0x7
  20 #define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
  21 #define PM_UNIT_SH      16      /* Unit event comes (TTMxSEL encoding) */
  22 #define PM_UNIT_MSK     0xf
  23 #define PM_UNIT_MSKS    (PM_UNIT_MSK << PM_UNIT_SH)
  24 #define PM_LLAV         0x8000  /* Load lookahead match value */
  25 #define PM_LLA          0x4000  /* Load lookahead match enable */
  26 #define PM_BYTE_SH      12      /* Byte of event bus to use */
  27 #define PM_BYTE_MSK     3
  28 #define PM_SUBUNIT_SH   8       /* Subunit event comes from (NEST_SEL enc.) */
  29 #define PM_SUBUNIT_MSK  7
  30 #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
  31 #define PM_PMCSEL_MSK   0xff    /* PMCxSEL value */
  32 #define PM_BUSEVENT_MSK 0xf3700
  33
  34 /*
  35  * Bits in MMCR1 for POWER6
  36  */
  37 #define MMCR1_TTM0SEL_SH        60
  38 #define MMCR1_TTMSEL_SH(n)      (MMCR1_TTM0SEL_SH - (n) * 4)
  39 #define MMCR1_TTMSEL_MSK        0xf
  40 #define MMCR1_TTMSEL(m, n)      (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
  41 #define MMCR1_NESTSEL_SH        45
  42 #define MMCR1_NESTSEL_MSK       0x7
  43 #define MMCR1_NESTSEL(m)        (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
  44 #define MMCR1_PMC1_LLA          (1ul << 44)
  45 #define MMCR1_PMC1_LLA_VALUE    (1ul << 39)
  46 #define MMCR1_PMC1_ADDR_SEL     (1ul << 35)
  47 #define MMCR1_PMC1SEL_SH        24
  48 #define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
  49 #define MMCR1_PMCSEL_MSK        0xff
  50
  51 /*
  52  * Map of which direct events on which PMCs are marked instruction events.
  53  * Indexed by PMCSEL value >> 1.
  54  * Bottom 4 bits are a map of which PMCs are interesting,
  55  * top 4 bits say what sort of event:
  56  *   0 = direct marked event,
  57  *   1 = byte decode event,
  58  *   4 = add/and event (PMC1 -> bits 0 & 4),
  59  *   5 = add/and event (PMC1 -> bits 1 & 5),
  60  *   6 = add/and event (PMC1 -> bits 2 & 6),
  61  *   7 = add/and event (PMC1 -> bits 3 & 7).
  62  */
  63 static unsigned char direct_event_is_marked[0x60 >> 1] = {
  64         0,      /* 00 */
  65         0,      /* 02 */
  66         0,      /* 04 */
  67         0x07,   /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
  68         0x04,   /* 08 PM_MRK_DFU_FIN */
  69         0x06,   /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
  70         0,      /* 0c */
  71         0,      /* 0e */
  72         0x02,   /* 10 PM_MRK_INST_DISP */
  73         0x08,   /* 12 PM_MRK_LSU_DERAT_MISS */
  74         0,      /* 14 */
  75         0,      /* 16 */
  76         0x0c,   /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
  77         0x0f,   /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
  78         0x01,   /* 1c PM_MRK_INST_ISSUED */
  79         0,      /* 1e */
  80         0,      /* 20 */
  81         0,      /* 22 */
  82         0,      /* 24 */
  83         0,      /* 26 */
  84         0x15,   /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
  85         0,      /* 2a */
  86         0,      /* 2c */
  87         0,      /* 2e */
  88         0x4f,   /* 30 */
  89         0x7f,   /* 32 */
  90         0x4f,   /* 34 */
  91         0x5f,   /* 36 */
  92         0x6f,   /* 38 */
  93         0x4f,   /* 3a */
  94         0,      /* 3c */
  95         0x08,   /* 3e PM_MRK_INST_TIMEO */
  96         0x1f,   /* 40 */
  97         0x1f,   /* 42 */
  98         0x1f,   /* 44 */
  99         0x1f,   /* 46 */
 100         0x1f,   /* 48 */
 101         0x1f,   /* 4a */
 102         0x1f,   /* 4c */
 103         0x1f,   /* 4e */
 104         0,      /* 50 */
 105         0x05,   /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
 106         0x1c,   /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
 107         0x02,   /* 56 PM_MRK_LD_MISS_L1 */
 108         0,      /* 58 */
 109         0,      /* 5a */
 110         0,      /* 5c */
 111         0,      /* 5e */
 112 };
 113
 114 /*
 115  * Masks showing for each unit which bits are marked events.
 116  * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
 117  */
 118 static u32 marked_bus_events[16] = {
 119         0x01000000,     /* direct events set 1: byte 3 bit 0 */
 120         0x00010000,     /* direct events set 2: byte 2 bit 0 */
 121         0, 0, 0, 0,     /* IDU, IFU, nest: nothing */
 122         0x00000088,     /* VMX set 1: byte 0 bits 3, 7 */
 123         0x000000c0,     /* VMX set 2: byte 0 bits 4-7 */
 124         0x04010000,     /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
 125         0xff010000u,    /* LSU set 2: byte 2 bit 0, all of byte 3 */
 126         0,              /* LSU set 3 */
 127         0x00000010,     /* VMX set 3: byte 0 bit 4 */
 128         0,              /* BFP set 1 */
 129         0x00000022,     /* BFP set 2: byte 0 bits 1, 5 */
 130         0, 0
 131 };
 132
 133 /*
 134  * Returns 1 if event counts things relating to marked instructions
 135  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 136  */
 137 static int power6_marked_instr_event(u64 event)
 138 {
 139         int pmc, psel, ptype;
 140         int bit, byte, unit;
 141         u32 mask;
 142
 143         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 144         psel = (event & PM_PMCSEL_MSK) >> 1;    /* drop edge/level bit */
 145         if (pmc >= 5)
 146                 return 0;
 147
 148         bit = -1;
 149         if (psel < sizeof(direct_event_is_marked)) {
 150                 ptype = direct_event_is_marked[psel];
 151                 if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
 152                         return 0;
 153                 ptype >>= 4;
 154                 if (ptype == 0)
 155                         return 1;
 156                 if (ptype == 1)
 157                         bit = 0;
 158                 else
 159                         bit = ptype ^ (pmc - 1);
 160         } else if ((psel & 0x48) == 0x40)
 161                 bit = psel & 7;
 162
 163         if (!(event & PM_BUSEVENT_MSK) || bit == -1)
 164                 return 0;
 165
 166         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 167         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 168         mask = marked_bus_events[unit];
 169         return (mask >> (byte * 8 + bit)) & 1;
 170 }
 171
 172 /*
 173  * Assign PMC numbers and compute MMCR1 value for a set of events
 174  */
 175 static int p6_compute_mmcr(u64 event[], int n_ev,
 176                            unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[])
 177 {
 178         unsigned long mmcr1 = 0;
 179         unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
 180         int i;
 181         unsigned int pmc, ev, b, u, s, psel;
 182         unsigned int ttmset = 0;
 183         unsigned int pmc_inuse = 0;
 184
 185         if (n_ev > 6)
 186                 return -1;
 187         for (i = 0; i < n_ev; ++i) {
 188                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 189                 if (pmc) {
 190                         if (pmc_inuse & (1 << (pmc - 1)))
 191                                 return -1;      /* collision! */
 192                         pmc_inuse |= 1 << (pmc - 1);
 193                 }
 194         }
 195         for (i = 0; i < n_ev; ++i) {
 196                 ev = event[i];
 197                 pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
 198                 if (pmc) {
 199                         --pmc;
 200                 } else {
 201                         /* can go on any PMC; find a free one */
 202                         for (pmc = 0; pmc < 4; ++pmc)
 203                                 if (!(pmc_inuse & (1 << pmc)))
 204                                         break;
 205                         if (pmc >= 4)
 206                                 return -1;
 207                         pmc_inuse |= 1 << pmc;
 208                 }
 209                 hwc[i] = pmc;
 210                 psel = ev & PM_PMCSEL_MSK;
 211                 if (ev & PM_BUSEVENT_MSK) {
 212                         /* this event uses the event bus */
 213                         b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
 214                         u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
 215                         /* check for conflict on this byte of event bus */
 216                         if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
 217                                 return -1;
 218                         mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
 219                         ttmset |= 1 << b;
 220                         if (u == 5) {
 221                                 /* Nest events have a further mux */
 222                                 s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
 223                                 if ((ttmset & 0x10) &&
 224                                     MMCR1_NESTSEL(mmcr1) != s)
 225                                         return -1;
 226                                 ttmset |= 0x10;
 227                                 mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
 228                         }
 229                         if (0x30 <= psel && psel <= 0x3d) {
 230                                 /* these need the PMCx_ADDR_SEL bits */
 231                                 if (b >= 2)
 232                                         mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
 233                         }
 234                         /* bus select values are different for PMC3/4 */
 235                         if (pmc >= 2 && (psel & 0x90) == 0x80)
 236                                 psel ^= 0x20;
 237                 }
 238                 if (ev & PM_LLA) {
 239                         mmcr1 |= MMCR1_PMC1_LLA >> pmc;
 240                         if (ev & PM_LLAV)
 241                                 mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
 242                 }
 243                 if (power6_marked_instr_event(event[i]))
 244                         mmcra |= MMCRA_SAMPLE_ENABLE;
 245                 if (pmc < 4)
 246                         mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
 247         }
 248         mmcr->mmcr0 = 0;
 249         if (pmc_inuse & 1)
 250                 mmcr->mmcr0 = MMCR0_PMC1CE;
 251         if (pmc_inuse & 0xe)
 252                 mmcr->mmcr0 |= MMCR0_PMCjCE;
 253         mmcr->mmcr1 = mmcr1;
 254         mmcr->mmcra = mmcra;
 255         return 0;
 256 }
 257
 258 /*
 259  * Layout of constraint bits:
 260  *
 261  *      0-1     add field: number of uses of PMC1 (max 1)
 262  *      2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
 263  *      12-15   add field: number of uses of PMC1-4 (max 4)
 264  *      16-19   select field: unit on byte 0 of event bus
 265  *      20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
 266  *      32-34   select field: nest (subunit) event selector
 267  */
 268 static int p6_get_constraint(u64 event, unsigned long *maskp,
 269                              unsigned long *valp)
 270 {
 271         int pmc, byte, sh, subunit;
 272         unsigned long mask = 0, value = 0;
 273
 274         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 275         if (pmc) {
 276                 if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
 277                         return -1;
 278                 sh = (pmc - 1) * 2;
 279                 mask |= 2 << sh;
 280                 value |= 1 << sh;
 281         }
 282         if (event & PM_BUSEVENT_MSK) {
 283                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 284                 sh = byte * 4 + (16 - PM_UNIT_SH);
 285                 mask |= PM_UNIT_MSKS << sh;
 286                 value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
 287                 if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
 288                         subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
 289                         mask  |= (unsigned long)PM_SUBUNIT_MSK << 32;
 290                         value |= (unsigned long)subunit << 32;
 291                 }
 292         }
 293         if (pmc <= 4) {
 294                 mask  |= 0x8000;        /* add field for count of PMC1-4 uses */
 295                 value |= 0x1000;
 296         }
 297         *maskp = mask;
 298         *valp = value;
 299         return 0;
 300 }
 301
 302 static int p6_limited_pmc_event(u64 event)
 303 {
 304         int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 305
 306         return pmc == 5 || pmc == 6;
 307 }
 308
 309 #define MAX_ALT 4       /* at most 4 alternatives for any event */
 310
 311 static const unsigned int event_alternatives[][MAX_ALT] = {
 312         { 0x0130e8, 0x2000f6, 0x3000fc },       /* PM_PTEG_RELOAD_VALID */
 313         { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
 314         { 0x080088, 0x200054, 0x3000f0 },       /* PM_ST_MISS_L1 */
 315         { 0x10000a, 0x2000f4, 0x600005 },       /* PM_RUN_CYC */
 316         { 0x10000b, 0x2000f5 },                 /* PM_RUN_COUNT */
 317         { 0x10000e, 0x400010 },                 /* PM_PURR */
 318         { 0x100010, 0x4000f8 },                 /* PM_FLUSH */
 319         { 0x10001a, 0x200010 },                 /* PM_MRK_INST_DISP */
 320         { 0x100026, 0x3000f8 },                 /* PM_TB_BIT_TRANS */
 321         { 0x100054, 0x2000f0 },                 /* PM_ST_FIN */
 322         { 0x100056, 0x2000fc },                 /* PM_L1_ICACHE_MISS */
 323         { 0x1000f0, 0x40000a },                 /* PM_INST_IMC_MATCH_CMPL */
 324         { 0x1000f8, 0x200008 },                 /* PM_GCT_EMPTY_CYC */
 325         { 0x1000fc, 0x400006 },                 /* PM_LSU_DERAT_MISS_CYC */
 326         { 0x20000e, 0x400007 },                 /* PM_LSU_DERAT_MISS */
 327         { 0x200012, 0x300012 },                 /* PM_INST_DISP */
 328         { 0x2000f2, 0x3000f2 },                 /* PM_INST_DISP */
 329         { 0x2000f8, 0x300010 },                 /* PM_EXT_INT */
 330         { 0x2000fe, 0x300056 },                 /* PM_DATA_FROM_L2MISS */
 331         { 0x2d0030, 0x30001a },                 /* PM_MRK_FPU_FIN */
 332         { 0x30000a, 0x400018 },                 /* PM_MRK_INST_FIN */
 333         { 0x3000f6, 0x40000e },                 /* PM_L1_DCACHE_RELOAD_VALID */
 334         { 0x3000fe, 0x400056 },                 /* PM_DATA_FROM_L3MISS */
 335 };
 336
 337 /*
 338  * This could be made more efficient with a binary search on
 339  * a presorted list, if necessary
 340  */
 341 static int find_alternatives_list(u64 event)
 342 {
 343         int i, j;
 344         unsigned int alt;
 345
 346         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 347                 if (event < event_alternatives[i][0])
 348                         return -1;
 349                 for (j = 0; j < MAX_ALT; ++j) {
 350                         alt = event_alternatives[i][j];
 351                         if (!alt || event < alt)
 352                                 break;
 353                         if (event == alt)
 354                                 return i;
 355                 }
 356         }
 357         return -1;
 358 }
 359
 360 static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 361 {
 362         int i, j, nlim;
 363         unsigned int psel, pmc;
 364         unsigned int nalt = 1;
 365         u64 aevent;
 366
 367         alt[0] = event;
 368         nlim = p6_limited_pmc_event(event);
 369
 370         /* check the alternatives table */
 371         i = find_alternatives_list(event);
 372         if (i >= 0) {
 373                 /* copy out alternatives from list */
 374                 for (j = 0; j < MAX_ALT; ++j) {
 375                         aevent = event_alternatives[i][j];
 376                         if (!aevent)
 377                                 break;
 378                         if (aevent != event)
 379                                 alt[nalt++] = aevent;
 380                         nlim += p6_limited_pmc_event(aevent);
 381                 }
 382
 383         } else {
 384                 /* Check for alternative ways of computing sum events */
 385                 /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
 386                 psel = event & (PM_PMCSEL_MSK & ~1);    /* ignore edge bit */
 387                 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 388                 if (pmc && (psel == 0x32 || psel == 0x34))
 389                         alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
 390                                 ((5 - pmc) << PM_PMC_SH);
 391
 392                 /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
 393                 if (pmc && (psel == 0x38 || psel == 0x3a))
 394                         alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
 395                                 ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
 396         }
 397
 398         if (flags & PPMU_ONLY_COUNT_RUN) {
 399                 /*
 400                  * We're only counting in RUN state,
 401                  * so PM_CYC is equivalent to PM_RUN_CYC,
 402                  * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
 403                  * This doesn't include alternatives that don't provide
 404                  * any extra flexibility in assigning PMCs (e.g.
 405                  * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
 406                  * Note that even with these additional alternatives
 407                  * we never end up with more than 4 alternatives for any event.
 408                  */
 409                 j = nalt;
 410                 for (i = 0; i < nalt; ++i) {
 411                         switch (alt[i]) {
 412                         case 0x1e:      /* PM_CYC */
 413                                 alt[j++] = 0x600005;    /* PM_RUN_CYC */
 414                                 ++nlim;
 415                                 break;
 416                         case 0x10000a:  /* PM_RUN_CYC */
 417                                 alt[j++] = 0x1e;        /* PM_CYC */
 418                                 break;
 419                         case 2:         /* PM_INST_CMPL */
 420                                 alt[j++] = 0x500009;    /* PM_RUN_INST_CMPL */
 421                                 ++nlim;
 422                                 break;
 423                         case 0x500009:  /* PM_RUN_INST_CMPL */
 424                                 alt[j++] = 2;           /* PM_INST_CMPL */
 425                                 break;
 426                         case 0x10000e:  /* PM_PURR */
 427                                 alt[j++] = 0x4000f4;    /* PM_RUN_PURR */
 428                                 break;
 429                         case 0x4000f4:  /* PM_RUN_PURR */
 430                                 alt[j++] = 0x10000e;    /* PM_PURR */
 431                                 break;
 432                         }
 433                 }
 434                 nalt = j;
 435         }
 436
 437         if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
 438                 /* remove the limited PMC events */
 439                 j = 0;
 440                 for (i = 0; i < nalt; ++i) {
 441                         if (!p6_limited_pmc_event(alt[i])) {
 442                                 alt[j] = alt[i];
 443                                 ++j;
 444                         }
 445                 }
 446                 nalt = j;
 447         } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
 448                 /* remove all but the limited PMC events */
 449                 j = 0;
 450                 for (i = 0; i < nalt; ++i) {
 451                         if (p6_limited_pmc_event(alt[i])) {
 452                                 alt[j] = alt[i];
 453                                 ++j;
 454                         }
 455                 }
 456                 nalt = j;
 457         }
 458
 459         return nalt;
 460 }
 461
 462 static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
 463 {
 464         /* Set PMCxSEL to 0 to disable PMCx */
 465         if (pmc <= 3)
 466                 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
 467 }
 468
 469 static int power6_generic_events[] = {
 470         [PERF_COUNT_HW_CPU_CYCLES]              = 0x1e,
 471         [PERF_COUNT_HW_INSTRUCTIONS]            = 2,
 472         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x280030, /* LD_REF_L1 */
 473         [PERF_COUNT_HW_CACHE_MISSES]            = 0x30000c, /* LD_MISS_L1 */
 474         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x410a0,  /* BR_PRED */
 475         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x400052, /* BR_MPRED */
 476 };
 477
 478 #define C(x)    PERF_COUNT_HW_CACHE_##x
 479
 480 /*
 481  * Table of generalized cache-related events.
 482  * 0 means not supported, -1 means nonsensical, other values
 483  * are event codes.
 484  * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
 485  */
 486 static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 487         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 488                 [C(OP_READ)] = {        0x280030,       0x80080         },
 489                 [C(OP_WRITE)] = {       0x180032,       0x80088         },
 490                 [C(OP_PREFETCH)] = {    0x810a4,        0               },
 491         },
 492         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 493                 [C(OP_READ)] = {        0,              0x100056        },
 494                 [C(OP_WRITE)] = {       -1,             -1              },
 495                 [C(OP_PREFETCH)] = {    0x4008c,        0               },
 496         },
 497         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 498                 [C(OP_READ)] = {        0x150730,       0x250532        },
 499                 [C(OP_WRITE)] = {       0x250432,       0x150432        },
 500                 [C(OP_PREFETCH)] = {    0x810a6,        0               },
 501         },
 502         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 503                 [C(OP_READ)] = {        0,              0x20000e        },
 504                 [C(OP_WRITE)] = {       -1,             -1              },
 505                 [C(OP_PREFETCH)] = {    -1,             -1              },
 506         },
 507         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 508                 [C(OP_READ)] = {        0,              0x420ce         },
 509                 [C(OP_WRITE)] = {       -1,             -1              },
 510                 [C(OP_PREFETCH)] = {    -1,             -1              },
 511         },
 512         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 513                 [C(OP_READ)] = {        0x430e6,        0x400052        },
 514                 [C(OP_WRITE)] = {       -1,             -1              },
 515                 [C(OP_PREFETCH)] = {    -1,             -1              },
 516         },
 517         [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 518                 [C(OP_READ)] = {        -1,             -1              },
 519                 [C(OP_WRITE)] = {       -1,             -1              },
 520                 [C(OP_PREFETCH)] = {    -1,             -1              },
 521         },
 522 };
 523
 524 static struct power_pmu power6_pmu = {
 525         .name                   = "POWER6",
 526         .n_counter              = 6,
 527         .max_alternatives       = MAX_ALT,
 528         .add_fields             = 0x1555,
 529         .test_adder             = 0x3000,
 530         .compute_mmcr           = p6_compute_mmcr,
 531         .get_constraint         = p6_get_constraint,
 532         .get_alternatives       = p6_get_alternatives,
 533         .disable_pmc            = p6_disable_pmc,
 534         .limited_pmc_event      = p6_limited_pmc_event,
 535         .flags                  = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
 536         .n_generic              = ARRAY_SIZE(power6_generic_events),
 537         .generic_events         = power6_generic_events,
 538         .cache_events           = &power6_cache_events,
 539 };
 540
 541 int init_power6_pmu(void)
 542 {
 543         if (!cur_cpu_spec->oprofile_cpu_type ||
 544             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
 545                 return -ENODEV;
 546
 547         return register_power_pmu(&power6_pmu);
 548 }