arch/powerpc/sysdev/fsl_pci.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * MPC85xx/86xx PCI Express structure define
   4  *
   5  * Copyright 2007,2011 Freescale Semiconductor, Inc
   6  */
   7
   8 #ifdef __KERNEL__
   9 #ifndef __POWERPC_FSL_PCI_H
  10 #define __POWERPC_FSL_PCI_H
  11
  12 struct platform_device;
  13
  14
  15 /* FSL PCI controller BRR1 register */
  16 #define PCI_FSL_BRR1      0xbf8
  17 #define PCI_FSL_BRR1_VER 0xffff
  18
  19 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
  20 #define PCIE_LTSSM_L0   0x16            /* L0 state */
  21 #define PCIE_IP_REV_2_2         0x02080202 /* PCIE IP block version Rev2.2 */
  22 #define PCIE_IP_REV_3_0         0x02080300 /* PCIE IP block version Rev3.0 */
  23 #define PIWAR_EN                0x80000000      /* Enable */
  24 #define PIWAR_PF                0x20000000      /* prefetch */
  25 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
  26 #define PIWAR_READ_SNOOP        0x00050000
  27 #define PIWAR_WRITE_SNOOP       0x00005000
  28 #define PIWAR_SZ_MASK          0x0000003f
  29
  30 #define PEX_PMCR_PTOMR          0x1
  31 #define PEX_PMCR_EXL2S          0x2
  32
  33 #define PME_DISR_EN_PTOD        0x00008000
  34 #define PME_DISR_EN_ENL23D      0x00002000
  35 #define PME_DISR_EN_EXL23D      0x00001000
  36
  37 /* PCI/PCI Express outbound window reg */
  38 struct pci_outbound_window_regs {
  39         __be32  potar;  /* 0x.0 - Outbound translation address register */
  40         __be32  potear; /* 0x.4 - Outbound translation extended address register */
  41         __be32  powbar; /* 0x.8 - Outbound window base address register */
  42         u8      res1[4];
  43         __be32  powar;  /* 0x.10 - Outbound window attributes register */
  44         u8      res2[12];
  45 };
  46
  47 /* PCI/PCI Express inbound window reg */
  48 struct pci_inbound_window_regs {
  49         __be32  pitar;  /* 0x.0 - Inbound translation address register */
  50         u8      res1[4];
  51         __be32  piwbar; /* 0x.8 - Inbound window base address register */
  52         __be32  piwbear;        /* 0x.c - Inbound window base extended address register */
  53         __be32  piwar;  /* 0x.10 - Inbound window attributes register */
  54         u8      res2[12];
  55 };
  56
  57 /* PCI/PCI Express IO block registers for 85xx/86xx */
  58 struct ccsr_pci {
  59         __be32  config_addr;            /* 0x.000 - PCI/PCIE Configuration Address Register */
  60         __be32  config_data;            /* 0x.004 - PCI/PCIE Configuration Data Register */
  61         __be32  int_ack;                /* 0x.008 - PCI Interrupt Acknowledge Register */
  62         __be32  pex_otb_cpl_tor;        /* 0x.00c - PCIE Outbound completion timeout register */
  63         __be32  pex_conf_tor;           /* 0x.010 - PCIE configuration timeout register */
  64         __be32  pex_config;             /* 0x.014 - PCIE CONFIG Register */
  65         __be32  pex_int_status;         /* 0x.018 - PCIE interrupt status */
  66         u8      res2[4];
  67         __be32  pex_pme_mes_dr;         /* 0x.020 - PCIE PME and message detect register */
  68         __be32  pex_pme_mes_disr;       /* 0x.024 - PCIE PME and message disable register */
  69         __be32  pex_pme_mes_ier;        /* 0x.028 - PCIE PME and message interrupt enable register */
  70         __be32  pex_pmcr;               /* 0x.02c - PCIE power management command register */
  71         u8      res3[3016];
  72         __be32  block_rev1;     /* 0x.bf8 - PCIE Block Revision register 1 */
  73         __be32  block_rev2;     /* 0x.bfc - PCIE Block Revision register 2 */
  74
  75 /* PCI/PCI Express outbound window 0-4
  76  * Window 0 is the default window and is the only window enabled upon reset.
  77  * The default outbound register set is used when a transaction misses
  78  * in all of the other outbound windows.
  79  */
  80         struct pci_outbound_window_regs pow[5];
  81         u8      res14[96];
  82         struct pci_inbound_window_regs  pmit;   /* 0xd00 - 0xd9c Inbound MSI */
  83         u8      res6[96];
  84 /* PCI/PCI Express inbound window 3-0
  85  * inbound window 1 supports only a 32-bit base address and does not
  86  * define an inbound window base extended address register.
  87  */
  88         struct pci_inbound_window_regs piw[4];
  89
  90         __be32  pex_err_dr;             /* 0x.e00 - PCI/PCIE error detect register */
  91         u8      res21[4];
  92         __be32  pex_err_en;             /* 0x.e08 - PCI/PCIE error interrupt enable register */
  93         u8      res22[4];
  94         __be32  pex_err_disr;           /* 0x.e10 - PCI/PCIE error disable register */
  95         u8      res23[12];
  96         __be32  pex_err_cap_stat;       /* 0x.e20 - PCI/PCIE error capture status register */
  97         u8      res24[4];
  98         __be32  pex_err_cap_r0;         /* 0x.e28 - PCIE error capture register 0 */
  99         __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
 100         __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
 101         __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
 102         u8      res_e38[200];
 103         __be32  pdb_stat;               /* 0x.f00 - PCIE Debug Status */
 104         u8      res_f04[16];
 105         __be32  pex_csr0;               /* 0x.f14 - PEX Control/Status register 0*/
 106 #define PEX_CSR0_LTSSM_MASK     0xFC
 107 #define PEX_CSR0_LTSSM_SHIFT    2
 108 #define PEX_CSR0_LTSSM_L0       0x11
 109         __be32  pex_csr1;               /* 0x.f18 - PEX Control/Status register 1*/
 110         u8      res_f1c[228];
 111
 112 };
 113
 114 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
 115 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
 116 extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
 117 extern int mpc83xx_add_bridge(struct device_node *dev);
 118 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
 119
 120 extern struct device_node *fsl_pci_primary;
 121
 122 #ifdef CONFIG_PCI
 123 void fsl_pci_assign_primary(void);
 124 #else
 125 static inline void fsl_pci_assign_primary(void) {}
 126 #endif
 127
 128 #ifdef CONFIG_FSL_PCI
 129 extern int fsl_pci_mcheck_exception(struct pt_regs *);
 130 #else
 131 static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
 132 #endif
 133
 134 #endif /* __POWERPC_FSL_PCI_H */
 135 #endif /* __KERNEL__ */