1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006, Segher Boessenkool, IBM Corporation.
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
11 #include <asm/hw_irq.h>
12 #include <asm/ppc-pci.h>
13 #include <asm/msi_bitmap.h>
17 /* A bit ugly, can we get this from the pci_dev somehow? */
18 static struct mpic
*msi_mpic
;
20 static void mpic_u3msi_mask_irq(struct irq_data
*data
)
22 pci_msi_mask_irq(data
);
26 static void mpic_u3msi_unmask_irq(struct irq_data
*data
)
28 mpic_unmask_irq(data
);
29 pci_msi_unmask_irq(data
);
32 static struct irq_chip mpic_u3msi_chip
= {
33 .irq_shutdown
= mpic_u3msi_mask_irq
,
34 .irq_mask
= mpic_u3msi_mask_irq
,
35 .irq_unmask
= mpic_u3msi_unmask_irq
,
36 .irq_eoi
= mpic_end_irq
,
37 .irq_set_type
= mpic_set_irq_type
,
38 .irq_set_affinity
= mpic_set_affinity
,
42 static u64
read_ht_magic_addr(struct pci_dev
*pdev
, unsigned int pos
)
48 pci_read_config_byte(pdev
, pos
+ HT_MSI_FLAGS
, &flags
);
50 if (flags
& HT_MSI_FLAGS_FIXED
)
51 return HT_MSI_FIXED_ADDR
;
53 pci_read_config_dword(pdev
, pos
+ HT_MSI_ADDR_LO
, &tmp
);
54 addr
= tmp
& HT_MSI_ADDR_LO_MASK
;
55 pci_read_config_dword(pdev
, pos
+ HT_MSI_ADDR_HI
, &tmp
);
56 addr
= addr
| ((u64
)tmp
<< 32);
61 static u64
find_ht_magic_addr(struct pci_dev
*pdev
, unsigned int hwirq
)
66 for (bus
= pdev
->bus
; bus
&& bus
->self
; bus
= bus
->parent
) {
67 pos
= pci_find_ht_capability(bus
->self
, HT_CAPTYPE_MSI_MAPPING
);
69 return read_ht_magic_addr(bus
->self
, pos
);
75 static u64
find_u4_magic_addr(struct pci_dev
*pdev
, unsigned int hwirq
)
77 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
79 /* U4 PCIe MSIs need to write to the special register in
80 * the bridge that generates interrupts. There should be
81 * theorically a register at 0xf8005000 where you just write
82 * the MSI number and that triggers the right interrupt, but
83 * unfortunately, this is busted in HW, the bridge endian swaps
84 * the value and hits the wrong nibble in the register.
86 * So instead we use another register set which is used normally
87 * for converting HT interrupts to MPIC interrupts, which decodes
88 * the interrupt number as part of the low address bits
90 * This will not work if we ever use more than one legacy MSI in
91 * a block but we never do. For one MSI or multiple MSI-X where
92 * each interrupt address can be specified separately, it works
95 if (of_device_is_compatible(hose
->dn
, "u4-pcie") ||
96 of_device_is_compatible(hose
->dn
, "U4-pcie"))
97 return 0xf8004000 | (hwirq
<< 4);
102 static void u3msi_teardown_msi_irqs(struct pci_dev
*pdev
)
104 struct msi_desc
*entry
;
105 irq_hw_number_t hwirq
;
107 for_each_pci_msi_entry(entry
, pdev
) {
111 hwirq
= virq_to_hw(entry
->irq
);
112 irq_set_msi_desc(entry
->irq
, NULL
);
113 irq_dispose_mapping(entry
->irq
);
114 msi_bitmap_free_hwirqs(&msi_mpic
->msi_bitmap
, hwirq
, 1);
120 static int u3msi_setup_msi_irqs(struct pci_dev
*pdev
, int nvec
, int type
)
123 struct msi_desc
*entry
;
128 if (type
== PCI_CAP_ID_MSIX
)
129 pr_debug("u3msi: MSI-X untested, trying anyway.\n");
131 /* If we can't find a magic address then MSI ain't gonna work */
132 if (find_ht_magic_addr(pdev
, 0) == 0 &&
133 find_u4_magic_addr(pdev
, 0) == 0) {
134 pr_debug("u3msi: no magic address found for %s\n",
139 for_each_pci_msi_entry(entry
, pdev
) {
140 hwirq
= msi_bitmap_alloc_hwirqs(&msi_mpic
->msi_bitmap
, 1);
142 pr_debug("u3msi: failed allocating hwirq\n");
146 addr
= find_ht_magic_addr(pdev
, hwirq
);
148 addr
= find_u4_magic_addr(pdev
, hwirq
);
149 msg
.address_lo
= addr
& 0xFFFFFFFF;
150 msg
.address_hi
= addr
>> 32;
152 virq
= irq_create_mapping(msi_mpic
->irqhost
, hwirq
);
154 pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq
);
155 msi_bitmap_free_hwirqs(&msi_mpic
->msi_bitmap
, hwirq
, 1);
159 irq_set_msi_desc(virq
, entry
);
160 irq_set_chip(virq
, &mpic_u3msi_chip
);
161 irq_set_irq_type(virq
, IRQ_TYPE_EDGE_RISING
);
163 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
164 virq
, hwirq
, (unsigned long)addr
);
166 printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
167 virq
, hwirq
, (unsigned long)addr
);
169 pci_write_msi_msg(virq
, &msg
);
177 int mpic_u3msi_init(struct mpic
*mpic
)
180 struct pci_controller
*phb
;
182 rc
= mpic_msi_init_allocator(mpic
);
184 pr_debug("u3msi: Error allocating bitmap!\n");
188 pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
193 list_for_each_entry(phb
, &hose_list
, list_node
) {
194 WARN_ON(phb
->controller_ops
.setup_msi_irqs
);
195 phb
->controller_ops
.setup_msi_irqs
= u3msi_setup_msi_irqs
;
196 phb
->controller_ops
.teardown_msi_irqs
= u3msi_teardown_msi_irqs
;