arch/sh/drivers/pci/ops-sh7786.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Generic SH7786 PCI-Express operations.
   4  *
   5  *  Copyright (C) 2009 - 2010  Paul Mundt
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/pci.h>
  10 #include <linux/io.h>
  11 #include <linux/spinlock.h>
  12 #include "pcie-sh7786.h"
  13
  14 enum {
  15         PCI_ACCESS_READ,
  16         PCI_ACCESS_WRITE,
  17 };
  18
  19 static int sh7786_pcie_config_access(unsigned char access_type,
  20                 struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
  21 {
  22         struct pci_channel *chan = bus->sysdata;
  23         int dev, func, type, reg;
  24
  25         dev = PCI_SLOT(devfn);
  26         func = PCI_FUNC(devfn);
  27         type = !!bus->parent;
  28         reg = where & ~3;
  29
  30         if (bus->number > 255 || dev > 31 || func > 7)
  31                 return PCIBIOS_FUNC_NOT_SUPPORTED;
  32
  33         /*
  34          * While each channel has its own memory-mapped extended config
  35          * space, it's generally only accessible when in endpoint mode.
  36          * When in root complex mode, the controller is unable to target
  37          * itself with either type 0 or type 1 accesses, and indeed, any
  38          * controller initiated target transfer to its own config space
  39          * result in a completer abort.
  40          *
  41          * Each channel effectively only supports a single device, but as
  42          * the same channel <-> device access works for any PCI_SLOT()
  43          * value, we cheat a bit here and bind the controller's config
  44          * space to devfn 0 in order to enable self-enumeration. In this
  45          * case the regular PAR/PDR path is sidelined and the mangled
  46          * config access itself is initiated as a SuperHyway transaction.
  47          */
  48         if (pci_is_root_bus(bus)) {
  49                 if (dev == 0) {
  50                         if (access_type == PCI_ACCESS_READ)
  51                                 *data = pci_read_reg(chan, PCI_REG(reg));
  52                         else
  53                                 pci_write_reg(chan, *data, PCI_REG(reg));
  54
  55                         return PCIBIOS_SUCCESSFUL;
  56                 } else if (dev > 1)
  57                         return PCIBIOS_DEVICE_NOT_FOUND;
  58         }
  59
  60         /* Clear errors */
  61         pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
  62
  63         /* Set the PIO address */
  64         pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
  65                                 (func << 16) | reg, SH4A_PCIEPAR);
  66
  67         /* Enable the configuration access */
  68         pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
  69
  70         /* Check for errors */
  71         if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
  72                 return PCIBIOS_DEVICE_NOT_FOUND;
  73
  74         /* Check for master and target aborts */
  75         if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
  76                 return PCIBIOS_DEVICE_NOT_FOUND;
  77
  78         if (access_type == PCI_ACCESS_READ)
  79                 *data = pci_read_reg(chan, SH4A_PCIEPDR);
  80         else
  81                 pci_write_reg(chan, *data, SH4A_PCIEPDR);
  82
  83         /* Disable the configuration access */
  84         pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
  85
  86         return PCIBIOS_SUCCESSFUL;
  87 }
  88
  89 static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
  90                             int where, int size, u32 *val)
  91 {
  92         unsigned long flags;
  93         int ret;
  94         u32 data;
  95
  96         if ((size == 2) && (where & 1))
  97                 return PCIBIOS_BAD_REGISTER_NUMBER;
  98         else if ((size == 4) && (where & 3))
  99                 return PCIBIOS_BAD_REGISTER_NUMBER;
 100
 101         raw_spin_lock_irqsave(&pci_config_lock, flags);
 102         ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
 103                                         devfn, where, &data);
 104         if (ret != PCIBIOS_SUCCESSFUL) {
 105                 *val = 0xffffffff;
 106                 goto out;
 107         }
 108
 109         if (size == 1)
 110                 *val = (data >> ((where & 3) << 3)) & 0xff;
 111         else if (size == 2)
 112                 *val = (data >> ((where & 2) << 3)) & 0xffff;
 113         else
 114                 *val = data;
 115
 116         dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
 117                 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
 118                 devfn, where, size, (unsigned long)*val);
 119
 120 out:
 121         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 122         return ret;
 123 }
 124
 125 static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
 126                              int where, int size, u32 val)
 127 {
 128         unsigned long flags;
 129         int shift, ret;
 130         u32 data;
 131
 132         if ((size == 2) && (where & 1))
 133                 return PCIBIOS_BAD_REGISTER_NUMBER;
 134         else if ((size == 4) && (where & 3))
 135                 return PCIBIOS_BAD_REGISTER_NUMBER;
 136
 137         raw_spin_lock_irqsave(&pci_config_lock, flags);
 138         ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
 139                                         devfn, where, &data);
 140         if (ret != PCIBIOS_SUCCESSFUL)
 141                 goto out;
 142
 143         dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
 144                 "where=0x%04x size=%d val=%08lx\n", bus->number,
 145                 devfn, where, size, (unsigned long)val);
 146
 147         if (size == 1) {
 148                 shift = (where & 3) << 3;
 149                 data &= ~(0xff << shift);
 150                 data |= ((val & 0xff) << shift);
 151         } else if (size == 2) {
 152                 shift = (where & 2) << 3;
 153                 data &= ~(0xffff << shift);
 154                 data |= ((val & 0xffff) << shift);
 155         } else
 156                 data = val;
 157
 158         ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
 159                                         devfn, where, &data);
 160 out:
 161         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 162         return ret;
 163 }
 164
 165 struct pci_ops sh7786_pci_ops = {
 166         .read   = sh7786_pcie_read,
 167         .write  = sh7786_pcie_write,
 168 };