arch/sh/kernel/cpu/sh2a/setup-sh7206.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7206 Setup
   4  *
   5  *  Copyright (C) 2006  Yoshinori Sato
   6  *  Copyright (C) 2009  Paul Mundt
   7  */
   8 #include <linux/platform_device.h>
   9 #include <linux/init.h>
  10 #include <linux/serial.h>
  11 #include <linux/serial_sci.h>
  12 #include <linux/sh_timer.h>
  13 #include <linux/io.h>
  14 #include <asm/platform_early.h>
  15
  16 enum {
  17         UNUSED = 0,
  18
  19         /* interrupt sources */
  20         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  21         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  22         ADC_ADI0, ADC_ADI1,
  23
  24         DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  25
  26         MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  27         MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
  28         IIC3,
  29
  30         CMT0, CMT1, BSC, WDT,
  31
  32         MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
  33
  34         POE2_OEI3,
  35
  36         SCIF0, SCIF1, SCIF2, SCIF3,
  37
  38         /* interrupt groups */
  39         PINT,
  40 };
  41
  42 static struct intc_vect vectors[] __initdata = {
  43         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  44         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  45         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  46         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  47         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  48         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  49         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  50         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  51         INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
  52         INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
  53         INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
  54         INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
  55         INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
  56         INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
  57         INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
  58         INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
  59         INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
  60         INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
  61         INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
  62         INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
  63         INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
  64         INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
  65         INTC_IRQ(MTU0_VEF, 162),
  66         INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
  67         INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
  68         INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
  69         INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
  70         INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
  71         INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
  72         INTC_IRQ(MTU2_TCI3V, 184),
  73         INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
  74         INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
  75         INTC_IRQ(MTU2_TCI4V, 192),
  76         INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
  77         INTC_IRQ(MTU5, 198),
  78         INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
  79         INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
  80         INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
  81         INTC_IRQ(MTU2S_TCI3V, 208),
  82         INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
  83         INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
  84         INTC_IRQ(MTU2S_TCI4V, 216),
  85         INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
  86         INTC_IRQ(MTU5S, 222),
  87         INTC_IRQ(POE2_OEI3, 224),
  88         INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
  89         INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
  90         INTC_IRQ(IIC3, 232),
  91         INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
  92         INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
  93         INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
  94         INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
  95         INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
  96         INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
  97         INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
  98         INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
  99 };
 100
 101 static struct intc_group groups[] __initdata = {
 102         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 103                    PINT4, PINT5, PINT6, PINT7),
 104 };
 105
 106 static struct intc_prio_reg prio_registers[] __initdata = {
 107         { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 108         { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 109         { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
 110         { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
 111         { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
 112         { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
 113         { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
 114                                               MTU1_AB, MTU1_VU } },
 115         { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
 116                                               MTU3_ABCD, MTU2_TCI3V } },
 117         { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
 118                                               MTU5, POE2_12 } },
 119         { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
 120                                               MTU4S_ABCD, MTU2S_TCI4V } },
 121         { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
 122         { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
 123 };
 124
 125 static struct intc_mask_reg mask_registers[] __initdata = {
 126         { 0xfffe0808, 0, 16, /* PINTER */
 127           { 0, 0, 0, 0, 0, 0, 0, 0,
 128             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 129 };
 130
 131 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
 132                          mask_registers, prio_registers, NULL);
 133
 134 static struct plat_sci_port scif0_platform_data = {
 135         .scscr          = SCSCR_REIE,
 136         .type           = PORT_SCIF,
 137 };
 138
 139 static struct resource scif0_resources[] = {
 140         DEFINE_RES_MEM(0xfffe8000, 0x100),
 141         DEFINE_RES_IRQ(240),
 142 };
 143
 144 static struct platform_device scif0_device = {
 145         .name           = "sh-sci",
 146         .id             = 0,
 147         .resource       = scif0_resources,
 148         .num_resources  = ARRAY_SIZE(scif0_resources),
 149         .dev            = {
 150                 .platform_data  = &scif0_platform_data,
 151         },
 152 };
 153
 154 static struct plat_sci_port scif1_platform_data = {
 155         .scscr          = SCSCR_REIE,
 156         .type           = PORT_SCIF,
 157 };
 158
 159 static struct resource scif1_resources[] = {
 160         DEFINE_RES_MEM(0xfffe8800, 0x100),
 161         DEFINE_RES_IRQ(244),
 162 };
 163
 164 static struct platform_device scif1_device = {
 165         .name           = "sh-sci",
 166         .id             = 1,
 167         .resource       = scif1_resources,
 168         .num_resources  = ARRAY_SIZE(scif1_resources),
 169         .dev            = {
 170                 .platform_data  = &scif1_platform_data,
 171         },
 172 };
 173
 174 static struct plat_sci_port scif2_platform_data = {
 175         .scscr          = SCSCR_REIE,
 176         .type           = PORT_SCIF,
 177 };
 178
 179 static struct resource scif2_resources[] = {
 180         DEFINE_RES_MEM(0xfffe9000, 0x100),
 181         DEFINE_RES_IRQ(248),
 182 };
 183
 184 static struct platform_device scif2_device = {
 185         .name           = "sh-sci",
 186         .id             = 2,
 187         .resource       = scif2_resources,
 188         .num_resources  = ARRAY_SIZE(scif2_resources),
 189         .dev            = {
 190                 .platform_data  = &scif2_platform_data,
 191         },
 192 };
 193
 194 static struct plat_sci_port scif3_platform_data = {
 195         .scscr          = SCSCR_REIE,
 196         .type           = PORT_SCIF,
 197 };
 198
 199 static struct resource scif3_resources[] = {
 200         DEFINE_RES_MEM(0xfffe9800, 0x100),
 201         DEFINE_RES_IRQ(252),
 202 };
 203
 204 static struct platform_device scif3_device = {
 205         .name           = "sh-sci",
 206         .id             = 3,
 207         .resource       = scif3_resources,
 208         .num_resources  = ARRAY_SIZE(scif3_resources),
 209         .dev            = {
 210                 .platform_data  = &scif3_platform_data,
 211         },
 212 };
 213
 214 static struct sh_timer_config cmt_platform_data = {
 215         .channels_mask = 3,
 216 };
 217
 218 static struct resource cmt_resources[] = {
 219         DEFINE_RES_MEM(0xfffec000, 0x10),
 220         DEFINE_RES_IRQ(140),
 221         DEFINE_RES_IRQ(144),
 222 };
 223
 224 static struct platform_device cmt_device = {
 225         .name           = "sh-cmt-16",
 226         .id             = 0,
 227         .dev = {
 228                 .platform_data  = &cmt_platform_data,
 229         },
 230         .resource       = cmt_resources,
 231         .num_resources  = ARRAY_SIZE(cmt_resources),
 232 };
 233
 234 static struct resource mtu2_resources[] = {
 235         DEFINE_RES_MEM(0xfffe4000, 0x400),
 236         DEFINE_RES_IRQ_NAMED(156, "tgi0a"),
 237         DEFINE_RES_IRQ_NAMED(164, "tgi1a"),
 238         DEFINE_RES_IRQ_NAMED(180, "tgi2a"),
 239 };
 240
 241 static struct platform_device mtu2_device = {
 242         .name           = "sh-mtu2s",
 243         .id             = -1,
 244         .resource       = mtu2_resources,
 245         .num_resources  = ARRAY_SIZE(mtu2_resources),
 246 };
 247
 248 static struct platform_device *sh7206_devices[] __initdata = {
 249         &scif0_device,
 250         &scif1_device,
 251         &scif2_device,
 252         &scif3_device,
 253         &cmt_device,
 254         &mtu2_device,
 255 };
 256
 257 static int __init sh7206_devices_setup(void)
 258 {
 259         return platform_add_devices(sh7206_devices,
 260                                     ARRAY_SIZE(sh7206_devices));
 261 }
 262 arch_initcall(sh7206_devices_setup);
 263
 264 void __init plat_irq_setup(void)
 265 {
 266         register_intc_controller(&intc_desc);
 267 }
 268
 269 static struct platform_device *sh7206_early_devices[] __initdata = {
 270         &scif0_device,
 271         &scif1_device,
 272         &scif2_device,
 273         &scif3_device,
 274         &cmt_device,
 275         &mtu2_device,
 276 };
 277
 278 #define STBCR3 0xfffe0408
 279 #define STBCR4 0xfffe040c
 280
 281 void __init plat_early_device_setup(void)
 282 {
 283         /* enable CMT clock */
 284         __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
 285
 286         /* enable MTU2 clock */
 287         __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
 288
 289         sh_early_platform_add_devices(sh7206_early_devices,
 290                                    ARRAY_SIZE(sh7206_early_devices));
 291 }