arch/sh/kernel/cpu/sh4a/clock-sh7734.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
   4  *
   5  * Clock framework for SH7734
   6  *
   7  * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   8  * Copyright (C) 2011, 2012 Renesas Solutions Corp.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/delay.h>
  16 #include <asm/clock.h>
  17 #include <asm/freq.h>
  18
  19 static struct clk extal_clk = {
  20         .rate       = 33333333,
  21 };
  22
  23 #define MODEMR          (0xFFCC0020)
  24 #define MODEMR_MASK     (0x6)
  25 #define MODEMR_533MHZ   (0x2)
  26
  27 static unsigned long pll_recalc(struct clk *clk)
  28 {
  29         int mode = 12;
  30         u32 r = __raw_readl(MODEMR);
  31
  32         if ((r & MODEMR_MASK) & MODEMR_533MHZ)
  33                 mode = 16;
  34
  35         return clk->parent->rate * mode;
  36 }
  37
  38 static struct sh_clk_ops pll_clk_ops = {
  39         .recalc         = pll_recalc,
  40 };
  41
  42 static struct clk pll_clk = {
  43         .ops        = &pll_clk_ops,
  44         .parent     = &extal_clk,
  45         .flags      = CLK_ENABLE_ON_INIT,
  46 };
  47
  48 static struct clk *main_clks[] = {
  49         &extal_clk,
  50         &pll_clk,
  51 };
  52
  53 static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
  54 static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };
  55
  56 static struct clk_div_mult_table div4_div_mult_table = {
  57         .divisors = divisors,
  58         .nr_divisors = ARRAY_SIZE(divisors),
  59         .multipliers = multipliers,
  60         .nr_multipliers = ARRAY_SIZE(multipliers),
  61 };
  62
  63 static struct clk_div4_table div4_table = {
  64         .div_mult_table = &div4_div_mult_table,
  65 };
  66
  67 enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };
  68
  69 #define DIV4(_reg, _bit, _mask, _flags) \
  70         SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
  71
  72 struct clk div4_clks[DIV4_NR] = {
  73         [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
  74         [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
  75         [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
  76         [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
  77         [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
  78         [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
  79 };
  80
  81 #define MSTPCR0 0xFFC80030
  82 #define MSTPCR1 0xFFC80034
  83 #define MSTPCR3 0xFFC8003C
  84
  85 enum {
  86         MSTP030, MSTP029, /* IIC */
  87         MSTP026, MSTP025, MSTP024, /* SCIF */
  88         MSTP023,
  89         MSTP022, MSTP021,
  90         MSTP019, /* HSCIF */
  91         MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
  92         MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */
  93         MSTP007, /* HSPI */
  94         MSTP115, /* ADMAC */
  95         MSTP114, /* GETHER */
  96         MSTP111, /* DMAC */
  97         MSTP109, /* VIDEOIN1 */
  98         MSTP108, /* VIDEOIN0 */
  99         MSTP107, /* RGPVBG */
 100         MSTP106, /* 2DG */
 101         MSTP103, /* VIEW */
 102         MSTP100, /* USB */
 103         MSTP331, /* MMC */
 104         MSTP330, /* MIMLB */
 105         MSTP323, /* SDHI0 */
 106         MSTP322, /* SDHI1 */
 107         MSTP321, /* SDHI2 */
 108         MSTP320, /* RQSPI */
 109         MSTP319, /* SRC0 */
 110         MSTP318, /* SRC1 */
 111         MSTP317, /* RSPI */
 112         MSTP316, /* RCAN0 */
 113         MSTP315, /* RCAN1 */
 114         MSTP314, /* FLTCL */
 115         MSTP313, /* ADC */
 116         MSTP312, /* MTU */
 117         MSTP304, /* IE-BUS */
 118         MSTP303, /* RTC */
 119         MSTP302, /* HIF */
 120         MSTP301, /* STIF0 */
 121         MSTP300, /* STIF1 */
 122         MSTP_NR };
 123
 124 static struct clk mstp_clks[MSTP_NR] = {
 125         /* MSTPCR0 */
 126         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
 127         [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
 128         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
 129         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
 130         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
 131         [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
 132         [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
 133         [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
 134         [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
 135         [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
 136         [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
 137         [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
 138         [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
 139         [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
 140         [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
 141         [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
 142         [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
 143         [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
 144
 145         /* MSTPCR1 */
 146         [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
 147         [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
 148         [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
 149         [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
 150         [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
 151         [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
 152         [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
 153         [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
 154         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
 155
 156         /* MSTPCR3 */
 157         [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
 158         [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
 159         [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
 160         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
 161         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
 162         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
 163         [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
 164         [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
 165         [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
 166         [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
 167         [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
 168         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
 169         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
 170         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
 171         [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  4, 0),
 172         [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  3, 0),
 173         [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  2, 0),
 174         [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  1, 0),
 175         [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  0, 0),
 176 };
 177
 178 static struct clk_lookup lookups[] = {
 179         /* main clocks */
 180         CLKDEV_CON_ID("extal", &extal_clk),
 181         CLKDEV_CON_ID("pll_clk", &pll_clk),
 182
 183         /* clocks */
 184         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 185         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
 186         CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
 187         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 188         CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
 189         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 190
 191         /* MSTP32 clocks */
 192         CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
 193         CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
 194         CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP026]),
 195         CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
 196         CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP024]),
 197         CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP023]),
 198         CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP022]),
 199         CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP021]),
 200         CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
 201         CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
 202         CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
 203         CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP014]),
 204         CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
 205         CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]),
 206         CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]),
 207         CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]),
 208         CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]),
 209         CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]),
 210         CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]),
 211         CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]),
 212         CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]),
 213         CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]),
 214         CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]),
 215         CLKDEV_CON_ID("view", &mstp_clks[MSTP103]),
 216
 217         CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]),
 218         CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]),
 219         CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]),
 220         CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]),
 221         CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]),
 222         CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]),
 223         CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]),
 224         CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]),
 225         CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]),
 226         CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]),
 227         CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]),
 228         CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]),
 229         CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]),
 230         CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]),
 231         CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]),
 232         CLKDEV_DEV_ID("sh7734-gether.0", &mstp_clks[MSTP114]),
 233         CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]),
 234         CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]),
 235         CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]),
 236         CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]),
 237 };
 238
 239 int __init arch_clk_init(void)
 240 {
 241         int i, ret = 0;
 242
 243         for (i = 0; i < ARRAY_SIZE(main_clks); i++)
 244                 ret |= clk_register(main_clks[i]);
 245
 246         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 247
 248         if (!ret)
 249                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 250                         &div4_table);
 251
 252         if (!ret)
 253                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 254
 255         return ret;
 256 }