?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'sched-urgent-2020-12-27' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / arch / sparc / kernel / leon_pci_grpci2.c
blobca22f93d904548071d631671a6fafe7dce2a06e2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * leon_pci_grpci2.c: GRPCI2 Host PCI driver
4 *
5 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
6 *
7 */
8
9 #include <linux/of_device.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/delay.h>
14 #include <linux/export.h>
15 #include <asm/io.h>
16 #include <asm/leon.h>
17 #include <asm/vaddrs.h>
18 #include <asm/sections.h>
19 #include <asm/leon_pci.h>
20
21 #include "irq.h"
22
23 struct grpci2_barcfg {
24 unsigned long pciadr; /* PCI Space Address */
25 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
26 };
27
28 /* Device Node Configuration options:
29 * - barcfgs : Custom Configuration of Host's 6 target BARs
30 * - irq_mask : Limit which PCI interrupts are enabled
31 * - do_reset : Force PCI Reset on startup
32 *
33 * barcfgs
34 * =======
35 *
36 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
37 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
38 *
39 * -1 means not configured (let host driver do default setup).
40 *
41 * [i*2+0] = PCI Address of BAR[i] on target interface
42 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
43 *
44 *
45 * irq_mask
46 * ========
47 *
48 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
49 * all are enabled. Use this when PCI interrupt pins are floating on PCB.
50 * int, len=4.
51 * bit0 = PCI INTA#
52 * bit1 = PCI INTB#
53 * bit2 = PCI INTC#
54 * bit3 = PCI INTD#
55 *
56 *
57 * reset
58 * =====
59 *
60 * Force PCI reset on startup. int, len=4
61 */
62
63 /* Enable Debugging Configuration Space Access */
64 #undef GRPCI2_DEBUG_CFGACCESS
65
66 /*
67 * GRPCI2 APB Register MAP
68 */
69 struct grpci2_regs {
70 unsigned int ctrl; /* 0x00 Control */
71 unsigned int sts_cap; /* 0x04 Status / Capabilities */
72 int res1; /* 0x08 */
73 unsigned int io_map; /* 0x0C I/O Map address */
74 unsigned int dma_ctrl; /* 0x10 DMA */
75 unsigned int dma_bdbase; /* 0x14 DMA */
76 int res2[2]; /* 0x18 */
77 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
78 int res3[2]; /* 0x38 */
79 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
80
81 /* PCI Trace Buffer Registers (OPTIONAL) */
82 unsigned int t_ctrl; /* 0x80 */
83 unsigned int t_cnt; /* 0x84 */
84 unsigned int t_adpat; /* 0x88 */
85 unsigned int t_admask; /* 0x8C */
86 unsigned int t_sigpat; /* 0x90 */
87 unsigned int t_sigmask; /* 0x94 */
88 unsigned int t_adstate; /* 0x98 */
89 unsigned int t_sigstate; /* 0x9C */
90 };
91
92 #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
93 #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
94
95 #define CTRL_BUS_BIT 16
96
97 #define CTRL_RESET (1<<31)
98 #define CTRL_SI (1<<27)
99 #define CTRL_PE (1<<26)
100 #define CTRL_EI (1<<25)
101 #define CTRL_ER (1<<24)
102 #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
103 #define CTRL_HOSTINT 0xf
104
105 #define STS_HOST_BIT 31
106 #define STS_MST_BIT 30
107 #define STS_TAR_BIT 29
108 #define STS_DMA_BIT 28
109 #define STS_DI_BIT 27
110 #define STS_HI_BIT 26
111 #define STS_IRQMODE_BIT 24
112 #define STS_TRACE_BIT 23
113 #define STS_CFGERRVALID_BIT 20
114 #define STS_CFGERR_BIT 19
115 #define STS_INTTYPE_BIT 12
116 #define STS_INTSTS_BIT 8
117 #define STS_FDEPTH_BIT 2
118 #define STS_FNUM_BIT 0
119
120 #define STS_HOST (1<<STS_HOST_BIT)
121 #define STS_MST (1<<STS_MST_BIT)
122 #define STS_TAR (1<<STS_TAR_BIT)
123 #define STS_DMA (1<<STS_DMA_BIT)
124 #define STS_DI (1<<STS_DI_BIT)
125 #define STS_HI (1<<STS_HI_BIT)
126 #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
127 #define STS_TRACE (1<<STS_TRACE_BIT)
128 #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
129 #define STS_CFGERR (1<<STS_CFGERR_BIT)
130 #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
131 #define STS_INTSTS (0xf<<STS_INTSTS_BIT)
132 #define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
133 #define STS_FNUM (0x3<<STS_FNUM_BIT)
134
135 #define STS_ISYSERR (1<<17)
136 #define STS_IDMA (1<<16)
137 #define STS_IDMAERR (1<<15)
138 #define STS_IMSTABRT (1<<14)
139 #define STS_ITGTABRT (1<<13)
140 #define STS_IPARERR (1<<12)
141
142 #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
143
144 struct grpci2_bd_chan {
145 unsigned int ctrl; /* 0x00 DMA Control */
146 unsigned int nchan; /* 0x04 Next DMA Channel Address */
147 unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
148 unsigned int res; /* 0x0C Reserved */
149 };
150
151 #define BD_CHAN_EN 0x80000000
152 #define BD_CHAN_TYPE 0x00300000
153 #define BD_CHAN_BDCNT 0x0000ffff
154 #define BD_CHAN_EN_BIT 31
155 #define BD_CHAN_TYPE_BIT 20
156 #define BD_CHAN_BDCNT_BIT 0
157
158 struct grpci2_bd_data {
159 unsigned int ctrl; /* 0x00 DMA Data Control */
160 unsigned int pci_adr; /* 0x04 PCI Start Address */
161 unsigned int ahb_adr; /* 0x08 AHB Start address */
162 unsigned int next; /* 0x0C Next Data Descriptor in chan */
163 };
164
165 #define BD_DATA_EN 0x80000000
166 #define BD_DATA_IE 0x40000000
167 #define BD_DATA_DR 0x20000000
168 #define BD_DATA_TYPE 0x00300000
169 #define BD_DATA_ER 0x00080000
170 #define BD_DATA_LEN 0x0000ffff
171 #define BD_DATA_EN_BIT 31
172 #define BD_DATA_IE_BIT 30
173 #define BD_DATA_DR_BIT 29
174 #define BD_DATA_TYPE_BIT 20
175 #define BD_DATA_ER_BIT 19
176 #define BD_DATA_LEN_BIT 0
177
178 /* GRPCI2 Capability */
179 struct grpci2_cap_first {
180 unsigned int ctrl;
181 unsigned int pci2ahb_map[6];
182 unsigned int ext2ahb_map;
183 unsigned int io_map;
184 unsigned int pcibar_size[6];
185 };
186 #define CAP9_CTRL_OFS 0
187 #define CAP9_BAR_OFS 0x4
188 #define CAP9_IOMAP_OFS 0x20
189 #define CAP9_BARSIZE_OFS 0x24
190
191 #define TGT 256
192
193 struct grpci2_priv {
194 struct leon_pci_info info; /* must be on top of this structure */
195 struct grpci2_regs __iomem *regs;
196 char irq;
197 char irq_mode; /* IRQ Mode from CAPSTS REG */
198 char bt_enabled;
199 char do_reset;
200 char irq_mask;
201 u32 pciid; /* PCI ID of Host */
202 unsigned char irq_map[4];
203
204 /* Virtual IRQ numbers */
205 unsigned int virq_err;
206 unsigned int virq_dma;
207
208 /* AHB PCI Windows */
209 unsigned long pci_area; /* MEMORY */
210 unsigned long pci_area_end;
211 unsigned long pci_io; /* I/O */
212 unsigned long pci_conf; /* CONFIGURATION */
213 unsigned long pci_conf_end;
214 unsigned long pci_io_va;
215
216 struct grpci2_barcfg tgtbars[6];
217 };
218
219 static DEFINE_SPINLOCK(grpci2_dev_lock);
220 static struct grpci2_priv *grpci2priv;
221
222 static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
223 {
224 struct grpci2_priv *priv = dev->bus->sysdata;
225 int irq_group;
226
227 /* Use default IRQ decoding on PCI BUS0 according slot numbering */
228 irq_group = slot & 0x3;
229 pin = ((pin - 1) + irq_group) & 0x3;
230
231 return priv->irq_map[pin];
232 }
233
234 static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
235 unsigned int devfn, int where, u32 *val)
236 {
237 unsigned int *pci_conf;
238 unsigned long flags;
239 u32 tmp;
240
241 if (where & 0x3)
242 return -EINVAL;
243
244 if (bus == 0) {
245 devfn += (0x8 * 6); /* start at AD16=Device0 */
246 } else if (bus == TGT) {
247 bus = 0;
248 devfn = 0; /* special case: bridge controller itself */
249 }
250
251 /* Select bus */
252 spin_lock_irqsave(&grpci2_dev_lock, flags);
253 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
254 (bus << 16));
255 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
256
257 /* clear old status */
258 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
259
260 pci_conf = (unsigned int *) (priv->pci_conf |
261 (devfn << 8) | (where & 0xfc));
262 tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
263
264 /* Wait until GRPCI2 signals that CFG access is done, it should be
265 * done instantaneously unless a DMA operation is ongoing...
266 */
267 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
268 ;
269
270 if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
271 *val = 0xffffffff;
272 } else {
273 /* Bus always little endian (unaffected by byte-swapping) */
274 *val = swab32(tmp);
275 }
276
277 return 0;
278 }
279
280 static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
281 unsigned int devfn, int where, u32 *val)
282 {
283 u32 v;
284 int ret;
285
286 if (where & 0x1)
287 return -EINVAL;
288 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
289 *val = 0xffff & (v >> (8 * (where & 0x3)));
290 return ret;
291 }
292
293 static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
294 unsigned int devfn, int where, u32 *val)
295 {
296 u32 v;
297 int ret;
298
299 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
300 *val = 0xff & (v >> (8 * (where & 3)));
301
302 return ret;
303 }
304
305 static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
306 unsigned int devfn, int where, u32 val)
307 {
308 unsigned int *pci_conf;
309 unsigned long flags;
310
311 if (where & 0x3)
312 return -EINVAL;
313
314 if (bus == 0) {
315 devfn += (0x8 * 6); /* start at AD16=Device0 */
316 } else if (bus == TGT) {
317 bus = 0;
318 devfn = 0; /* special case: bridge controller itself */
319 }
320
321 /* Select bus */
322 spin_lock_irqsave(&grpci2_dev_lock, flags);
323 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
324 (bus << 16));
325 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
326
327 /* clear old status */
328 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
329
330 pci_conf = (unsigned int *) (priv->pci_conf |
331 (devfn << 8) | (where & 0xfc));
332 LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
333
334 /* Wait until GRPCI2 signals that CFG access is done, it should be
335 * done instantaneously unless a DMA operation is ongoing...
336 */
337 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
338 ;
339
340 return 0;
341 }
342
343 static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
344 unsigned int devfn, int where, u32 val)
345 {
346 int ret;
347 u32 v;
348
349 if (where & 0x1)
350 return -EINVAL;
351 ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
352 if (ret)
353 return ret;
354 v = (v & ~(0xffff << (8 * (where & 0x3)))) |
355 ((0xffff & val) << (8 * (where & 0x3)));
356 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
357 }
358
359 static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
360 unsigned int devfn, int where, u32 val)
361 {
362 int ret;
363 u32 v;
364
365 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
366 if (ret != 0)
367 return ret;
368 v = (v & ~(0xff << (8 * (where & 0x3)))) |
369 ((0xff & val) << (8 * (where & 0x3)));
370 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
371 }
372
373 /* Read from Configuration Space. When entering here the PCI layer has taken
374 * the pci_lock spinlock and IRQ is off.
375 */
376 static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
377 int where, int size, u32 *val)
378 {
379 struct grpci2_priv *priv = grpci2priv;
380 unsigned int busno = bus->number;
381 int ret;
382
383 if (PCI_SLOT(devfn) > 15 || busno > 255) {
384 *val = ~0;
385 return 0;
386 }
387
388 switch (size) {
389 case 1:
390 ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
391 break;
392 case 2:
393 ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
394 break;
395 case 4:
396 ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
397 break;
398 default:
399 ret = -EINVAL;
400 break;
401 }
402
403 #ifdef GRPCI2_DEBUG_CFGACCESS
404 printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
405 "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
406 *val, size);
407 #endif
408
409 return ret;
410 }
411
412 /* Write to Configuration Space. When entering here the PCI layer has taken
413 * the pci_lock spinlock and IRQ is off.
414 */
415 static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
416 int where, int size, u32 val)
417 {
418 struct grpci2_priv *priv = grpci2priv;
419 unsigned int busno = bus->number;
420
421 if (PCI_SLOT(devfn) > 15 || busno > 255)
422 return 0;
423
424 #ifdef GRPCI2_DEBUG_CFGACCESS
425 printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
426 "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
427 where, size, val);
428 #endif
429
430 switch (size) {
431 default:
432 return -EINVAL;
433 case 1:
434 return grpci2_cfg_w8(priv, busno, devfn, where, val);
435 case 2:
436 return grpci2_cfg_w16(priv, busno, devfn, where, val);
437 case 4:
438 return grpci2_cfg_w32(priv, busno, devfn, where, val);
439 }
440 }
441
442 static struct pci_ops grpci2_ops = {
443 .read = grpci2_read_config,
444 .write = grpci2_write_config,
445 };
446
447 /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
448 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
449 * this is not needed and the standard IRQ controller can be used.
450 */
451
452 static void grpci2_mask_irq(struct irq_data *data)
453 {
454 unsigned long flags;
455 unsigned int irqidx;
456 struct grpci2_priv *priv = grpci2priv;
457
458 irqidx = (unsigned int)data->chip_data - 1;
459 if (irqidx > 3) /* only mask PCI interrupts here */
460 return;
461
462 spin_lock_irqsave(&grpci2_dev_lock, flags);
463 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
464 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
465 }
466
467 static void grpci2_unmask_irq(struct irq_data *data)
468 {
469 unsigned long flags;
470 unsigned int irqidx;
471 struct grpci2_priv *priv = grpci2priv;
472
473 irqidx = (unsigned int)data->chip_data - 1;
474 if (irqidx > 3) /* only unmask PCI interrupts here */
475 return;
476
477 spin_lock_irqsave(&grpci2_dev_lock, flags);
478 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
479 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
480 }
481
482 static unsigned int grpci2_startup_irq(struct irq_data *data)
483 {
484 grpci2_unmask_irq(data);
485 return 0;
486 }
487
488 static void grpci2_shutdown_irq(struct irq_data *data)
489 {
490 grpci2_mask_irq(data);
491 }
492
493 static struct irq_chip grpci2_irq = {
494 .name = "grpci2",
495 .irq_startup = grpci2_startup_irq,
496 .irq_shutdown = grpci2_shutdown_irq,
497 .irq_mask = grpci2_mask_irq,
498 .irq_unmask = grpci2_unmask_irq,
499 };
500
501 /* Handle one or multiple IRQs from the PCI core */
502 static void grpci2_pci_flow_irq(struct irq_desc *desc)
503 {
504 struct grpci2_priv *priv = grpci2priv;
505 int i, ack = 0;
506 unsigned int ctrl, sts_cap, pci_ints;
507
508 ctrl = REGLOAD(priv->regs->ctrl);
509 sts_cap = REGLOAD(priv->regs->sts_cap);
510
511 /* Error Interrupt? */
512 if (sts_cap & STS_ERR_IRQ) {
513 generic_handle_irq(priv->virq_err);
514 ack = 1;
515 }
516
517 /* PCI Interrupt? */
518 pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
519 if (pci_ints) {
520 /* Call respective PCI Interrupt handler */
521 for (i = 0; i < 4; i++) {
522 if (pci_ints & (1 << i))
523 generic_handle_irq(priv->irq_map[i]);
524 }
525 ack = 1;
526 }
527
528 /*
529 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
530 * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
531 * goes directly to DMA ISR.
532 */
533 if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
534 generic_handle_irq(priv->virq_dma);
535 ack = 1;
536 }
537
538 /*
539 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
540 * Controller, this must be done after IRQ sources have been handled to
541 * avoid double IRQ generation
542 */
543 if (ack)
544 desc->irq_data.chip->irq_eoi(&desc->irq_data);
545 }
546
547 /* Create a virtual IRQ */
548 static unsigned int grpci2_build_device_irq(unsigned int irq)
549 {
550 unsigned int virq = 0, pil;
551
552 pil = 1 << 8;
553 virq = irq_alloc(irq, pil);
554 if (virq == 0)
555 goto out;
556
557 irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
558 "pcilvl");
559 irq_set_chip_data(virq, (void *)irq);
560
561 out:
562 return virq;
563 }
564
565 static void grpci2_hw_init(struct grpci2_priv *priv)
566 {
567 u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
568 struct grpci2_regs __iomem *regs = priv->regs;
569 int i;
570 struct grpci2_barcfg *barcfg = priv->tgtbars;
571
572 /* Reset any earlier setup */
573 if (priv->do_reset) {
574 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
575 REGSTORE(regs->ctrl, CTRL_RESET);
576 ssleep(1); /* Wait for boards to settle */
577 }
578 REGSTORE(regs->ctrl, 0);
579 REGSTORE(regs->sts_cap, ~0); /* Clear Status */
580 REGSTORE(regs->dma_ctrl, 0);
581 REGSTORE(regs->dma_bdbase, 0);
582
583 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
584 REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
585
586 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
587 * Each AHB master has it's own mapping registers. Max 16 AHB masters.
588 */
589 for (i = 0; i < 16; i++)
590 REGSTORE(regs->ahbmst_map[i], priv->pci_area);
591
592 /* Get the GRPCI2 Host PCI ID */
593 grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
594
595 /* Get address to first (always defined) capability structure */
596 grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
597
598 /* Enable/Disable Byte twisting */
599 grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
600 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
601 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
602
603 /* Setup the Host's PCI Target BARs for other peripherals to access,
604 * and do DMA to the host's memory. The target BARs can be sized and
605 * enabled individually.
606 *
607 * User may set custom target BARs, but default is:
608 * The first BARs is used to map kernel low (DMA is part of normal
609 * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
610 * PCI bus, the other BARs are disabled. We assume that the first BAR
611 * is always available.
612 */
613 for (i = 0; i < 6; i++) {
614 if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
615 /* Target BARs must have the proper alignment */
616 ahbadr = barcfg[i].ahbadr;
617 pciadr = barcfg[i].pciadr;
618 bar_sz = ((pciadr - 1) & ~pciadr) + 1;
619 } else {
620 if (i == 0) {
621 /* Map main memory */
622 bar_sz = 0xf0000008; /* 256MB prefetchable */
623 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
624 (unsigned long) &_end));
625 pciadr = ahbadr;
626 } else {
627 bar_sz = 0;
628 ahbadr = 0;
629 pciadr = 0;
630 }
631 }
632 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
633 bar_sz);
634 grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
635 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
636 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
637 i, pciadr, ahbadr);
638 }
639
640 /* set as bus master and enable pci memory responses */
641 grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
642 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
643 grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
644
645 /* Enable Error respone (CPU-TRAP) on illegal memory access. */
646 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
647 }
648
649 static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
650 {
651 printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
652 return IRQ_NONE;
653 }
654
655 /* Handle GRPCI2 Error Interrupt */
656 static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
657 {
658 struct grpci2_priv *priv = arg;
659 struct grpci2_regs __iomem *regs = priv->regs;
660 unsigned int status;
661
662 status = REGLOAD(regs->sts_cap);
663 if ((status & STS_ERR_IRQ) == 0)
664 return IRQ_NONE;
665
666 if (status & STS_IPARERR)
667 printk(KERN_ERR "GRPCI2: Parity Error\n");
668
669 if (status & STS_ITGTABRT)
670 printk(KERN_ERR "GRPCI2: Target Abort\n");
671
672 if (status & STS_IMSTABRT)
673 printk(KERN_ERR "GRPCI2: Master Abort\n");
674
675 if (status & STS_ISYSERR)
676 printk(KERN_ERR "GRPCI2: System Error\n");
677
678 /* Clear handled INT TYPE IRQs */
679 REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
680
681 return IRQ_HANDLED;
682 }
683
684 static int grpci2_of_probe(struct platform_device *ofdev)
685 {
686 struct grpci2_regs __iomem *regs;
687 struct grpci2_priv *priv;
688 int err, i, len;
689 const int *tmp;
690 unsigned int capability;
691
692 if (grpci2priv) {
693 printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
694 return -ENODEV;
695 }
696
697 if (ofdev->num_resources < 3) {
698 printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
699 return -EIO;
700 }
701
702 /* Find Device Address */
703 regs = of_ioremap(&ofdev->resource[0], 0,
704 resource_size(&ofdev->resource[0]),
705 "grlib-grpci2 regs");
706 if (regs == NULL) {
707 printk(KERN_ERR "GRPCI2: ioremap failed\n");
708 return -EIO;
709 }
710
711 /*
712 * Check that we're in Host Slot and that we can act as a Host Bridge
713 * and not only as target.
714 */
715 capability = REGLOAD(regs->sts_cap);
716 if ((capability & STS_HOST) || !(capability & STS_MST)) {
717 printk(KERN_INFO "GRPCI2: not in host system slot\n");
718 err = -EIO;
719 goto err1;
720 }
721
722 priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
723 if (grpci2priv == NULL) {
724 err = -ENOMEM;
725 goto err1;
726 }
727 priv->regs = regs;
728 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
729 priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
730
731 printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
732
733 /* Byte twisting should be made configurable from kernel command line */
734 priv->bt_enabled = 1;
735
736 /* Let user do custom Target BAR assignment */
737 tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
738 if (tmp && (len == 2*4*6))
739 memcpy(priv->tgtbars, tmp, 2*4*6);
740 else
741 memset(priv->tgtbars, -1, 2*4*6);
742
743 /* Limit IRQ unmasking in irq_mode 2 and 3 */
744 tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
745 if (tmp && (len == 4))
746 priv->do_reset = *tmp;
747 else
748 priv->irq_mask = 0xf;
749
750 /* Optional PCI reset. Force PCI reset on startup */
751 tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
752 if (tmp && (len == 4))
753 priv->do_reset = *tmp;
754 else
755 priv->do_reset = 0;
756
757 /* Find PCI Memory, I/O and Configuration Space Windows */
758 priv->pci_area = ofdev->resource[1].start;
759 priv->pci_area_end = ofdev->resource[1].end+1;
760 priv->pci_io = ofdev->resource[2].start;
761 priv->pci_conf = ofdev->resource[2].start + 0x10000;
762 priv->pci_conf_end = priv->pci_conf + 0x10000;
763 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
764 if (!priv->pci_io_va) {
765 err = -EIO;
766 goto err2;
767 }
768
769 printk(KERN_INFO
770 "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
771 " I/O SPACE [0x%08lx - 0x%08lx]\n"
772 " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
773 priv->pci_area, priv->pci_area_end-1,
774 priv->pci_io, priv->pci_conf-1,
775 priv->pci_conf, priv->pci_conf_end-1);
776
777 /*
778 * I/O Space resources in I/O Window mapped into Virtual Adr Space
779 * We never use low 4KB because some devices seem have problems using
780 * address 0.
781 */
782 memset(&priv->info.io_space, 0, sizeof(struct resource));
783 priv->info.io_space.name = "GRPCI2 PCI I/O Space";
784 priv->info.io_space.start = priv->pci_io_va + 0x1000;
785 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
786 priv->info.io_space.flags = IORESOURCE_IO;
787
788 /*
789 * GRPCI2 has no prefetchable memory, map everything as
790 * non-prefetchable memory
791 */
792 memset(&priv->info.mem_space, 0, sizeof(struct resource));
793 priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
794 priv->info.mem_space.start = priv->pci_area;
795 priv->info.mem_space.end = priv->pci_area_end - 1;
796 priv->info.mem_space.flags = IORESOURCE_MEM;
797
798 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
799 goto err3;
800 if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
801 goto err4;
802
803 /* setup maximum supported PCI buses */
804 priv->info.busn.name = "GRPCI2 busn";
805 priv->info.busn.start = 0;
806 priv->info.busn.end = 255;
807
808 grpci2_hw_init(priv);
809
810 /*
811 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
812 * Error IRQ always on PCI INTA.
813 */
814 if (priv->irq_mode < 2) {
815 /* All PCI interrupts are shared using the same system IRQ */
816 leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
817 "pcilvl", 0);
818
819 priv->irq_map[0] = grpci2_build_device_irq(1);
820 priv->irq_map[1] = grpci2_build_device_irq(2);
821 priv->irq_map[2] = grpci2_build_device_irq(3);
822 priv->irq_map[3] = grpci2_build_device_irq(4);
823
824 priv->virq_err = grpci2_build_device_irq(5);
825 if (priv->irq_mode & 1)
826 priv->virq_dma = ofdev->archdata.irqs[1];
827 else
828 priv->virq_dma = grpci2_build_device_irq(6);
829
830 /* Enable IRQs on LEON IRQ controller */
831 err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
832 "GRPCI2_JUMP", priv);
833 if (err)
834 printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
835 } else {
836 /* All PCI interrupts have an unique IRQ interrupt */
837 for (i = 0; i < 4; i++) {
838 /* Make LEON IRQ layer handle level IRQ by acking */
839 leon_update_virq_handling(ofdev->archdata.irqs[i],
840 handle_fasteoi_irq, "pcilvl",
841 1);
842 priv->irq_map[i] = ofdev->archdata.irqs[i];
843 }
844 priv->virq_err = priv->irq_map[0];
845 if (priv->irq_mode & 1)
846 priv->virq_dma = ofdev->archdata.irqs[4];
847 else
848 priv->virq_dma = priv->irq_map[0];
849
850 /* Unmask all PCI interrupts, request_irq will not do that */
851 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
852 }
853
854 /* Setup IRQ handler for non-configuration space access errors */
855 err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
856 "GRPCI2_ERR", priv);
857 if (err) {
858 printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
859 goto err5;
860 }
861
862 /*
863 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
864 * is called by the PCI Device drivers
865 */
866 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
867
868 /* Init common layer and scan buses */
869 priv->info.ops = &grpci2_ops;
870 priv->info.map_irq = grpci2_map_irq;
871 leon_pci_init(ofdev, &priv->info);
872
873 return 0;
874
875 err5:
876 release_resource(&priv->info.io_space);
877 err4:
878 release_resource(&priv->info.mem_space);
879 err3:
880 err = -ENOMEM;
881 iounmap((void __iomem *)priv->pci_io_va);
882 err2:
883 kfree(priv);
884 err1:
885 of_iounmap(&ofdev->resource[0], regs,
886 resource_size(&ofdev->resource[0]));
887 return err;
888 }
889
890 static const struct of_device_id grpci2_of_match[] __initconst = {
891 {
892 .name = "GAISLER_GRPCI2",
893 },
894 {
895 .name = "01_07c",
896 },
897 {},
898 };
899
900 static struct platform_driver grpci2_of_driver = {
901 .driver = {
902 .name = "grpci2",
903 .of_match_table = grpci2_of_match,
904 },
905 .probe = grpci2_of_probe,
906 };
907
908 static int __init grpci2_init(void)
909 {
910 return platform_driver_register(&grpci2_of_driver);
911 }
912
913 subsys_initcall(grpci2_init);
Linux with added FPC-III support