arch/x86/pci/intel_mid_pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel MID PCI support
   4  *   Copyright (c) 2008 Intel Corporation
   5  *     Jesse Barnes <jesse.barnes@intel.com>
   6  *
   7  * Moorestown has an interesting PCI implementation:
   8  *   - configuration space is memory mapped (as defined by MCFG)
   9  *   - Lincroft devices also have a real, type 1 configuration space
  10  *   - Early Lincroft silicon has a type 1 access bug that will cause
  11  *     a hang if non-existent devices are accessed
  12  *   - some devices have the "fixed BAR" capability, which means
  13  *     they can't be relocated or modified; check for that during
  14  *     BAR sizing
  15  *
  16  * So, we use the MCFG space for all reads and writes, but also send
  17  * Lincroft writes to type 1 space.  But only read/write if the device
  18  * actually exists, otherwise return all 1s for reads and bit bucket
  19  * the writes.
  20  */
  21
  22 #include <linux/sched.h>
  23 #include <linux/pci.h>
  24 #include <linux/ioport.h>
  25 #include <linux/init.h>
  26 #include <linux/dmi.h>
  27 #include <linux/acpi.h>
  28 #include <linux/io.h>
  29 #include <linux/smp.h>
  30
  31 #include <asm/segment.h>
  32 #include <asm/pci_x86.h>
  33 #include <asm/hw_irq.h>
  34 #include <asm/io_apic.h>
  35 #include <asm/intel-mid.h>
  36 #include <asm/acpi.h>
  37
  38 #define PCIE_CAP_OFFSET 0x100
  39
  40 /* Quirks for the listed devices */
  41 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC   0x1190
  42 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU   0x1191
  43
  44 /* Fixed BAR fields */
  45 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
  46 #define PCI_FIXED_BAR_0_SIZE    0x04
  47 #define PCI_FIXED_BAR_1_SIZE    0x08
  48 #define PCI_FIXED_BAR_2_SIZE    0x0c
  49 #define PCI_FIXED_BAR_3_SIZE    0x10
  50 #define PCI_FIXED_BAR_4_SIZE    0x14
  51 #define PCI_FIXED_BAR_5_SIZE    0x1c
  52
  53 static int pci_soc_mode;
  54
  55 /**
  56  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  57  * @bus: PCI bus
  58  * @devfn: device in question
  59  *
  60  * Look for the fixed BAR cap on @bus and @devfn, returning its offset
  61  * if found or 0 otherwise.
  62  */
  63 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
  64 {
  65         int pos;
  66         u32 pcie_cap = 0, cap_data;
  67
  68         pos = PCIE_CAP_OFFSET;
  69
  70         if (!raw_pci_ext_ops)
  71                 return 0;
  72
  73         while (pos) {
  74                 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  75                                           devfn, pos, 4, &pcie_cap))
  76                         return 0;
  77
  78                 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
  79                         PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
  80                         break;
  81
  82                 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
  83                         raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  84                                               devfn, pos + 4, 4, &cap_data);
  85                         if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
  86                                 return pos;
  87                 }
  88
  89                 pos = PCI_EXT_CAP_NEXT(pcie_cap);
  90         }
  91
  92         return 0;
  93 }
  94
  95 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
  96                                    int reg, int len, u32 val, int offset)
  97 {
  98         u32 size;
  99         unsigned int domain, busnum;
 100         int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
 101
 102         domain = pci_domain_nr(bus);
 103         busnum = bus->number;
 104
 105         if (val == ~0 && len == 4) {
 106                 unsigned long decode;
 107
 108                 raw_pci_ext_ops->read(domain, busnum, devfn,
 109                                offset + 8 + (bar * 4), 4, &size);
 110
 111                 /* Turn the size into a decode pattern for the sizing code */
 112                 if (size) {
 113                         decode = size - 1;
 114                         decode |= decode >> 1;
 115                         decode |= decode >> 2;
 116                         decode |= decode >> 4;
 117                         decode |= decode >> 8;
 118                         decode |= decode >> 16;
 119                         decode++;
 120                         decode = ~(decode - 1);
 121                 } else {
 122                         decode = 0;
 123                 }
 124
 125                 /*
 126                  * If val is all ones, the core code is trying to size the reg,
 127                  * so update the mmconfig space with the real size.
 128                  *
 129                  * Note: this assumes the fixed size we got is a power of two.
 130                  */
 131                 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
 132                                        decode);
 133         }
 134
 135         /* This is some other kind of BAR write, so just do it. */
 136         return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
 137 }
 138
 139 /**
 140  * type1_access_ok - check whether to use type 1
 141  * @bus: bus number
 142  * @devfn: device & function in question
 143  *
 144  * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
 145  * all, the we can go ahead with any reads & writes.  If it's on a Lincroft,
 146  * but doesn't exist, avoid the access altogether to keep the chip from
 147  * hanging.
 148  */
 149 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
 150 {
 151         /*
 152          * This is a workaround for A0 LNC bug where PCI status register does
 153          * not have new CAP bit set. can not be written by SW either.
 154          *
 155          * PCI header type in real LNC indicates a single function device, this
 156          * will prevent probing other devices under the same function in PCI
 157          * shim. Therefore, use the header type in shim instead.
 158          */
 159         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
 160                 return false;
 161         if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
 162                                 || devfn == PCI_DEVFN(0, 0)
 163                                 || devfn == PCI_DEVFN(3, 0)))
 164                 return true;
 165         return false; /* Langwell on others */
 166 }
 167
 168 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 169                     int size, u32 *value)
 170 {
 171         if (type1_access_ok(bus->number, devfn, where))
 172                 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
 173                                         devfn, where, size, value);
 174         return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
 175                               devfn, where, size, value);
 176 }
 177
 178 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 179                      int size, u32 value)
 180 {
 181         int offset;
 182
 183         /*
 184          * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
 185          * to ROM BAR return 0 then being ignored.
 186          */
 187         if (where == PCI_ROM_ADDRESS)
 188                 return 0;
 189
 190         /*
 191          * Devices with fixed BARs need special handling:
 192          *   - BAR sizing code will save, write ~0, read size, restore
 193          *   - so writes to fixed BARs need special handling
 194          *   - other writes to fixed BAR devices should go through mmconfig
 195          */
 196         offset = fixed_bar_cap(bus, devfn);
 197         if (offset &&
 198             (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
 199                 return pci_device_update_fixed(bus, devfn, where, size, value,
 200                                                offset);
 201         }
 202
 203         /*
 204          * On Moorestown update both real & mmconfig space
 205          * Note: early Lincroft silicon can't handle type 1 accesses to
 206          *       non-existent devices, so just eat the write in that case.
 207          */
 208         if (type1_access_ok(bus->number, devfn, where))
 209                 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
 210                                               devfn, where, size, value);
 211         return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
 212                                where, size, value);
 213 }
 214
 215 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 216 {
 217         struct irq_alloc_info info;
 218         bool polarity_low;
 219         int ret;
 220         u8 gsi;
 221
 222         if (dev->irq_managed && dev->irq > 0)
 223                 return 0;
 224
 225         ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
 226         if (ret < 0) {
 227                 dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret);
 228                 return ret;
 229         }
 230
 231         switch (intel_mid_identify_cpu()) {
 232         case INTEL_MID_CPU_CHIP_TANGIER:
 233                 polarity_low = false;
 234
 235                 /* Special treatment for IRQ0 */
 236                 if (gsi == 0) {
 237                         /*
 238                          * Skip HS UART common registers device since it has
 239                          * IRQ0 assigned and not used by the kernel.
 240                          */
 241                         if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
 242                                 return -EBUSY;
 243                         /*
 244                          * TNG has IRQ0 assigned to eMMC controller. But there
 245                          * are also other devices with bogus PCI configuration
 246                          * that have IRQ0 assigned. This check ensures that
 247                          * eMMC gets it. The rest of devices still could be
 248                          * enabled without interrupt line being allocated.
 249                          */
 250                         if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
 251                                 return 0;
 252                 }
 253                 break;
 254         default:
 255                 polarity_low = true;
 256                 break;
 257         }
 258
 259         ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low);
 260
 261         /*
 262          * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 263          * IOAPIC RTE entries, so we just enable RTE for the device.
 264          */
 265         ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
 266         if (ret < 0)
 267                 return ret;
 268
 269         dev->irq = ret;
 270         dev->irq_managed = 1;
 271
 272         return 0;
 273 }
 274
 275 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 276 {
 277         if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
 278             dev->irq > 0) {
 279                 mp_unmap_irq(dev->irq);
 280                 dev->irq_managed = 0;
 281         }
 282 }
 283
 284 static const struct pci_ops intel_mid_pci_ops __initconst = {
 285         .read = pci_read,
 286         .write = pci_write,
 287 };
 288
 289 /**
 290  * intel_mid_pci_init - installs intel_mid_pci_ops
 291  *
 292  * Moorestown has an interesting PCI implementation (see above).
 293  * Called when the early platform detection installs it.
 294  */
 295 int __init intel_mid_pci_init(void)
 296 {
 297         pr_info("Intel MID platform detected, using MID PCI ops\n");
 298         pci_mmcfg_late_init();
 299         pcibios_enable_irq = intel_mid_pci_irq_enable;
 300         pcibios_disable_irq = intel_mid_pci_irq_disable;
 301         pci_root_ops = intel_mid_pci_ops;
 302         pci_soc_mode = 1;
 303         /* Continue with standard init */
 304         acpi_noirq_set();
 305         return 1;
 306 }
 307
 308 /*
 309  * Langwell devices are not true PCI devices; they are not subject to 10 ms
 310  * d3 to d0 delay required by PCI spec.
 311  */
 312 static void pci_d3delay_fixup(struct pci_dev *dev)
 313 {
 314         /*
 315          * PCI fixups are effectively decided compile time. If we have a dual
 316          * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
 317          */
 318         if (!pci_soc_mode)
 319                 return;
 320         /*
 321          * True PCI devices in Lincroft should allow type 1 access, the rest
 322          * are Langwell fake PCI devices.
 323          */
 324         if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
 325                 return;
 326         dev->d3hot_delay = 0;
 327 }
 328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
 329
 330 static void mid_power_off_one_device(struct pci_dev *dev)
 331 {
 332         u16 pmcsr;
 333
 334         /*
 335          * Update current state first, otherwise PCI core enforces PCI_D0 in
 336          * pci_set_power_state() for devices which status was PCI_UNKNOWN.
 337          */
 338         pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 339         dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
 340
 341         pci_set_power_state(dev, PCI_D3hot);
 342 }
 343
 344 static void mid_power_off_devices(struct pci_dev *dev)
 345 {
 346         int id;
 347
 348         if (!pci_soc_mode)
 349                 return;
 350
 351         id = intel_mid_pwr_get_lss_id(dev);
 352         if (id < 0)
 353                 return;
 354
 355         /*
 356          * This sets only PMCSR bits. The actual power off will happen in
 357          * arch/x86/platform/intel-mid/pwr.c.
 358          */
 359         mid_power_off_one_device(dev);
 360 }
 361
 362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
 363
 364 /*
 365  * Langwell devices reside at fixed offsets, don't try to move them.
 366  */
 367 static void pci_fixed_bar_fixup(struct pci_dev *dev)
 368 {
 369         unsigned long offset;
 370         u32 size;
 371         int i;
 372
 373         if (!pci_soc_mode)
 374                 return;
 375
 376         /* Must have extended configuration space */
 377         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
 378                 return;
 379
 380         /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
 381         offset = fixed_bar_cap(dev->bus, dev->devfn);
 382         if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
 383             PCI_DEVFN(2, 2) == dev->devfn)
 384                 return;
 385
 386         for (i = 0; i < PCI_STD_NUM_BARS; i++) {
 387                 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
 388                 dev->resource[i].end = dev->resource[i].start + size - 1;
 389                 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
 390         }
 391 }
 392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);